gen5200/ata/idecfg.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * RTEMS generic MPC5200 BSP
0005  *
0006  * This file contains the IDE configuration.
0007  */
0008
0009 /*
0010  * Copyright (c) 2005 embedded brains GmbH & Co. KG
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #include <rtems.h>
0035 #include <bsp.h>
0036 #include <bsp/irq.h>
0037 #include <bsp/mpc5200.h>
0038 #include "./pcmcia_ide.h"
0039
0040 #include <libchip/ide_ctrl.h>
0041 #include <libchip/ide_ctrl_cfg.h>
0042 #include <libchip/ide_ctrl_io.h>
0043
0044 /*
0045  * The following table configures the IDE driver used in this BSP.
0046  */
0047 extern ide_ctrl_fns_t mpc5200_pcmciaide_ctrl_fns;
0048
0049 volatile uint32_t * mpc5200_ata_drive_regs[] =
0050   {
0051   (uint32_t *)&(mpc5200.ata_ddr),       /* data (offset 0x00)                */
0052   (uint32_t *)&(mpc5200.ata_dfr_der),   /* features / error (offset 0x01)    */
0053   (uint32_t *)&(mpc5200.ata_dscr),      /* sector count (offset 0x02)        */
0054   (uint32_t *)&(mpc5200.ata_dsnr),      /* sector no.   / lba0 (offset 0x03) */
0055   (uint32_t *)&(mpc5200.ata_dclr),      /* cylinder low / lba1 (offset 0x04) */
0056   (uint32_t *)&(mpc5200.ata_dchr),      /* cylinder high/ lba2 (offset 0x05) */
0057   (uint32_t *)&(mpc5200.ata_ddhr),      /* device head  / lba3 (offset 0x06) */
0058   (uint32_t *)&(mpc5200.ata_dcr_dsr),   /* command /status (offset 0x07)     */
0059
0060   (uint32_t *)&(mpc5200.ata_dctr_dasr), /* device control / alternate status (offset 0x08) */
0061   (uint32_t *)&(mpc5200.ata_ddr),       /* (offset 0x09) */
0062   (uint32_t *)&(mpc5200.ata_ddr),       /* (offset 0x0A) */
0063   NULL,                                 /* (offset 0x0B) */
0064   NULL,                                 /* (offset 0x0C) */
0065   NULL,                                 /* (offset 0x0D) */
0066   NULL,                                 /* (offset 0x0E) */
0067   NULL                                  /* (offset 0x0F) */
0068   };
0069
0070 /* IDE controllers Table */
0071 ide_controller_bsp_table_t IDE_Controller_Table[] =
0072   {
0073     {
0074     "/dev/idepcmcia",
0075     IDE_CUSTOM,                                        /* PCMCIA Flash cards emulate custom IDE controller */
0076     &mpc5200_pcmciaide_ctrl_fns,                       /* pointer to function set used for IDE drivers in this BSP */
0077     NULL,                                              /* no BSP dependent probe needed */
0078     FALSE,                                             /* not (yet) initialized */
0079     (uint32_t)0,                                     /* no port address but custom reg.set in params is used */
0080 #ifdef ATA_USE_INT
0081     TRUE,                                              /* interrupt driven */
0082 #else
0083     FALSE,                                             /* non interrupt driven     */
0084 #endif
0085     BSP_SIU_IRQ_ATA,                                   /* interrupt vector         */
0086     NULL                                               /* no additional parameters */
0087     }
0088 };
0089
0090 /* Number of rows in IDE_Controller_Table */
0091 unsigned long IDE_Controller_Count = sizeof(IDE_Controller_Table)/sizeof(IDE_Controller_Table[0]);
0092
0093 uint32_t ata_pio_timings[2][6] =
0094  {
0095    /* PIO3 timings in nanosconds */
0096    {
0097    180, /* t0 cycle time */
0098    80,  /* t2 DIOR-/DIOW pulse width 8 bit */
0099    80,  /* t1 DIOR-/DIOW pulse width 16 bit */
0100    10,  /* t4 DIOW- data hold */
0101    30,  /* t1 Addr.valid to DIOR-/DIOW setup */
0102    35,  /* ta IORDY setup time */
0103    },
0104    /* PIO4 timings in nanosconds */
0105    {
0106    120, /* t0 cycle time */
0107    70,  /* t1 DIOR-/DIOW pulse width 8 bit */
0108    70,  /* t1 DIOR-/DIOW pulse width 16 bit */
0109    10,  /* t4 DIOW- data hold */
0110    25,  /* t1 Addr.valid to DIOR-/DIOW setup */
0111    35,  /* ta IORDY setup time */
0112    }
0113  };
0114
0115