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File indexing completed on 2025-05-11 08:23:51
0001 /* $NetBSD: gtreg.h,v 1.2 2005/02/27 00:27:21 perry Exp $ */ 0002 0003 /* 0004 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 0005 * All rights reserved. * 0006 * Redistribution and use in source and binary forms, with or without 0007 * modification, are permitted provided that the following conditions 0008 * are met: 0009 * 1. Redistributions of source code must retain the above copyright 0010 * notice, this list of conditions and the following disclaimer. 0011 * 2. Redistributions in binary form must reproduce the above copyright 0012 * notice, this list of conditions and the following disclaimer in the 0013 * documentation and/or other materials provided with the distribution. 0014 * 3. All advertising materials mentioning features or use of this software 0015 * must display the following acknowledgement: 0016 * This product includes software developed for the NetBSD Project by 0017 * Allegro Networks, Inc., and Wasabi Systems, Inc. 0018 * 4. The name of Allegro Networks, Inc. may not be used to endorse 0019 * or promote products derived from this software without specific prior 0020 * written permission. 0021 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 0022 * or promote products derived from this software without specific prior 0023 * written permission. 0024 * 0025 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 0026 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 0027 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 0028 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 0029 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 0030 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0031 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0032 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0033 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0034 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0035 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0036 * POSSIBILITY OF SUCH DAMAGE. 0037 */ 0038 0039 #ifndef _DISCOVERY_DEV_GTREG_H_ 0040 #define _DISCOVERY_DEV_GTREG_H_ 0041 0042 0043 #define GT__BIT(bit) (1U << (bit)) 0044 #define GT__MASK(bit) (GT__BIT(bit) - 1) 0045 #define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len)) 0046 #define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit))) 0047 #define GT__INS(new, bit) ((new) << (bit)) 0048 0049 0050 /* 0051 * Table 30: CPU Address Decode Register Map 0052 */ 0053 #define GT_SCS0_Low_Decode 0x0008 0054 #define GT_SCS0_High_Decode 0x0010 0055 #define GT_SCS1_Low_Decode 0x0208 0056 #define GT_SCS1_High_Decode 0x0210 0057 #define GT_SCS2_Low_Decode 0x0018 0058 #define GT_SCS2_High_Decode 0x0020 0059 #define GT_SCS3_Low_Decode 0x0218 0060 #define GT_SCS3_High_Decode 0x0220 0061 #define GT_CS0_Low_Decode 0x0028 0062 #define GT_CS0_High_Decode 0x0030 0063 #define GT_CS1_Low_Decode 0x0228 0064 #define GT_CS1_High_Decode 0x0230 0065 #define GT_CS2_Low_Decode 0x0248 0066 #define GT_CS2_High_Decode 0x0250 0067 #define GT_CS3_Low_Decode 0x0038 0068 #define GT_CS3_High_Decode 0x0040 0069 #define GT_BootCS_Low_Decode 0x0238 0070 #define GT_BootCS_High_Decode 0x0240 0071 #define GT_PCI0_IO_Low_Decode 0x0048 0072 #define GT_PCI0_IO_High_Decode 0x0050 0073 #define GT_PCI0_Mem0_Low_Decode 0x0058 0074 #define GT_PCI0_Mem0_High_Decode 0x0060 0075 #define GT_PCI0_Mem1_Low_Decode 0x0080 0076 #define GT_PCI0_Mem1_High_Decode 0x0088 0077 #define GT_PCI0_Mem2_Low_Decode 0x0258 0078 #define GT_PCI0_Mem2_High_Decode 0x0260 0079 #define GT_PCI0_Mem3_Low_Decode 0x0280 0080 #define GT_PCI0_Mem3_High_Decode 0x0288 0081 #define GT_PCI1_IO_Low_Decode 0x0090 0082 #define GT_PCI1_IO_High_Decode 0x0098 0083 #define GT_PCI1_Mem0_Low_Decode 0x00a0 0084 #define GT_PCI1_Mem0_High_Decode 0x00a8 0085 #define GT_PCI1_Mem1_Low_Decode 0x00b0 0086 #define GT_PCI1_Mem1_High_Decode 0x00b8 0087 #define GT_PCI1_Mem2_Low_Decode 0x02a0 0088 #define GT_PCI1_Mem2_High_Decode 0x02a8 0089 #define GT_PCI1_Mem3_Low_Decode 0x02b0 0090 #define GT_PCI1_Mem3_High_Decode 0x02b8 0091 #define GT_Internal_Decode 0x0068 0092 #define GT_CPU0_Low_Decode 0x0290 0093 #define GT_CPU0_High_Decode 0x0298 0094 #define GT_CPU1_Low_Decode 0x02c0 0095 #define GT_CPU1_High_Decode 0x02c8 0096 /* ts, 2005/8: it seems that these are implicitely written 0097 * when setting the 'Low_Decode' regs... 0098 */ 0099 #define GT_PCI0_IO_Remap 0x00f0 0100 #define GT_PCI0_Mem0_Remap_Low 0x00f8 0101 #define GT_PCI0_Mem0_Remap_High 0x0320 0102 #define GT_PCI0_Mem1_Remap_Low 0x0100 0103 #define GT_PCI0_Mem1_Remap_High 0x0328 0104 #define GT_PCI0_Mem2_Remap_Low 0x02f8 0105 #define GT_PCI0_Mem2_Remap_High 0x0330 0106 #define GT_PCI0_Mem3_Remap_Low 0x0300 0107 #define GT_PCI0_Mem3_Remap_High 0x0338 0108 #define GT_PCI1_IO_Remap 0x0108 0109 #define GT_PCI1_Mem0_Remap_Low 0x0110 0110 #define GT_PCI1_Mem0_Remap_High 0x0340 0111 #define GT_PCI1_Mem1_Remap_Low 0x0118 0112 #define GT_PCI1_Mem1_Remap_High 0x0348 0113 #define GT_PCI1_Mem2_Remap_Low 0x0310 0114 #define GT_PCI1_Mem2_Remap_High 0x0350 0115 #define GT_PCI1_Mem3_Remap_Low 0x0318 0116 #define GT_PCI1_Mem3_Remap_High 0x0358 0117 0118 0119 /* 0120 * Table 31: CPU Control Register Map 0121 */ 0122 #define GT_CPU_Cfg 0x0000 0123 #define GT_CPU_Mode 0x0120 0124 #define GT_CPU_Master_Ctl 0x0160 0125 #define GT_CPU_If_Xbar_Ctl_Low 0x0150 0126 #define GT_CPU_If_Xbar_Ctl_High 0x0158 0127 #define GT_CPU_If_Xbar_Timeout 0x0168 0128 #define GT_260_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170 0129 #define GT_260_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178 0130 0131 /* 0132 * Table 32: CPU Sync Barrier Register Map 0133 */ 0134 #define GT_260_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3)) 0135 #define GT_260_PCI0_Sync_Barrier 0x00c0 0136 #define GT_260_PCI1_Sync_Barrier 0x00c8 0137 0138 /* 0139 * Table 33: CPU Access Protection Register Map 0140 */ 0141 #define GT_Protect_Low_0 0x0180 0142 #define GT_Protect_High_0 0x0188 0143 #define GT_Protect_Low_1 0x0190 0144 #define GT_Protect_High_1 0x0198 0145 #define GT_Protect_Low_2 0x01a0 0146 #define GT_Protect_High_2 0x01a8 0147 #define GT_Protect_Low_3 0x01b0 0148 #define GT_Protect_High_3 0x01b8 0149 #define GT_260_Protect_Low_4 0x01c0 0150 #define GT_260_Protect_High_4 0x01c8 0151 #define GT_260_Protect_Low_5 0x01d0 0152 #define GT_260_Protect_High_5 0x01d8 0153 #define GT_260_Protect_Low_6 0x01e0 0154 #define GT_260_Protect_High_6 0x01e8 0155 #define GT_260_Protect_Low_7 0x01f0 0156 #define GT_260_Protect_High_7 0x01f8 0157 0158 /* 0159 * Table 34: Snoop Control Register Map 0160 */ 0161 #define GT_260_Snoop_Base_0 0x0380 0162 #define GT_260_Snoop_Top_0 0x0388 0163 #define GT_260_Snoop_Base_1 0x0390 0164 #define GT_260_Snoop_Top_1 0x0398 0165 #define GT_260_Snoop_Base_2 0x03a0 0166 #define GT_260_Snoop_Top_2 0x03a8 0167 #define GT_260_Snoop_Base_3 0x03b0 0168 #define GT_260_Snoop_Top_3 0x03b8 0169 0170 /* 0171 * Table 35: CPU Error Report Register Map 0172 */ 0173 #define GT_CPU_Error_Address_Low 0x0070 0174 #define GT_CPU_Error_Address_High 0x0078 0175 #define GT_CPU_Error_Data_Low 0x0128 0176 #define GT_CPU_Error_Data_High 0x0130 0177 #define GT_CPU_Error_Parity 0x0138 0178 #define GT_CPU_Error_Cause 0x0140 0179 #define GT_CPU_Error_Mask 0x0148 0180 0181 #define GT_DecodeAddr_SET(g, r, v) \ 0182 do { \ 0183 gt_read((g), GT_Internal_Decode); \ 0184 gt_write((g), (r), ((v) & 0xfff00000) >> 20); \ 0185 while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \ 0186 } while (0) 0187 0188 #define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20) 0189 #define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff) 0190 0191 #define GT_MPP_Control0 0xf000 0192 #define GT_MPP_Control1 0xf004 0193 #define GT_MPP_Control2 0xf008 0194 #define GT_MPP_Control3 0xf00c 0195 0196 #define GT_GPP_IO_Control 0xf100 0197 #define GT_GPP_Level_Control 0xf110 0198 #define GT_GPP_Value 0xf104 0199 #define GT_GPP_Interrupt_Cause 0xf108 0200 #define GT_GPP_Interrupt_Mask 0xf10c 0201 /* 0202 * Table 36: SCS[0]* Low Decode Address, Offset: 0x008 0203 * Table 38: SCS[1]* Low Decode Address, Offset: 0x208 0204 * Table 40: SCS[2]* Low Decode Address, Offset: 0x018 0205 * Table 42: SCS[3]* Low Decode Address, Offset: 0x218 0206 * Table 44: CS[0]* Low Decode Address, Offset: 0x028 0207 * Table 46: CS[1]* Low Decode Address, Offset: 0x228 0208 * Table 48: CS[2]* Low Decode Address, Offset: 0x248 0209 * Table 50: CS[3]* Low Decode Address, Offset: 0x038 0210 * Table 52: BootCS* Low Decode Address, Offset: 0x238 0211 * Table 75: CPU 0 Low Decode Address, Offset: 0x290 0212 * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0 0213 * 0214 * 11:00 LowAddr SCS[0] Base Address 0215 * 31:12 Reserved Must be 0. 0216 */ 0217 0218 /* 0219 * Table 37: SCS[0]* High Decode Address, Offset: 0x010 0220 * Table 39: SCS[1]* High Decode Address, Offset: 0x210 0221 * Table 41: SCS[2]* High Decode Address, Offset: 0x020 0222 * Table 43: SCS[3]* High Decode Address, Offset: 0x220 0223 * Table 45: CS[0]* High Decode Address, Offset: 0x030 0224 * Table 47: CS[1]* High Decode Address, Offset: 0x230 0225 * Table 49: CS[2]* High Decode Address, Offset: 0x250 0226 * Table 51: CS[3]* High Decode Address, Offset: 0x040 0227 * Table 53: BootCS* High Decode Address, Offset: 0x240 0228 * Table 76: CPU 0 High Decode Address, Offset: 0x298 0229 * Table 78: CPU 1 High Decode Address, Offset: 0x2c8 0230 * 0231 * 11:00 HighAddr SCS[0] Top Address 0232 * 31:12 Reserved 0233 */ 0234 0235 /* 0236 * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048 0237 * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058 0238 * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080 0239 * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258 0240 * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280 0241 * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090 0242 * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0 0243 * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0 0244 * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0 0245 * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0 0246 * 0247 * 11:00 LowAddr PCI IO/Memory Space Base Address 0248 * 23:12 Reserved 0249 * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap; 0250 * 1: No swapping; 2: Both byte and word swap; 0251 * 3: Word swap; 4..7: Reserved) 0252 * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when 0253 * configured to 64-bit PCI bus and not I/O) 0254 * 0: Assert s REQ64* only when transaction 0255 * is longer than 64-bits. 0256 * 1: Always assert REQ64*. 0257 * 31:28 Reserved 0258 */ 0259 #define GT_PCISwap_GET(v) GT__EXT((v), 24, 3) 0260 #define GT_PCISwap_ByteSwap 0 0261 #define GT_PCISwap_NoSwap 1 0262 #define GT_PCISwap_ByteWordSwap 2 0263 #define GT_PCISwap_WordSwap 3 0264 #define GT_PCI_LowDecode_PCIReq64 GT__BIT(27) 0265 0266 /* 0267 * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050 0268 * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060 0269 * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088 0270 * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260 0271 * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288 0272 * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098 0273 * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8 0274 * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8 0275 * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8 0276 * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8 0277 * 0278 * 11:00 HighAddr PCI_0 I/O Space Top Address 0279 * 31:12 Reserved 0280 */ 0281 0282 /* 0283 * Table 74: Internal Space Decode, Offset: 0x068 0284 * 15:00 IntDecode GT64260 Internal Space Base Address 0285 * 23:16 Reserved 0286 * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address. 0287 * NOTE: Reserved for Galileo Technology usage. 0288 * Relevant only for PCI master configuration 0289 * transactions on the PCI bus. 0290 * 31:27 Reserved 0291 */ 0292 0293 /* 0294 * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0 0295 * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8 0296 * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100 0297 * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8 0298 * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300 0299 * Table 88: PCI_1 I/O Address Remap, Offset: 0x108 0300 * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110 0301 * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118 0302 * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310 0303 * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318 0304 * 0305 * 11:00 Remap PCI IO/Memory Space Address Remap (31:20) 0306 * 31:12 Reserved 0307 */ 0308 0309 /* 0310 * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320 0311 * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328 0312 * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330 0313 * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338 0314 * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340 0315 * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348 0316 * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350 0317 * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358 0318 * 0319 * 31:00 Remap PCI Memory Address Remap (high 32 bits) 0320 */ 0321 0322 /* 0323 * Table 97: CPU Configuration, Offset: 0x000 0324 * 07:00 NoMatchCnt CPU Address Miss Counter 0325 * 08:08 NoMatchCntEn CPU Address Miss Counter Enable 0326 * NOTE: Relevant only if multi-GT is enabled. 0327 * (0: Disabled; 1: Enabled) 0328 * 09:09 NoMatchCntExt CPU address miss counter MSB 0329 * 10:10 Reserved 0330 * 11:11 AACKDelay Address Acknowledge Delay 0331 * 0: AACK* is asserted one cycle after TS*. 0332 * 1: AACK* is asserted two cycles after TS*. 0333 * 12:12 Endianess Must be 0 0334 * NOTE: The GT64260 does not support the PowerPC 0335 * Little Endian convention 0336 * 13:13 Pipeline Pipeline Enable 0337 * 0: Disabled. The GT64260 will not respond with 0338 * AACK* to a new CPU transaction, before the 0339 * previous transaction data phase completes. 0340 * 1: Enabled. 0341 * 14:14 Reserved 0342 * 15:15 TADelay Transfer Acknowledge Delay 0343 * 0: TA* is asserted one cycle after AACK* 0344 * 1: TA* is asserted two cycles after AACK* 0345 * 16:16 RdOOO Read Out of Order Completion 0346 * 0: Not Supported, Data is always returned in 0347 * order (DTI[0-2] is always driven 0348 * 1: Supported 0349 * 17:17 StopRetry Relevant only if PCI Retry is enabled 0350 * 0: Keep Retry all PCI transactions targeted 0351 * to the GT64260. 0352 * 1: Stop Retry of PCI transactions. 0353 * 18:18 MultiGTDec Multi-GT Address Decode 0354 * 0: Normal address decoding 0355 * 1: Multi-GT address decoding 0356 * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ... 0357 * 0: is not checked. (Not connected) 0358 * 1: is checked (Connected) 0359 * 21:20 Reserved 0360 * 22:22 PErrProp Parity Error Propagation 0361 * 0: GT64260 always drives good parity on 0362 * DP[0-7] during CPU reads. 0363 * 1: GT64260 drives bad parity on DP[0-7] in case 0364 * the read response from the target interface 0365 * comes with erroneous data indication 0366 * (e.g. ECC error from SDRAM interface). 0367 * 25:23 Reserved 0368 * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ... 0369 * 0: is not checked. (Not connected) 0370 * 1: is checked (Connected) 0371 * 27:27 RemapWrDis Address Remap Registers Write Control 0372 * 0: Write to Low Address decode register. 0373 * Results in writing of the corresponding 0374 * Remap register. 0375 * 1: Write to Low Address decode register. No 0376 * affect on the corresponding Remap register. 0377 * 28:28 ConfSBDis Configuration Read Sync Barrier Disable 0378 * 0: enabled; 1: disabled 0379 * 29:29 IOSBDis I/O Read Sync Barrier Disable 0380 * 0: enabled; 1: disabled 0381 * 30:30 ClkSync Clocks Synchronization 0382 * 0: The CPU interface is running with SysClk, 0383 * which is asynchronous to TClk. 0384 * 1: The CPU interface is running with TClk. 0385 * 31:31 Reserved 0386 */ 0387 #define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8) 0388 #define GT_CPUCfg_NoMatchCntEn GT__BIT( 9) 0389 #define GT_CPUCfg_NoMatchCntExt GT__BIT(10) 0390 #define GT_CPUCfg_AACKDelay GT__BIT(11) 0391 #define GT_CPUCfg_Endianess GT__BIT(12) 0392 #define GT_CPUCfg_Pipeline GT__BIT(13) 0393 #define GT_CPUCfg_TADelay GT__BIT(15) 0394 #define GT_CPUCfg_RdOOO GT__BIT(16) 0395 #define GT_CPUCfg_StopRetry GT__BIT(17) 0396 #define GT_CPUCfg_MultiGTDec GT__BIT(18) 0397 #define GT_CPUCfg_DPValid GT__BIT(19) 0398 #define GT_CPUCfg_PErrProp GT__BIT(22) 0399 #define GT_CPUCfg_APValid GT__BIT(26) 0400 #define GT_CPUCfg_RemapWrDis GT__BIT(27) 0401 #define GT_CPUCfg_ConfSBDis GT__BIT(28) 0402 #define GT_CPUCfg_IOSBDis GT__BIT(29) 0403 #define GT_CPUCfg_ClkSync GT__BIT(30) 0404 0405 /* 0406 * Table 98: CPU Mode, Offset: 0x120, Read only 0407 * 01:00 MultiGTID Multi-GT ID 0408 * Represents the ID to which the GT64260 responds 0409 * to during a multi-GT address decoding period. 0410 * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration 0411 * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions 0412 * 07:04 CPUType 0413 * 0x0-0x3: Reserved 0414 * 0x4: 64-bit PowerPC CPU, 60x bus 0415 * 0x5: 64-bit PowerPC CPU, MPX bus 0416 * 0x6-0xf: Reserved 0417 * 31:08 Reserved 0418 */ 0419 #define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2) 0420 #define GT_CPUMode_MultiGT GT__BIT(2) 0421 #define GT_CPUMode_RetryEn GT__BIT(3) 0422 #define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4) 0423 0424 /* 0425 * Table 99: CPU Master Control, Offset: 0x160 0426 * 07:00 Reserved 0427 * 08:08 IntArb CPU Bus Internal Arbiter Enable 0428 * NOTE: Only relevant to 60x bus mode. When 0429 * running MPX bus, the GT64260 internal 0430 * arbiter must be used. 0431 * 0: Disabled. External arbiter is required. 0432 * 1: Enabled. Use the GT64260 CPU bus arbiter. 0433 * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control 0434 * NOTE: This bit must be set to 1. It is reserved 0435 * for Galileo Technology usage. 0436 * 0: Enable internal bus sharing between master 0437 * and slave interfaces. 0438 * 1: Disable internal bus sharing between master 0439 * and slave interfaces. 0440 * 10:10 MWrTrig Master Write Transaction Trigger 0441 * 0: With first valid write data 0442 * 1: With last valid write data 0443 * 11:11 MRdTrig Master Read Response Trigger 0444 * 0: With first valid read data 0445 * 1: With last valid read data 0446 * 12:12 CleanBlock Clean Block Snoop Transaction Support 0447 * 0: CPU does not support clean block (603e,750) 0448 * 1: CPU supports clean block (604e,G4) 0449 * 13:13 FlushBlock Flush Block Snoop Transaction Support 0450 * 0: CPU does not support flush block (603e,750) 0451 * 1: CPU supports flush block (604e,G4) 0452 * 31:14 Reserved 0453 */ 0454 #define GT_CPUMstrCtl_IntArb GT__BIT(8) 0455 #define GT_CPUMstrCtl_IntBusCtl GT__BIT(9) 0456 #define GT_CPUMstrCtl_MWrTrig GT__BIT(10) 0457 #define GT_CPUMstrCtl_MRdTrig GT__BIT(11) 0458 #define GT_CPUMstrCtl_CleanBlock GT__BIT(12) 0459 #define GT_CPUMstrCtl_FlushBlock GT__BIT(13) 0460 0461 #define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */ 0462 #define GT_ArbSlice_DEVICE 0x1 /* Device request */ 0463 #define GT_ArbSlice_NULL 0x2 /* NULL request */ 0464 #define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */ 0465 #define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */ 0466 #define GT_ArbSlice_COMM 0x5 /* Comm unit access */ 0467 #define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */ 0468 #define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */ 0469 /* 0x8-0xf: Reserved */ 0470 0471 /* Pass in the slice number (from 0..16) as 'n' 0472 */ 0473 #define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4) 0474 0475 /* 0476 * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150 0477 * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter 0478 * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter 0479 * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter 0480 * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter 0481 * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter 0482 * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter 0483 * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter 0484 * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter 0485 */ 0486 0487 /* 0488 * Table 101: CPU Interface Crossbar Control High, Offset: 0x158 0489 * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter 0490 * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter 0491 * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter 0492 * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter 0493 * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter 0494 * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter 0495 * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter 0496 * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter 0497 */ 0498 0499 /* 0500 * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168 0501 * NOTE: Reserved for Galileo Technology usage. 0502 * 07:00 Timeout Crossbar Arbiter Timeout Preset Value 0503 * 15:08 Reserved 0504 * 16:16 TimeoutEn Crossbar Arbiter Timer Enable 0505 * (0: Enable; 1: Disable) 0506 * 31:17 Reserved 0507 */ 0508 0509 /* 0510 * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170 0511 * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter 0512 * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter 0513 * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter 0514 * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter 0515 * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter 0516 * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter 0517 * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter 0518 * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter 0519 */ 0520 /* 0521 * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178 0522 * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter 0523 * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter 0524 * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter 0525 * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter 0526 * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter 0527 * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter 0528 * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter 0529 * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter 0530 */ 0531 0532 /* 0533 * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0 0534 * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8 0535 * NOTE: The read data is random and should be ignored. 0536 * 31:00 SyncBarrier A CPU read from this register creates a 0537 * synchronization barrier cycle. 0538 */ 0539 0540 /* 0541 * Table 107: CPU Protect Address 0 Low, Offset: 0x180 0542 * Table 109: CPU Protect Address 1 Low, Offset: 0x190 0543 * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0 0544 * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0 0545 * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0 0546 * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0 0547 * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0 0548 * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0 0549 * 0550 * 11:00 LowAddr CPU Protect Region Base Address 0551 * Corresponds to address bits[31:20]. 0552 * 15:12 Reserved. Must be 0 0553 * 16:16 AccProtect CPU Access Protect 0554 * Access is (0: allowed; 1: forbidden) 0555 * 17:17 WrProtect CPU Write Protect 0556 * Writes are (0: allowed; 1: forbidden) 0557 * 18:18 CacheProtect CPU caching protect. Caching (block read) 0558 * is (0: allowed; 1: forbidden) 0559 * 31:19 Reserved 0560 */ 0561 #define GT_CPU_AccProtect GT__BIT(16) 0562 #define GT_CPU_WrProtect GT__BIT(17) 0563 #define GT_CPU_CacheProtect GT__BIT(18) 0564 0565 /* 0566 * Table 108: CPU Protect Address 0 High, Offset: 0x188 0567 * Table 110: CPU Protect Address 1 High, Offset: 0x198 0568 * Table 112: CPU Protect Address 2 High, Offset: 0x1a8 0569 * Table 114: CPU Protect Address 3 High, Offset: 0x1b8 0570 * Table 116: CPU Protect Address 4 High, Offset: 0x1c8 0571 * Table 118: CPU Protect Address 5 High, Offset: 0x1d8 0572 * Table 120: CPU Protect Address 6 High, Offset: 0x1e8 0573 * Table 122: CPU Protect Address 7 High, Offset: 0x1f8 0574 * 0575 * 11:00 HighAddr CPU Protect Region Top Address 0576 * Corresponds to address bits[31:20] 0577 * 31:12 Reserved 0578 */ 0579 0580 /* 0581 * Table 123: Snoop Base Address 0, Offset: 0x380 0582 * Table 125: Snoop Base Address 1, Offset: 0x390 0583 * Table 127: Snoop Base Address 2, Offset: 0x3a0 0584 * Table 129: Snoop Base Address 3, Offset: 0x3b0 0585 * 0586 * 11:00 LowAddr Snoop Region Base Address [31:20] 0587 * 15:12 Reserved Must be 0. 0588 * 17:16 Snoop Snoop Type 0589 * 0x0: No Snoop 0590 * 0x1: Snoop to WT region 0591 * 0x2: Snoop to WB region 0592 * 0x3: Reserved 0593 * 31:18 Reserved 0594 */ 0595 #define GT_Snoop_GET(v) GT__EXT((v), 16, 2) 0596 #define GT_Snoop_INS(v) GT__INS((v), 16) 0597 #define GT_Snoop_None 0 0598 #define GT_Snoop_WT 1 0599 #define GT_Snoop_WB 2 0600 0601 0602 /* 0603 * Table 124: Snoop Top Address 0, Offset: 0x388 0604 * Table 126: Snoop Top Address 1, Offset: 0x398 0605 * Table 128: Snoop Top Address 2, Offset: 0x3a8 0606 * Table 130: Snoop Top Address 3, Offset: 0x3b8 0607 * 11:00 HighAddr Snoop Region Top Address [31:20] 0608 * 31:12 Reserved 0609 */ 0610 0611 0612 /* 0613 * Table 131: CPU Error Address Low, Offset: 0x070, Read Only. 0614 * In case of multiple errors, only the first one is latched. New error 0615 * report latching is enabled only after the CPU Error Address Low register 0616 * is being read. 0617 * 31:00 ErrAddr Latched address bits [31:0] of a CPU 0618 * transaction in case of: 0619 * o illegal address (failed address decoding) 0620 * o access protection violation 0621 * o bad data parity 0622 * o bad address parity 0623 * Upon address latch, no new address are 0624 * registered (due to additional error condition), 0625 * until the register is being read. 0626 */ 0627 0628 /* 0629 * Table 132: CPU Error Address High, Offset: 0x078, Read Only. 0630 * Once data is latched, no new data can be registered (due to additional 0631 * error condition), until CPU Error Low Address is being read (which 0632 * implies, it should be the last being read by the interrupt handler). 0633 * 03:00 Reserved 0634 * 07:04 ErrPar Latched address parity bits in case 0635 * of bad CPU address parity detection. 0636 * 31:08 Reserved 0637 */ 0638 #define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4) 0639 0640 /* 0641 * Table 133: CPU Error Data Low, Offset: 0x128, Read only. 0642 * 31:00 PErrData Latched data bits [31:0] in case of bad data 0643 * parity sampled on write transactions or on 0644 * master read transactions. 0645 */ 0646 0647 /* 0648 * Table 134: CPU Error Data High, Offset: 0x130, Read only. 0649 * 31:00 PErrData Latched data bits [63:32] in case of bad data 0650 * parity sampled on write transactions or on 0651 * master read transactions. 0652 */ 0653 0654 /* 0655 * Table 135: CPU Error Parity, Offset: 0x138, Read only. 0656 * 07:00 PErrPar Latched data parity bus in case of bad data 0657 * parity sampled on write transactions or on 0658 * master read transactions. 0659 * 31:10 Reserved 0660 */ 0661 #define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8) 0662 0663 /* 0664 * Table 136: CPU Error Cause, Offset: 0x140 0665 * Bits[7:0] are clear only. A cause bit is set upon an error condition 0666 * occurrence. Write a 0 value to clear the bit. Writing a 1 value has 0667 * no affect. 0668 * 00:00 AddrOut CPU Address Out of Range 0669 * 01:01 AddrPErr Bad Address Parity Detected 0670 * 02:02 TTErr Transfer Type Violation. 0671 * The CPU attempts to burst (read or write) to an 0672 * internal register. 0673 * 03:03 AccErr Access to a Protected Region 0674 * 04:04 WrErr Write to a Write Protected Region 0675 * 05:05 CacheErr Read from a Caching protected region 0676 * 06:06 WrDataPErr Bad Write Data Parity Detected 0677 * 07:07 RdDataPErr Bad Read Data Parity Detected 0678 * 26:08 Reserved 0679 * 31:27 Sel Specifies the error event currently being 0680 * reported in Error Address, Error Data, and 0681 * Error Parity registers. 0682 * 0x0: AddrOut 0683 * 0x1: AddrPErr 0684 * 0x2: TTErr 0685 * 0x3: AccErr 0686 * 0x4: WrErr 0687 * 0x5: CacheErr 0688 * 0x6: WrDataPErr 0689 * 0x7: RdDataPErr 0690 * 0x8-0x1f: Reserved 0691 */ 0692 #define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut) 0693 #define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr) 0694 #define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr) 0695 #define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr) 0696 #define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr) 0697 #define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr) 0698 #define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr) 0699 #define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr) 0700 0701 #define GT_CPUError_Sel_AddrOut 0 0702 #define GT_CPUError_Sel_AddrPErr 1 0703 #define GT_CPUError_Sel_TTErr 2 0704 #define GT_CPUError_Sel_AccErr 3 0705 #define GT_CPUError_Sel_WrErr 4 0706 #define GT_CPUError_Sel_CacheErr 5 0707 #define GT_CPUError_Sel_WrDataPErr 6 0708 #define GT_CPUError_Sel_RdDataPErr 7 0709 0710 #define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5) 0711 0712 /* 0713 * Table 137: CPU Error Mask, Offset: 0x148 0714 * 00:00 AddrOut If set to 1, enables AddrOut interrupt. 0715 * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt. 0716 * 02:02 TTErr If set to 1, enables TTErr interrupt. 0717 * 03:03 AccErr If set to 1, enables AccErr interrupt. 0718 * 04:04 WrErr If set to 1, enables WrErr interrupt. 0719 * 05:05 CacheErr If set to 1, enables CacheErr interrupt. 0720 * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt. 0721 * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt. 0722 * 31:08 Reserved 0723 */ 0724 0725 /* 0726 * Comm Unit Interrupt registers 0727 */ 0728 0729 /* Comm Unit Arbiter Control */ 0730 #define GT_CommUnitArb_Ctrl 0xf300 0731 /* GPP IRQs level vs. edge sensitivity */ 0732 #define GT_CommUnitArb_Ctrl_GPP_Ints_Level_Sensitive (1<<10) 0733 0734 #define GT_CommUnitIntr_Cause 0xf310 0735 #define GT_CommUnitIntr_Mask 0xf314 0736 #define GT_CommUnitIntr_ErrAddr 0xf318 0737 0738 #define GT_CommUnitIntr_E0 0x00000007 0739 #define GT_CommUnitIntr_E1 0x00000070 0740 #define GT_CommUnitIntr_E2 0x00000700 0741 #define GT_CommUnitIntr_S0 0x00070000 0742 #define GT_CommUnitIntr_S1 0x00700000 0743 #define GT_CommUnitIntr_Sel 0x70000000 0744 0745 /* 0746 * SDRAM Error Report (ECC) Registers 0747 */ 0748 #define GT_260_ECC_Data_Lo 0x484 /* latched Error Data (low) */ 0749 #define GT_260_ECC_Data_Hi 0x480 /* latched Error Data (high) */ 0750 #define GT_260_ECC_Addr 0x490 /* latched Error Address */ 0751 #define GT_260_ECC_Rec 0x488 /* latched ECC code from SDRAM */ 0752 #define GT_260_ECC_Calc 0x48c /* latched ECC code from SDRAM */ 0753 #define GT_260_ECC_Ctl 0x494 /* ECC Control */ 0754 #define GT_260_ECC_Count 0x498 /* ECC 1-bit error count */ 0755 0756 /* Timer/Counter Registers (t. straumann) 0757 */ 0758 #define GT_TIMER_0 0x0850 /* preset / running value */ 0759 #define GT_TIMER_1 0x0854 0760 #define GT_TIMER_2 0x0858 0761 #define GT_TIMER_3 0x085c 0762 0763 #define GT_TIMER_0_3_Ctl 0x0864 0764 0765 #define GT_TIMER_0_Ctl_Enb 0x00000001 /* enable timer */ 0766 #define GT_TIMER_0_Ctl_Rld 0x00000002 /* reload after expiration */ 0767 #define GT_TIMER_1_Ctl_Enb 0x00000100 /* enable timer */ 0768 #define GT_TIMER_1_Ctl_Rld 0x00000200 /* reload after expiration */ 0769 #define GT_TIMER_2_Ctl_Enb 0x00010000 /* enable timer */ 0770 #define GT_TIMER_2_Ctl_Rld 0x00020000 /* reload after expiration */ 0771 #define GT_TIMER_3_Ctl_Enb 0x01000000 /* enable timer */ 0772 #define GT_TIMER_3_Ctl_Rld 0x02000000 /* reload after expiration */ 0773 0774 #define GT_TIMER_0_3_Intr_Cse 0x0868 0775 #define GT_TIMER_0_Intr 0x00000001 0776 #define GT_TIMER_1_Intr 0x00000002 0777 #define GT_TIMER_2_Intr 0x00000004 0778 #define GT_TIMER_3_Intr 0x00000008 0779 #define GT_TIMER_Intr_Smry 0x80000000 /* Interrupt Summary */ 0780 0781 #define GT_TIMER_0_3_Intr_Msk 0x086c 0782 0783 /* 0784 * Watchdog Registers 0785 */ 0786 #define GT_WDOG_Config 0xb410 0787 #define GT_WDOG_Value 0xb414 0788 #define GT_WDOG_Value_NMI GT__MASK(24) 0789 #define GT_WDOG_Config_Preset GT__MASK(24) 0790 #define GT_WDOG_Config_Ctl1a GT__BIT(24) 0791 #define GT_WDOG_Config_Ctl1b GT__BIT(25) 0792 #define GT_WDOG_Config_Ctl2a GT__BIT(26) 0793 #define GT_WDOG_Config_Ctl2b GT__BIT(27) 0794 #define GT_WDOG_Config_Enb GT__BIT(31) 0795 0796 #define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI) 0797 #define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset) 0798 0799 /* 0800 * Device Bus Interrupts 0801 */ 0802 #define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */ 0803 #define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */ 0804 #define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */ 0805 0806 /* 0807 * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK 0808 */ 0809 #define GT_DEVBUS_DBurstErr GT__BIT(0) 0810 #define GT_DEVBUS_DRdyErr GT__BIT(1) 0811 #define GT_DEVBUS_Sel GT__BIT(27) 0812 #define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel) 0813 0814 /* MV64360 */ 0815 /* Enable individual CPU windows by *clearing* respective bits 0816 * in MV_64360_BASE_ADDR_DISBL 0817 * 0818 * Bit ordering is: 0819 * 0820 * SDRAM_CS_0..3 (1<<0..3) 0821 * DEV_CS_0..3 (1<<4..7) 0822 * BOOT_CS_0..3 (1<<8) 0823 * PCI_0_IO (1<<9) 0824 * PCI_0_MEM_0..3 (1<<10..13) 0825 * PCI_1_IO (1<<14) 0826 * PCI_1_MEM_0..3 (1<<15..18) 0827 * INTERNAL_SRAM (1<<19) 0828 * MV64x60_REGS (1<<20) 0829 */ 0830 #define MV_64360_BASE_ADDR_DISBL (0x278) 0831 0832 /* Internal SRAM */ 0833 #define MV_64360_SRAM_BASE (0x268) 0834 #define MV_64360_SRAM_CTRL (0x380) 0835 /* Control register bits */ 0836 #define MV_64360_SRAM_CacheWb GT__BIT(1) 0837 /* default setup used by linux, motload (uses 90 instead of b0), ... 0838 * Comments say: 0839 * - parity enabled, 0840 * - parity error propagation 0841 * - arbitration not parked for CPU only 0842 * - other bits are reserved 0843 */ 0844 #define MV_64360_SRAM_Ctl_Setup (0x001600b0) 0845 0846 #define MV_64360_SRAM_TEST_MODE (0x3f4) 0847 #define MV_64340_SRAM_ERR_CAUSE (0x388) 0848 #define MV_64340_SRAM_ERR_ADDR (0x390) 0849 #define MV_64340_SRAM_ERR_ADDR_HI (0X3f8) 0850 #define MV_64340_SRAM_ERR_DATA_LO (0x398) 0851 #define MV_64340_SRAM_ERR_DATA_HI (0x3a0) 0852 #define MV_64340_SRAM_ERR_DATA_PARITY (0x3a8) 0853 0854 #endif /* !_DISCOVERY_DEV_GTREG_H */
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