include/bsp/gtpcireg.h

0001 /*  $NetBSD: gtpcireg.h,v 1.4 2005/12/11 12:22:16 christos Exp $    */
0002
0003 /*
0004  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions and the following disclaimer.
0012  * 2. Redistributions in binary form must reproduce the above copyright
0013  *    notice, this list of conditions and the following disclaimer in the
0014  *    documentation and/or other materials provided with the distribution.
0015  * 3. All advertising materials mentioning features or use of this software
0016  *    must display the following acknowledgement:
0017  *      This product includes software developed for the NetBSD Project by
0018  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
0019  * 4. The name of Allegro Networks, Inc. may not be used to endorse
0020  *    or promote products derived from this software without specific prior
0021  *    written permission.
0022  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
0023  *    or promote products derived from this software without specific prior
0024  *    written permission.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
0027  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
0028  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
0029  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
0030  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
0031  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0032  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0033  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0036  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGE.
0038  */
0039
0040 #ifndef _DEV_GTPCIREG_H
0041 #define _DEV_GTPCIREG_H
0042
0043 #define PCI__BIT(bit)           (1U << (bit))
0044 #define PCI__MASK(bit)          (PCI__BIT(bit) - 1)
0045 #define PCI__GEN(bus, off, num)     (((off)^((bus) << 7))+((num) << 4))
0046 #define PCI__EXT(data, bit, len)    (((data) >> (bit)) & PCI__MASK(len))
0047 #define PCI__CLR(data, bit, len)    ((data) &= ~(PCI__MASK(len) << (bit)))
0048 #define PCI__INS(bit, new)      ((new) << (bit))
0049
0050 #define PCI_SYNC_REG(bus)       (0xc0 | ((bus) << 3))
0051
0052 /*
0053  * Table 185: PCI Slave ADDRess Decoding Register Map
0054  */
0055 #define PCI_SCS0_BAR_SIZE(bus)              PCI__GEN(bus, 0x0c08, 0)
0056 #define PCI_SCS2_BAR_SIZE(bus)              PCI__GEN(bus, 0x0c0c, 0)
0057 #define PCI_CS0_BAR_SIZE(bus)               PCI__GEN(bus, 0x0c10, 0)
0058 #define PCI_CS3_BAR_SIZE(bus)               PCI__GEN(bus, 0x0c14, 0)
0059 #define PCI_SCS1_BAR_SIZE(bus)              PCI__GEN(bus, 0x0d08, 0)
0060 #define PCI_SCS3_BAR_SIZE(bus)              PCI__GEN(bus, 0x0d0c, 0)
0061 #define PCI_CS1_BAR_SIZE(bus)               PCI__GEN(bus, 0x0d10, 0)
0062 #define PCI_BOOTCS_BAR_SIZE(bus)            PCI__GEN(bus, 0x0d14, 0)
0063 #define PCI_CS2_BAR_SIZE(bus)               PCI__GEN(bus, 0x0d18, 0)
0064 #define PCI_P2P_MEM0_BAR_SIZE(bus)          PCI__GEN(bus, 0x0d1c, 0)
0065 #define PCI_P2P_MEM1_BAR_SIZE(bus)          PCI__GEN(bus, 0x0d20, 0)
0066 #define PCI_P2P_IO_BAR_SIZE(bus)            PCI__GEN(bus, 0x0d24, 0)
0067 #define PCI_CPU_BAR_SIZE(bus)               PCI__GEN(bus, 0x0d28, 0)
0068 #define PCI_EXPANSION_ROM_BAR_SIZE(bus)         PCI__GEN(bus, 0x0d2c, 0)
0069 #define PCI_DAC_SCS0_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e00, 0)
0070 #define PCI_DAC_SCS1_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e04, 0)
0071 #define PCI_DAC_SCS2_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e08, 0)
0072 #define PCI_DAC_SCS3_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e0c, 0)
0073 #define PCI_DAC_CS0_BAR_SIZE(bus)           PCI__GEN(bus, 0x0e10, 0)
0074 #define PCI_DAC_CS1_BAR_SIZE(bus)           PCI__GEN(bus, 0x0e14, 0)
0075 #define PCI_DAC_CS2_BAR_SIZE(bus)           PCI__GEN(bus, 0x0e18, 0)
0076 #define PCI_DAC_CS3_BAR_SIZE(bus)           PCI__GEN(bus, 0x0e1c, 0)
0077 #define PCI_DAC_BOOTCS_BAR_SIZE(bus)            PCI__GEN(bus, 0x0e20, 0)
0078 #define PCI_DAC_P2P_MEM0_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e24, 0)
0079 #define PCI_DAC_P2P_MEM1_BAR_SIZE(bus)          PCI__GEN(bus, 0x0e28, 0)
0080 #define PCI_DAC_CPU_BAR_SIZE(bus)           PCI__GEN(bus, 0x0e2c, 0)
0081 #define PCI_BASE_ADDR_REGISTERS_ENABLE(bus)     PCI__GEN(bus, 0x0c3c, 0)
0082 #define PCI_SCS0_BASE_ADDR_REMAP(bus)           PCI__GEN(bus, 0x0c48, 0)
0083 #define PCI_SCS1_BASE_ADDR_REMAP(bus)           PCI__GEN(bus, 0x0d48, 0)
0084 #define PCI_SCS2_BASE_ADDR_REMAP(bus)           PCI__GEN(bus, 0x0c4c, 0)
0085 #define PCI_SCS3_BASE_ADDR_REMAP(bus)           PCI__GEN(bus, 0x0d4c, 0)
0086 #define PCI_CS0_BASE_ADDR_REMAP(bus)            PCI__GEN(bus, 0x0c50, 0)
0087 #define PCI_CS1_BASE_ADDR_REMAP(bus)            PCI__GEN(bus, 0x0d50, 0)
0088 #define PCI_CS2_BASE_ADDR_REMAP(bus)            PCI__GEN(bus, 0x0d58, 0)
0089 #define PCI_CS3_BASE_ADDR_REMAP(bus)            PCI__GEN(bus, 0x0c54, 0)
0090 #define PCI_ADDR_DECODE_CONTROL(bus)            PCI__GEN(bus, 0x0d3c, 0)
0091 #define PCI_BOOTCS_ADDR_REMAP(bus)          PCI__GEN(bus, 0x0d54, 0)
0092 #define PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)       PCI__GEN(bus, 0x0d5c, 0)
0093 #define PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)      PCI__GEN(bus, 0x0d60, 0)
0094 #define PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)       PCI__GEN(bus, 0x0d64, 0)
0095 #define PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)      PCI__GEN(bus, 0x0d68, 0)
0096 #define PCI_P2P_IO_BASE_ADDR_REMAP(bus)         PCI__GEN(bus, 0x0d6c, 0)
0097 #define PCI_CPU_BASE_ADDR_REMAP(bus)            PCI__GEN(bus, 0x0d70, 0)
0098 #define PCI_DAC_SCS0_BASE_ADDR_REMAP(bus)       PCI__GEN(bus, 0x0f00, 0)
0099 #define PCI_DAC_SCS1_BASE_ADDR_REMAP(bus)       PCI__GEN(bus, 0x0f04, 0)
0100 #define PCI_DAC_SCS2_BASE_ADDR_REMAP(bus)       PCI__GEN(bus, 0x0f08, 0)
0101 #define PCI_DAC_SCS3_BASE_ADDR_REMAP(bus)       PCI__GEN(bus, 0x0f0c, 0)
0102 #define PCI_DAC_CS0_BASE_ADDR_REMAP(bus)        PCI__GEN(bus, 0x0f10, 0)
0103 #define PCI_DAC_CS1_BASE_ADDR_REMAP(bus)        PCI__GEN(bus, 0x0f14, 0)
0104 #define PCI_DAC_CS2_BASE_ADDR_REMAP(bus)        PCI__GEN(bus, 0x0f18, 0)
0105 #define PCI_DAC_CS3_BASE_ADDR_REMAP(bus)        PCI__GEN(bus, 0x0f1c, 0)
0106 #define PCI_DAC_BOOTCS_BASE_ADDR_REMAP(bus)     PCI__GEN(bus, 0x0f20, 0)
0107 #define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_LOW(bus)   PCI__GEN(bus, 0x0f24, 0)
0108 #define PCI_DAC_P2P_MEM0_BASE_ADDR_REMAP_HIGH(bus)  PCI__GEN(bus, 0x0f28, 0)
0109 #define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_LOW(bus)   PCI__GEN(bus, 0x0f2c, 0)
0110 #define PCI_DAC_P2P_MEM1_BASE_ADDR_REMAP_HIGH(bus)  PCI__GEN(bus, 0x0f30, 0)
0111 #define PCI_DAC_CPU_BASE_ADDR_REMAP(bus)        PCI__GEN(bus, 0x0f34, 0)
0112 #define PCI_EXPANSION_ROM_BASE_ADDR_REMAP(bus)      PCI__GEN(bus, 0x0f38, 0)
0113
0114 /*
0115  * Table 186: PCI Control Register Map
0116  */
0117 #define PCI_COMMAND(bus)                PCI__GEN(bus, 0x0c00, 0)
0118 #define PCI_MODE(bus)                   PCI__GEN(bus, 0x0d00, 0)
0119 #define PCI_TIMEOUT_RETRY(bus)              PCI__GEN(bus, 0x0c04, 0)
0120 #define PCI_READ_BUFFER_DISCARD_TIMER(bus)      PCI__GEN(bus, 0x0d04, 0)
0121 #define PCI_MSI_TRIGGER_TIMER(bus)          PCI__GEN(bus, 0x0c38, 0)
0122 #define PCI_ARBITER_CONTROL(bus)            PCI__GEN(bus, 0x1d00, 0)
0123 #define PCI_INTERFACE_XBAR_CONTROL_LOW(bus)     PCI__GEN(bus, 0x1d08, 0)
0124 #define PCI_INTERFACE_XBAR_CONTROL_HIGH(bus)        PCI__GEN(bus, 0x1d0c, 0)
0125 #define PCI_INTERFACE_XBAR_TIMEOUT(bus)         PCI__GEN(bus, 0x1d04, 0)
0126 #define PCI_READ_RESPONSE_XBAR_CONTROL_LOW(bus)     PCI__GEN(bus, 0x1d18, 0)
0127 #define PCI_READ_RESPONSE_XBAR_CONTROL_HIGH(bus)    PCI__GEN(bus, 0x1d1c, 0)
0128 #define PCI_SYNC_BARRIER(bus)               PCI__GEN(bus, 0x1d10, 0)
0129 #define PCI_P2P_CONFIGURATION(bus)          PCI__GEN(bus, 0x1d14, 0)
0130 #define PCI_P2P_SWAP_CONTROL(bus)           PCI__GEN(bus, 0x1d54, 0)
0131 #define PCI_ACCESS_CONTROL_BASE_LOW(bus, n)     PCI__GEN(bus, 0x1e00, n)
0132 #define PCI_ACCESS_CONTROL_BASE_HIGH(bus, n)        PCI__GEN(bus, 0x1e04, n)
0133 #define PCI_ACCESS_CONTROL_TOP(bus, n)          PCI__GEN(bus, 0x1e08, n)
0134
0135
0136 /*
0137  * Table 187: PCI Snoop Control Register Map
0138  */
0139 #define PCI_SNOOP_CONTROL_BASE_LOW(bus, n)      PCI__GEN(bus, 0x1f00, n)
0140 #define PCI_SNOOP_CONTROL_BASE_HIGH(bus, n)     PCI__GEN(bus, 0x1f04, n)
0141 #define PCI_SNOOP_CONTROL_TOP(bus, n)           PCI__GEN(bus, 0x1f08, n)
0142
0143 /*
0144  * Table 188: PCI Configuration ACCESS_Register Map
0145  */
0146 #define PCI_CONFIG_ADDR(bus)                PCI__GEN(bus, 0x0cf8, 0)
0147 #define PCI_CONFIG_DATA(bus)                PCI__GEN(bus, 0x0cfc, 0)
0148 #define PCI_INTR_ACK(bus)               PCI__GEN(bus, 0x0c34, 0)
0149
0150 /*
0151  * Table 189: PCI ERROR Report Register Map
0152  */
0153 #define PCI_SERR_MASK(bus)              PCI__GEN(bus, 0x0c28, 0)
0154 #define PCI_ERROR_ADDRESS_LOW(bus)          PCI__GEN(bus, 0x1d40, 0)
0155 #define PCI_ERROR_ADDRESS_HIGH(bus)         PCI__GEN(bus, 0x1d44, 0)
0156 #define PCI_ERROR_DATA_LOW(bus)             PCI__GEN(bus, 0x1d48, 0)
0157 #define PCI_ERROR_DATA_HIGH(bus)            PCI__GEN(bus, 0x1d4c, 0)
0158 #define PCI_ERROR_COMMAND(bus)              PCI__GEN(bus, 0x1d50, 0)
0159 #define PCI_ERROR_CAUSE(bus)                PCI__GEN(bus, 0x1d58, 0)
0160 #define PCI_ERROR_MASK(bus)             PCI__GEN(bus, 0x1d5c, 0)
0161
0162
0163
0164 /*
0165  * Table 223: PCI Base Address Registers Enable
0166  * If a bit is clear, the BAR is enabled.  If set, disabled.  The GT64260]
0167  * prevents disabling both memory mapped and I/O mapped BARs (bits 9 and 10
0168  * cannot simultaneously be set to 1).
0169  */
0170 #define PCI_BARE_SCS0En     PCI__BIT(0) /* SCS[0]* BAR Enable */
0171 #define PCI_BARE_SCS1En     PCI__BIT(1) /* SCS[1]* BAR Enable */
0172 #define PCI_BARE_SCS2En     PCI__BIT(2) /* SCS[2]* BAR Enable */
0173 #define PCI_BARE_SCS3En     PCI__BIT(3) /* SCS[3]* BAR Enable */
0174 #define PCI_BARE_CS0En      PCI__BIT(4) /* CS[0]* BAR Enable */
0175 #define PCI_BARE_CS1En      PCI__BIT(5) /* CS[1]* BAR Enable */
0176 #define PCI_BARE_CS2En      PCI__BIT(6) /* CS[2]* BAR Enable */
0177 #define PCI_BARE_CS3En      PCI__BIT(7) /* CS[3]* BAR Enable */
0178 #define PCI_BARE_BootCSEn   PCI__BIT(8) /* BootCS* BAR Enable */
0179 #define PCI_BARE_IntMemEn   PCI__BIT(9) /* Memory Mapped Internal
0180                          * Registers BAR Enable */
0181 #define PCI_BARE_IntIOEn    PCI__BIT(10)    /* I/O Mapped Internal
0182                          * Registers BAR Enable */
0183 #define PCI_BARE_P2PMem0En  PCI__BIT(11)    /* P2P Mem0 BAR Enable */
0184 #define PCI_BARE_P2PMem1En  PCI__BIT(12)    /* P2P Mem1 BAR Enable */
0185 #define PCI_BARE_P2PIOEn    PCI__BIT(13)    /* P2P IO BAR Enable */
0186 #define PCI_BARE_CPUEn      PCI__BIT(14)    /* CPU BAR Enable */
0187 #define PCI_BARE_DSCS0En    PCI__BIT(15)    /* DAC SCS[0]* BAR Enable */
0188 #define PCI_BARE_DSCS1En    PCI__BIT(16)    /* DAC SCS[1]* BAR Enable */
0189 #define PCI_BARE_DSCS2En    PCI__BIT(17)    /* DAC SCS[2]* BAR Enable */
0190 #define PCI_BARE_DSCS3En    PCI__BIT(18)    /* DAC SCS[3]* BAR Enable */
0191 #define PCI_BARE_DCS0En     PCI__BIT(19)    /* DAC CS[0]* BAR Enable */
0192 #define PCI_BARE_DCS1En     PCI__BIT(20)    /* DAC CS[1]* BAR Enable */
0193 #define PCI_BARE_DCS2En     PCI__BIT(21)    /* DAC CS[2]* BAR Enable */
0194 #define PCI_BARE_DCS3En     PCI__BIT(22)    /* DAC CS[3]* BAR Enable */
0195 #define PCI_BARE_DBootCSEn  PCI__BIT(23)    /* DAC BootCS* BAR Enable */
0196 #define PCI_BARE_DP2PMem0En PCI__BIT(24)    /* DAC P2P Mem0 BAR Enable */
0197 #define PCI_BARE_DP2PMem1En PCI__BIT(25)    /* DAC P2P Mem1 BAR Enable */
0198 #define PCI_BARE_DCPUEn     PCI__BIT(26)    /* DAC CPU BAR Enable */
0199
0200 /*
0201  * Table 254: PCI Address Decode Control
0202  * Bits 7:4 and 31:25 are reserved
0203  * 00:00 RemapWrDis     Address Remap Registers Write Disable
0204  *              0: Writes to a BAR result in updating the
0205  *                 corresponding remap register with the BAR's
0206  *                 new value.
0207  *              1: Writes to a BAR have no affect on the
0208  *                 corresponding Remap register value.
0209  * 01:01 ExpRomDev      Expansion ROM Device (0: CS[3]; 1: BootCS)
0210  * 02:02 VPDDev         VPD Device (0: CS[3]; 1: BootCS)
0211  * 03:03 MsgAcc         Messaging registers access
0212  *              0: Messaging unit registers are accessible on
0213  *                 lowest 4Kbyte of SCS[0] BAR space.
0214  *              1: Messaging unit registers are only accessible
0215  *                 as part of the GT64260 internal space.
0216  * 07:04 Reserved
0217  * 24:08 VPDHighAddr        VPD High Address bits
0218  *              [31:15] of VPD the address.
0219  * 31:25 Reserved
0220  */
0221 #define PCI_ADC_RemapWrDis      PCI__BIT(0)
0222 #define PCI_ADC_ExpRomDev       PCI__BIT(1)
0223 #define PCI_ADC_VPDDev          PCI__BIT(2)
0224 #define PCI_ADC_MsgAcc          PCI__BIT(3)
0225 #define PCI_ADC_VPDHighAddr_GET(v)  PCI__EXT(v, 8, 16)
0226
0227
0228 /*
0229  * Table 255: PCI Command
0230  * 00:00 MByteSwap  PCI Master Byte Swap
0231  *              NOTE: GT-64120 and GT-64130 compatible.
0232  *          When set to 0, the GTO64260 PCI master swaps the bytes
0233  *          of the incoming and outgoing PCI data (swap the 8 bytes
0234  *          of a longword).
0235  * 01:01 Reserved
0236  * 02:02 Reserved   Must be 0.
0237  * 03:03 Reserved
0238  * 04:04 MWrCom     PCI Master Write Combine Enable
0239  *          When set to 1, write combining is enabled.
0240  * 05:05 MRdCom     PCI Master Read Combine Enable
0241  *          When set to 1, read combining is enabled.
0242  * 06:06 MWrTrig    PCI Master Write Trigger
0243  *          0: Accesses the PCI bus only when the whole burst is
0244  *             written into the master write buffer.
0245  *          1: Accesses the PCI bus when the first data is written
0246  *             into the master write buffer.
0247  * 07:07 MRdTrig    PCI Master Read Trigger
0248  *          0: Returns read data to the initiating unit only when
0249  *             the whole burst is written into master read buffer.
0250  *          1: Returns read data to the initiating unit when the
0251  *             first read data is written into master read buffer.
0252  * 08:08 MRdLine    PCI Master Memory Read Line Enable
0253  *          (0: Disable; 1: Enable)
0254  * 09:09 MRdMul     PCI Master Memory Read Multiple Enable
0255  *          (0: Disable; 1: Enable)
0256  * 10:10 MWordSwap  PCI Master Word Swap
0257  *              NOTE: GT-64120 and GT-64130 compatible.
0258  *          When set to 1, the GT64260 PCI master swaps the 32-bit
0259  *          words of the incoming and outgoing PCI data.
0260  * 11:11 SWordSwap  PCI Slave Word Swap
0261  *              NOTE: GT-64120 and GT-64130 compatible.
0262  *          When set to 1, the GT64260 PCI slave swaps the 32-bit
0263  *          words of the incoming and outgoing PCI data.
0264  * 12:12 IntBusCtl  PCI Interface Unit Internal Bus Control
0265  *              NOTE: Reserved for Galileo Technology usage
0266  *          0: Enable internal bus sharing between master and
0267  *             slave interfaces.
0268  *          1: Disable internal bus sharing between master and
0269  *             slave interfaces.
0270  * 13:13 SBDis      PCI Slave Sync Barrier Disable
0271  *          When set to 1, the PCI configuration read transaction
0272  *          will stop act as sync barrier transaction.
0273  * 14:14 Reserved   Must be 0
0274  * 15:15 MReq64     PCI Master REQ64* Enable (0: Disable; 1: Enable)
0275  * 16:16 SByteSwap  PCI Slave Byte Swap
0276  *              NOTE: GT-64120 and GT-64130 compatible.
0277  *          When set to 0, the GT64260 PCI slave swaps the bytes of
0278  *          the incoming and outgoing PCI data (swap the 8 bytes of
0279  *          a long-word).
0280  * 17:17 MDACEn     PCI Master DAC Enable
0281  *          0: Disable (The PCI master never drives the DAC cycle)
0282  *          1: Enable (In case the upper 32-bit address is not 0,
0283  *             the PCI master drives the DAC cycle)
0284  * 18:18 M64Allign  PCI Master REQ64* assertion on non-aligned
0285  *          0: Disable (The master asserts REQ64* only if
0286  *             the address is 64-bit aligned)
0287  *          1: Enable (The master asserts REQ64* even if
0288  *             the address is not 64-bit aligned)
0289  * 19:19 PErrProp   Parity/ECC Errors Propagation Enable
0290  *          0: Disable (The PCI interface always drives
0291  *             correct parity on the PAR signal)
0292  *          1: Enable (In case of slave read bad ECC from
0293  *             SDRAM, or master write with bad parity/ECC
0294  *             indication from the initiator, the PCI interface
0295  *             drives bad parity on the PAR signal)
0296  * 20:20 SSwapEn    PCI Slave Swap Enable
0297  *              NOTE: Even if the SSwapEn bit is set to 1 and
0298  *              the PCI address does not match any of the
0299  *              Access Control registers, slave data swapping
0300  *              works according to SByteSwap and SWordSwap bits.
0301  *          0: PCI slave data swapping is determined via
0302  *             SByteSwap and SWordSwap bits (bits 16 and 11),
0303  *             as in the GT-64120/130.
0304  *          1: PCI slave data swapping is determined via PCISwap
0305  *             bits [25:24] in the PCI Access Control registers.
0306  * 21:21 MSwapEn    PCI Master Swap Enable
0307  *          0: PCI master data swapping is determined via
0308  *             MByteSwap and MWordSwap bits (bits 0 and 10),
0309  *             as in the GT-64120/130.
0310  *          1: PCI master data swapping is determined via
0311  *             PCISwap bits in CPU to PCI Address Decoding
0312  *             registers.
0313  * 22:22 MIntSwapEn PCI Master Configuration Transactions Data Swap Enable
0314  *              NOTE: Reserved for Galileo Technology usage.
0315  *          0: Disable (The PCI master configuration transaction
0316  *             to the PCI bus is always in Little Endian convention)
0317  *          1: Enable (The PCI master configuration transaction to
0318  *             the PCI bus is determined according to the setting
0319  *             of MSwapEn bit)
0320  * 23:23 LBEn       PCI Loop Back Enable
0321  *              NOTE: Reserved for Galileo Technology usage.
0322  *          0: Disable (The PCI slave does not respond to
0323  *             transactions initiated by the PCI master)
0324  *          1: Enable (The PCI slave does respond to
0325  *             transactions initiated by the PCI master,
0326  *             if targeted to the slave (address match)
0327  * 26:24 SIntSwap   PCI Slave data swap control on PCI accesses to the
0328  *          GT64260 internal and configuration registers.
0329  *          Bits encoding are the same as bits[26:24] in PCI Access
0330  *          Control registers.
0331  * 27:27 Reserved   Must be 0.
0332  * 31:28 Reserved   Read only.
0333  */
0334 #define PCI_CMD_MByteSwap   PCI__BIT(0)
0335 #define PCI_CMD_MBZ0_2      PCI__BIT(2)
0336 #define PCI_CMD_MWrCom      PCI__BIT(4)
0337 #define PCI_CMD_MRdCom      PCI__BIT(5)
0338 #define PCI_CMD_MWrTrig     PCI__BIT(6)
0339 #define PCI_CMD_MRdTrig     PCI__BIT(7)
0340 #define PCI_CMD_MRdLine     PCI__BIT(8)
0341 #define PCI_CMD_MRdMul      PCI__BIT(9)
0342 #define PCI_CMD_MWordSwap   PCI__BIT(10)
0343 #define PCI_CMD_SWordSwap   PCI__BIT(11)
0344 #define PCI_CMD_IntBusCtl   PCI__BIT(12)
0345 #define PCI_CMD_SBDis       PCI__BIT(13)
0346 #define PCI_CMD_MBZ0_14     PCI__BIT(14)
0347 #define PCI_CMD_MReq64      PCI__BIT(15)
0348 #define PCI_CMD_SByteSwap   PCI__BIT(16)
0349 #define PCI_CMD_MDCAEn      PCI__BIT(17)
0350 #define PCI_CMD_M64Allign   PCI__BIT(18)
0351 #define PCI_CMD_PErrProp    PCI__BIT(19)
0352 #define PCI_CMD_SSwapEn     PCI__BIT(20)
0353 #define PCI_CMD_MSwapEn     PCI__BIT(21)
0354 #define PCI_CMD_MIntSwapEn  PCI__BIT(22)
0355 #define PCI_CMD_LBEn        PCI__BIT(23)
0356 #define PCI_CMD_SIntSwap_GET(v) PCI__EXT(v, 24, 3)
0357 #define PCI_CMD_MBZ0_27     PCI__BIT(27)
0358
0359
0360 /*
0361  * Table 256: PCI Mode
0362  * 00:00 PciID      PCI Interface ID -- Read Only (PCI_0: 0x0; PCI_1: 0x1)
0363  * 01:01 Reserved
0364  * 02:02 Pci64      64-bit PCI Interface -- Read Only
0365  *          When set to 1, the PCI interface is configured to a
0366  *          64 bit interface.
0367  * 07:03 Reserved
0368  * 08:08 ExpRom     Expansion ROM Enable -- Read Only from PCI
0369  *          When set to 1, the expansion ROM BAR is enabled.
0370  * 09:09 VPD        VPD Enable -- Read Only from PCI
0371  *          When set to 1, VPD is supported.
0372  * 10:10 MSI        MSI Enable -- Read Only from PCI
0373  *          When set to 1, MSI is supported.
0374  * 11:11 PMG        Power Management Enable -- Read Only from PCI
0375  *          When set to 1, PMG is supported.
0376  * 12:12 HotSwap    CompactPCI Hot Swap Enable -- Read Only from PCI
0377  *          When set to 1, HotSwap is supported.
0378  * 13:13 BIST       BIST Enable -- Read only from PCI
0379  *          If set to 1, BIST is enabled.
0380  * 30:14 Reserved
0381  * 31:31 PRst       PCI Interface Reset Indication -- Read Only
0382  *          Set to 0 as long as the RST* pin is asserted.
0383  */
0384 #define PCI_MODE_PciID_GET(v)   PCI__EXT(v, 0, 1)
0385 #define PCI_MODE_Pci64      PCI__BIT(2)
0386 #define PCI_MODE_ExpRom     PCI__BIT(8)
0387 #define PCI_MODE_VPD        PCI__BIT(9)
0388 #define PCI_MODE_MSI        PCI__BIT(10)
0389 #define PCI_MODE_PMG        PCI__BIT(11)
0390 #define PCI_MODE_HotSwap    PCI__BIT(12)
0391 #define PCI_MODE_BIST       PCI__BIT(13)
0392 #define PCI_MODE_PRst       PCI__BIT(31)
0393
0394 /*
0395  * Table 257: PCI Timeout and Retry
0396  * 07:00 Timeout0   Specifies the number of PClk cycles the GT64260 slave
0397  *          holds the PCI bus before terminating a transaction
0398  *          with RETRY.
0399  * 15:08 Timeout1   Specifies the number of PClk cycles the GT64260 slave
0400  *          holds the PCI bus before terminating a transaction
0401  *          with DISCONNECT.
0402  * 23:16 RetryCtr   Retry Counter
0403  *          Specifies the number of retries of the GT64260 Master.
0404  *          The GT64260 generates an interrupt when this timer
0405  *          expires.  A 0x00 value means a retry forever.
0406  * 31:24 Reserved
0407  */
0408 #define PCI_TMORTRY_Timeout0_GET(v) PCI__EXT(v, 0, 8)
0409 #define PCI_TMORTRY_Timeout1_GET(v) PCI__EXT(v, 8, 8)
0410 #define PCI_TMORTRY_RetryCtr_GET(v) PCI__EXT(v, 16, 8)
0411
0412
0413 /*
0414  * Table 258: PCI Read Buffer Discard Timer
0415  * 15:00 Timer      Specifies the number of PClk cycles the GT64260
0416  *          slave keeps an non-accessed read buffers (non com-
0417  *          pleted delayed read) before invalidating the buffer.
0418  * 23:16 RdBufEn    Slave Read Buffers Enable
0419  *          Each bit corresponds to one of the eight read buffers.
0420  *          If set to 1, buffer is enabled.
0421  * 31:24 Reserved
0422  */
0423 #define PCI_RdBufDisTmr_Timer_GET(v)    PCI__EXT(v, 0, 16)
0424 #define PCI_RdBufDisTmr_RdBufEn_GET(v)  PCI__EXT(v, 16, 8)
0425 #define PCI_RdBufDisTmr_RdBufEn0(v) PCI__BIT(16)
0426 #define PCI_RdBufDisTmr_RdBufEn1(v) PCI__BIT(17)
0427 #define PCI_RdBufDisTmr_RdBufEn2(v) PCI__BIT(18)
0428 #define PCI_RdBufDisTmr_RdBufEn3(v) PCI__BIT(19)
0429 #define PCI_RdBufDisTmr_RdBufEn4(v) PCI__BIT(20)
0430 #define PCI_RdBufDisTmr_RdBufEn5(v) PCI__BIT(21)
0431 #define PCI_RdBufDisTmr_RdBufEn6(v) PCI__BIT(22)
0432 #define PCI_RdBufDisTmr_RdBufEn7(v) PCI__BIT(23)
0433
0434 /*
0435  * Table 259: MSI Trigger Timer
0436  * 15:00 Timer      Specifies the number of TClk cycles between consecutive
0437  *          MSI requests.
0438  * 31:16 Reserved
0439  */
0440 #define PCI_MSITrigger_Timer_GET(v) PCI__EXT(v, 0, 16)
0441
0442 /*
0443  * Table 260: PCI Arbiter Control
0444  *  NOTE:   If HPPV (bits [28:21]) is set to 0 and PAEn is set to 1,
0445  *      priority scheme is reversed. This means that high priority
0446  *      requests are granted if no low priority request is pending.
0447  * 00:00 Reserved   Must be 0. 0x0
0448  * 01:01 BDEn       Broken Detection Enable
0449  *          If set to 1, broken master detection is enabled. A mas-
0450  *          ter is said to be broken if it fails to respond to grant
0451  *          assertion within a window specified in BV (bits [6:3]).
0452  * 02:02 PAEn       Priority Arbitration Enable
0453  *          0: Low priority requests are granted only when no high
0454  *             priority request is pending
0455  *          1: Weighted round robin arbitration is performed
0456  *             between high priority and low priority groups.
0457  * 06:03 BV     Broken Value
0458  *          This value sets the maximum number of cycles that the
0459  *          arbiter waits for a PCI master to respond to its grant
0460  *          assertion. If a PCI master fails to assert FRAME* within
0461  *          this time, the PCI arbiter aborts the transaction and
0462  *          performs a new arbitration cycle and a maskable
0463  *          interrupt is generated. Must be greater than 0.
0464  *          NOTE:   The PCI arbiter waits for the current
0465  *              transaction to end before starting to
0466  *              count the wait-for-broken cycles.
0467  *          Must be greater than 1 for masters that performs address
0468  *          stepping (such as the GTO 64260 PCI master), since they
0469  *          require GNT* assertion for two cycles.
0470  * 13:07 P[6:0]     Priority
0471  *          These bits assign priority levels to the requests
0472  *          connected to the PCI arbiter. When a PM bit is set to
0473  *          1, priority of the associated request is high.  The
0474  *          mapping between P[6:0] bits and the request/grant pairs
0475  *          are as follows:
0476  *           P[0]: internal PCI master  P[1]: external REQ0/GNT0
0477  *           P[2]: external REQ1/GNT1   P[3]: external REQ2/GNT2
0478  *           P[4]: external REQ3/GNT3   P[5]: external REQ4/GNT4
0479  *           P[6]: external REQ5/GNT5
0480  * 20:14 PD[6:0]    Parking Disable
0481  *          Use these bits to disable parking on any of the PCI
0482  *          masters.  When a PD bit is set to 1, parking on the
0483  *          associated PCI master is disabled.
0484  *          NOTE:   The arbiter parks on the last master granted
0485  *              unless disabled through the PD bit. Also, if
0486  *              PD bits are all 1, the PCI arbiter parks on
0487  *              the internal PCI master.
0488  * 28:21 HPPV       High Priority Preset Value
0489  *          This is the preset value of the high priority counter
0490  *          (High_cnt). This counter decrements each time a high
0491  *          priority request is granted. When the counter reaches
0492  *          zero, it reloads with this preset value.  The counter
0493  *          reloads when a low priority request is granted.
0494  * 30:29 Reserved
0495  * 31:31 EN     Enable
0496  *          Setting this bit to 1 enables operation of the arbiter.
0497  */
0498 #define PCI_ARBCTL_MBZ0_0       PCI__BIT(0)
0499 #define PCI_ARBCTL_BDEn         PCI__BIT(1)
0500 #define PCI_ARBCTL_PAEn         PCI__BIT(2)
0501 #define PCI_ARBCTL_BV_GET(v)        PCI__EXT(v, 3, 4)
0502 #define PCI_ARBCTL_P_GET(v)     PCI__EXT(v, 7, 7)
0503 #define PCI_ARBCTL_PD_GET(v)        PCI__EXT(v, 14, 7)
0504 #define PCI_ARBCTL_HPPV_GET(v)      PCI__EXT(v, 21, 7)
0505 #define PCI_ARBCTL_EN           PCI__BIT(31)
0506
0507 #define PCI_ARBPRI_IntPci       PCI__BIT(0)
0508 #define PCI_ARBPRI_ExtReqGnt0       PCI__BIT(1)
0509 #define PCI_ARBPRI_ExtReqGnt1       PCI__BIT(2)
0510 #define PCI_ARBPRI_EXtReqGnt2       PCI__BIT(3)
0511 #define PCI_ARBPRI_EXtReqGnt3       PCI__BIT(4)
0512 #define PCI_ARBPRI_EXtReqGnt4       PCI__BIT(5)
0513 #define PCI_ARBPRI_EXtReqGnt5       PCI__BIT(6)
0514
0515 /*
0516  * Table 261: PCI Interface Crossbar Control (Low)
0517  * 03:00 Arb0       Slice 0 of PCI master pizza arbiter.
0518  * 07:04 Arb1       Slice 1 of PCI master pizza arbiter.
0519  * 11:08 Arb2       Slice 2 of PCI master pizza arbiter.
0520  * 15:12 Arb3       Slice 3 of PCI master pizza arbiter.
0521  * 19:16 Arb4       Slice 4 of PCI master pizza arbiter.
0522  * 23:20 Arb5       Slice 5 of PCI master pizza arbiter.
0523  * 27:24 Arb6       Slice 6 of PCI master pizza arbiter.
0524  * 31:28 Arb7       Slice 7 of PCI master pizza arbiter.
0525  */
0526 #define PCI_IFXBRCTL_GET_SLICE(v, n)    PCI__EXT(v, (n) * 4, 4)
0527 #define PCI_IFXBRCTL_SET_SLICE(v, n, s) ((void)(PCI__CLR(v, (n)*4, 4),\
0528                         (v) |= PCI__INS((n)*4, s)))
0529
0530 /*
0531  * Table 262: PCI Interface Crossbar Control (High)
0532  * 03:00 Arb8       Slice 8 of PCI master pizza arbiter.
0533  * 07:04 Arb9       Slice 9 of PCI master pizza arbiter.
0534  * 11:08 Arb10      Slice 10 of PCI master pizza arbiter.
0535  * 15:12 Arb11      Slice 11 of PCI master pizza arbiter.
0536  * 19:16 Arb12      Slice 12 of PCI master pizza arbiter.
0537  * 23:20 Arb13      Slice 13 of PCI master pizza arbiter.
0538  * 27:24 Arb14      Slice 14 of PCI master pizza arbiter.
0539  * 31:28 Arb15      Slice 15 of PCI master pizza arbiter.
0540  */
0541 #define PCI_IFXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4)
0542 #define PCI_IFXBRCH_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
0543                         (v) |= PCI__INS(((n)-8)*4, s)))
0544
0545 /*
0546  * Table 263: PCI Interface Crossbar Timeout
0547         (NOTE: Reserved for Galileo Technology usage.)
0548  * 07:00 Timeout    Crossbar Arbiter Timeout Preset Value
0549  * 15:08 Reserved
0550  * 16:16 TimeoutEn  Crossbar Arbiter Timer Enable (1: Disable)
0551  * 31:17 Reserved
0552  */
0553 #define PCI_IFXBRTMO_Timeout_GET(v) PCI__EXT(v, 0, 8)
0554 #define PCI_IFXBRTMO_TimeoutEn      PCI__BIT(16)
0555
0556 /*
0557  * Table 264: PCI Read Response Crossbar Control (Low)
0558  * 03:00 Arb0       Slice 0 of PCI slave pizza arbiter.
0559  * 07:04 Arb1       Slice 1 of PCI slave pizza arbiter.
0560  * 11:08 Arb2       Slice 2 of PCI slave pizza arbiter.
0561  * 15:12 Arb3       Slice 3 of PCI slave pizza arbiter.
0562  * 19:16 Arb4       Slice 4 of PCI slave pizza arbiter.
0563  * 23:20 Arb5       Slice 5 of PCI slave pizza arbiter.
0564  * 27:24 Arb6       Slice 6 of PCI slave pizza arbiter.
0565  * 31:28 Arb7       Slice 7 of PCI slave pizza arbiter.
0566  */
0567 #define PCI_RRXBRCL_GET_SLICE(v, n) PCI__EXT(v, (n) * 4, 4)
0568 #define PCI_RRXBRCL_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, (n)*4, 4),\
0569                         (v) |= PCI__INS((n)*4, s)))
0570
0571
0572 /*
0573  * Table 265: PCI Read Response Crossbar Control (High)
0574  * 03:00 Arb8       Slice 8 of PCI slave pizza arbiter.
0575  * 07:04 Arb9       Slice 9 of PCI slave pizza arbiter.
0576  * 11:08 Arb10      Slice 10 of PCI slave pizza arbiter.
0577  * 15:12 Arb11      Slice 11 of PCI slave pizza arbiter.
0578  * 19:16 Arb12      Slice 12 of PCI slave pizza arbiter.
0579  * 23:20 Arb13      Slice 13 of PCI slave pizza arbiter.
0580  * 27:24 Arb14      Slice 14 of PCI slave pizza arbiter.
0581  * 31:28 Arb15      Slice 15 of PCI slave pizza arbiter.
0582  */
0583 #define PCI_RRXBRCH_GET_SLICE(v, n) PCI__EXT(v, ((n) - 8) * 4, 4)
0584 #define PCI_RRXBRCH_SET_SLICE(v, n, s)  ((void)(PCI__CLR(v, ((n)*-8)4, 4),\
0585                         (v) |= PCI__INS(((n)-8)*4, s)))
0586
0587 /*
0588  * Table 266: PCI Sync Barrier Virtual Register
0589  * 31:0 SyncReg Sync Barrier Virtual Register
0590  * PCI read from this register results in PCI slave sync barrier
0591  * action.  The returned data is un-deterministic.  Read Only.
0592  */
0593
0594 /*
0595  * Table 267: PCI P2P Configuration
0596  * 07:00 2ndBusL    Secondary PCI Interface Bus Range Lower Boundary
0597  * 15:08 2ndBusH    Secondary PCI Interface Bus Range Upper Boundary
0598  * 23:16 BusNum     The PCI bus number to which the PCI interface
0599  *          is connected.
0600  * 28:24 DevNum     The PCI interface's device number.
0601  * 31:29 Reserved   Reserved.
0602  */
0603 #define PCI_P2PCFG_2ndBusL_GET(v)   PCI__EXT(v,  0, 8)
0604 #define PCI_P2PCFG_2ndBusH_GET(v)   PCI__EXT(v,  8, 8)
0605 #define PCI_P2PCFG_BusNum_GET(v)    PCI__EXT(v, 16, 8)
0606 #define PCI_P2PCFG_DevNum_GET(v)    PCI__EXT(v, 24, 5)
0607
0608 /*
0609  * Table 268: PCI P2P Swap Control
0610  * 02:00 M0Sw       P2P Mem0 BAR Swap Control
0611  * 03:03 M0Req64    P2P Mem0 BAR Force REQ64
0612  * 06:04 M1Sw       P2P Mem1 BAR Swap Control
0613  * 07:07 M1Req64    P2P Mem1 BAR Force REQ64
0614  * 10:08 DM0Sw      P2P DAC Mem0 BAR Swap Control
0615  * 11:11 DM0Req64   P2P DAC Mem0 BAR Force REQ64
0616  * 14:12 DM1Sw      P2P DAC Mem1 BAR Swap Control
0617  * 15:15 DM1Req64   P2P DAC Mem1 BAR Force REQ64
0618  * 18:16 IOSw       P2P I/O BAR Swap Control
0619  * 19:19 Reserved
0620  * 22:20 CfgSw      P2P Configuration Swap Control
0621  * 31:19 Reserved
0622  */
0623 #define PCI_P2PSWAP_M0Sw_GET(v)     PCI__EXT(v, 0, 3)
0624 #define PCI_P2PSWAP_M0Req64     PCI__BIT(3)
0625 #define PCI_P2PSWAP_M1Sw_GET(v)     PCI__EXT(v, 4, 3)
0626 #define PCI_P2PSWAP_M1Req64     PCI__BIT(7)
0627 #define PCI_P2PSWAP_DM0Sw_GET(v)    PCI__EXT(v, 8, 3)
0628 #define PCI_P2PSWAP_DM0Req64        PCI__BIT(11)
0629 #define PCI_P2PSWAP_DM1Sw_GET(v)    PCI__EXT(v, 12, 3)
0630 #define PCI_P2PSWAP_DM1Req64        PCI__BIT(15)
0631 #define PCI_P2PSWAP_CfgSw_GET(v)    PCI__EXT(v, 20, 3)
0632
0633
0634
0635 /*
0636  * Table 269: PCI Access Control Base (Low)
0637  * 11:00 Addr       Base Address Corresponds to address bits[31:20].
0638  * 12:12 PrefetchEn Read Prefetch Enable
0639  *          0: Prefetch disabled (The PCI slave reads single words)
0640  *          1: Prefetch enabled.
0641  * 14:14 Reserved    Must be 0
0642  * 15:15 Reserved
0643  * 16:16 RdPrefetch PCI Read Aggressive Prefetch Enable; 0: Disable;
0644  *          1: Enable (The PCI slave prefetches two
0645  *          bursts in advance)
0646  * 17:17 RdLinePrefetch PCI Read Line Aggressive Prefetch Enable; 0: Disable;
0647  *          1: Enable (PCI slave prefetch two bursts in advance)
0648  * 18:18 RdMulPrefetch  PCI Read Multiple Aggressive Prefetch Enable
0649  *          0: Disable; 1: Enable (PCI slave prefetch two bursts in
0650  *          advance)
0651  * 19:19 Reserved
0652  * 21:20 MBurst     PCI Max Burst
0653  *          Specifies the maximum burst size for a single transac-
0654  *          tion between a PCI slave and the other interfaces
0655  *              00 - 4 64-bit words
0656  *              01 - 8 64-bit words
0657  *              10 - 16 64-bit words
0658  *              11 - Reserved
0659  * 23:22 Reserved
0660  * 25:24 PCISwap    Data Swap Control
0661  *              00 - Byte Swap
0662  *              01 - No swapping
0663  *              10 - Both byte and word swap
0664  *              11 - Word swap
0665  * 26:26 Reserved   Must be 0
0666  * 27:27 Reserved
0667  * 28:28 AccProt    Access Protect (0: PCI access is allowed; 1; Region is
0668             not accessible from PCI)
0669  * 29:29 WrProt     Write Protect (0: PCI write is allowed; 1: Region is
0670  *          not writeable from PCI)
0671  * 31:30 Reserved
0672  */
0673 #define PCI_ACCCTLBASEL_Addr_GET(v) PCI__EXT(v, 0, 12)
0674 #define PCI_ACCCTLBASEL_PrefetchEn  PCI__BIT(12)
0675 #define PCI_ACCCTLBASEL_MBZ0_14     PCI__BIT(14)
0676 #define PCI_ACCCTLBASEL_RdPrefetch  PCI__BIT(16)
0677 #define PCI_ACCCTLBASEL_RdLinePrefetch  PCI__BIT(17)
0678 #define PCI_ACCCTLBASEL_RdMulPrefetch   PCI__BIT(18)
0679 #define PCI_ACCCTLBASEL_WBurst      PCI__EXT(v, 20, 2)
0680 #define PCI_ACCCTLBASEL_WBurst_8_QW PCI__INS(20, PCI_WBURST_8_QW)
0681 #define PCI_ACCCTLBASEL_PCISwap     PCI__EXT(v, 24, 2)
0682 #define PCI_ACCCTLBASEL_PCISwap_NoSwap  PCI__INS(24, PCI_PCISWAP_NoSwap)
0683 #define PCI_ACCCTLBASEL_MBZ0_26     PCI__BIT(26)
0684 #define PCI_ACCCTLBASEL_AccProt     PCI__BIT(28)
0685 #define PCI_ACCCTLBASEL_WrProt      PCI__BIT(29)
0686
0687 #define PCI_WBURST_4_QW         0x00
0688 #define PCI_WBURST_8_QW         0x01
0689 #define PCI_WBURST_16_QW        0x02
0690 #define PCI_WBURST_Reserved     0x04
0691
0692 #define PCI_PCISWAP_ByteSwap        0x00
0693 #define PCI_PCISWAP_NoSwap      0x01
0694 #define PCI_PCISWAP_ByteWordSwap    0x02
0695 #define PCI_PCISWAP_WordSwap        0x04
0696
0697 /*
0698  * Table 293: PCI Snoop Control Base (Low)
0699  * 11:00 Addr       Base Address     Corresponds to address bits[31:20].
0700  * 13:12 Snoop      Snoop Type
0701  * 31:14 Reserved
0702  */
0703 #define PCI_SNOOPCTL_ADDR(v)    PCI__EXT(v, 0, 12)
0704 #define PCI_SNOOPCTL_TYPE(v)    PCI__EXT(v, 12, 2)
0705
0706 #define PCI_SNOOP_None      0   /* no snoop */
0707 #define PCI_SNOOP_WT        1   /* Snoop to WT region */
0708 #define PCI_SNOOP_WB        2   /* Snoop to WB region */
0709
0710
0711 /*
0712  * Table 305: PCI Configuration Address
0713  *
0714  * 07:02 RegNum     Register number.
0715  * 10:08 FunctNum   Function number.
0716  * 15:11 DevNum     Device number.
0717  * 23:16 BusNum     Bus number.
0718  * 31:31 ConfigEn   When set, an access to the Configuration Data
0719  *          register is translated into a Configuration
0720  *          or Special cycle on the PCI bus.
0721  */
0722 #define PCI_CFG_MAKE_TAG(bus, dev, fun, reg)    (PCI__BIT(31)|\
0723                          PCI__INS(16, (bus))|\
0724                          PCI__INS(11, (dev))|\
0725                          PCI__INS( 8, (fun))|\
0726                          PCI__INS( 0, (reg)))
0727 #define PCI_CFG_GET_BUSNO(tag)          PCI__EXT(tag, 16, 8)
0728 #define PCI_CFG_GET_DEVNO(tag)          PCI__EXT(tag, 11, 5)
0729 #define PCI_CFG_GET_FUNCNO(tag)         PCI__EXT(tag,  8, 3)
0730 #define PCI_CFG_GET_REGNO(tag)          PCI__EXT(tag,  0, 8)
0731
0732 /*
0733  * Table 306: PCI Configuration Data
0734  *
0735  * 31:00 ConfigData The data is transferred to/from the PCI bus when
0736  *          the CPU accesses this register and the ConfigEn
0737  *          bit in the Configuration Address register is set
0738  *
0739  * A CPU access to this register causes the GT64260 to perform a Configuration
0740  * or Special cycle on the PCI bus.
0741  */
0742
0743
0744 /*
0745  * Table 307: PCI Interrupt Acknowledge (This register is READ ONLY)
0746  * 31:00 IntAck     A CPU read access to this register forces an
0747  *          interrupt acknowledge cycle on the PCI bus.
0748  */
0749
0750
0751 /*
0752  * Table 308: PCI SERR* Mask
0753  *
0754  * NOTE: The GT64260 asserts SERR* only if SERR* is enabled via the PCI Status
0755  *       and Command register.
0756  * If the corresponding bit is set, then asserts SERR* upon ...
0757  */
0758 #define PCI_SERRMSK_SAPerr  PCI__BIT(0) /* PCI slave detection of bad
0759                          * address parity. */
0760 #define PCI_SERRMSK_SWrPerr PCI__BIT(1) /* PCI slave detection of bad
0761                          * write data parity. */
0762 #define PCI_SERRMSK_SRdPerr PCI__BIT(2) /* a PERR* response to read
0763                          * data driven by the PCI
0764                          * slave. */
0765 #define PCI_SERRMSK_MAPerr  PCI__BIT(4) /* a PERR* response to an
0766                          * address driven by the PCI
0767                          * master. */
0768 #define PCI_SERRMSK_MWrPerr PCI__BIT(5) /* a PERR* response to write
0769                          * data driven by the PCI
0770                          * master. */
0771 #define PCI_SERRMSK_MRdPerr PCI__BIT(6) /* bad data parity detection
0772                          * during a PCI master read
0773                          * transaction. */
0774 #define PCI_SERRMSK_MMabort PCI__BIT(8) /* a PCI master generation of
0775                          * master abort. */
0776 #define PCI_SERRMSK_MTabort PCI__BIT(9) /* a PCI master detection of
0777                          * target abort. */
0778 #define PCI_SERRMSK_MRetry  PCI__BIT(11)    /* a PCI master reaching retry
0779                          * counter limit. */
0780 #define PCI_SERRMSK_SMabort PCI__BIT(16)    /* a PCI slave detection of
0781                          * master abort. */
0782 #define PCI_SERRMSK_STabort PCI__BIT(17)    /* a PCI slave termination of
0783                          * a transaction with Target
0784                          * Abort. */
0785 #define PCI_SERRMSK_SAccProt    PCI__BIT(18)    /* a PCI slave access protect
0786                          * violation. */
0787 #define PCI_SERRMSK_SWrProt PCI__BIT(19)    /* a PCI slave write protect
0788                          * violation. */
0789 #define PCI_SERRMSK_SRdBuf  PCI__BIT(20)    /* the PCI slave's read buffer,
0790                          * discard timer expires */
0791 #define PCI_SERRMSK_Arb     PCI__BIT(21)    /* the internal PCI arbiter
0792                          * detection of a broken PCI
0793                          * master. */
0794
0795 #define PCI_SERRMSK_ALL_ERRS \
0796     (PCI_SERRMSK_SAPerr|PCI_SERRMSK_SWrPerr|PCI_SERRMSK_SRdPerr \
0797     |PCI_SERRMSK_MAPerr|PCI_SERRMSK_MWrPerr|PCI_SERRMSK_MRdPerr \
0798     |PCI_SERRMSK_MMabort|PCI_SERRMSK_MTabort|PCI_SERRMSK_MRetry \
0799     |PCI_SERRMSK_SMabort|PCI_SERRMSK_STabort|PCI_SERRMSK_SAccProt \
0800     |PCI_SERRMSK_SWrProt|PCI_SERRMSK_SRdBuf|PCI_SERRMSK_Arb)
0801
0802
0803
0804 /*
0805  * Table 309: PCI Error Address (Low) -- Read Only.
0806  * 31:00 ErrAddr    PCI address bits [31:0] are latched upon an error
0807  *          condition.  Upon address latch, no new addresses can
0808  *          be registered (due to additional error condition) until
0809  *          the register is being read.
0810  */
0811
0812
0813
0814 /*
0815  * Table 310: PCI Error Address (High)  Applicable only when running DAC cycles.
0816  * 31:00 ErrAddr    PCI address bits [63:32] are latched upon
0817  *          error condition.
0818  *
0819  * NOTE: Upon data sample, no new data is latched until the PCI Error Low
0820  *       Address register is read. This means that PCI Error Low Address
0821  *       register must bethe last register read by the interrupt handler.
0822  */
0823
0824 /*
0825  * Table 311: PCI Error Data (Low)
0826  * 31:00 ErrData    PCI data bits [31:00] are latched upon error condition.
0827  */
0828
0829 /*
0830  * Table 312: PCI Error Data (High) Applicable only when running
0831  *                  64-bit cycles.
0832  * 31:00 ErrData    PCI data bits [63:32] are latched upon error condition.
0833  */
0834
0835 /*
0836  * Table 313: PCI Error Command
0837  * 03:00 ErrCmd     PCI command is latched upon error condition.
0838  * 07:04 Reserved
0839  * 15:08 ErrBE      PCI byte enable is latched upon error condition.
0840  * 16:16 ErrPAR     PCI PAR is latched upon error condition.
0841  * 17:17 ErrPAR64   PCI PAR64 is latched upon error condition.
0842  *          Applicable only when running 64-bit cycles.
0843  * 31:18 Reserved
0844  * NOTE: Upon data sample, no new data is latched until the PCI Error Low
0845  * Address register is read. This means that PCI Error Low Address register
0846  * must be the last register read by the interrupt handler.
0847  */
0848 #define PCI_ERRCMD_Cmd_GET(v)       PCI__EXT(v, 0, 4)
0849 #define PCI_ERRCMD_ByteEn_GET(v)    PCI__EXT(v, 8, 8)
0850 #define PCI_ERRCMD_PAR          PCI__BIT(16)
0851 #define PCI_ERRCMD_PAR64        PCI__BIT(17)
0852
0853 /*
0854  * Table 314: PCI Interrupt Cause
0855  * 1. All bits are Clear Only. A cause bit set upon error event occurrence.
0856  *    A write of 0 clears the bit. A write of 1 has no affect.
0857  * 2. PCI Interrupt bits are organized in four groups:
0858  *    bits[ 7: 0] for address and data parity errors,
0859  *    bits[15: 8] for PCI master transaction failure (possible external
0860  *        target problem),
0861  *    bits[23:16] for slave response failure (possible external master problem),
0862  *    bits[26:24] for external PCI events that require CPU handle.
0863  */
0864 #define PCI_IC_SAPerr       PCI__BIT(0) /* The PCI slave detected
0865                          * bad address parity. */
0866 #define PCI_IC_SWrPerr      PCI__BIT(1) /* The PCI slave detected
0867                          * bad write data parity. */
0868 #define PCI_IC_SRdPerr      PCI__BIT(2) /* PERR* response to read
0869                          * data driven by PCI slave. */
0870 #define PCI_IC_MAPerr       PCI__BIT(4) /* PERR* response to address
0871                          * driven by the PCI master. */
0872 #define PCI_IC_MWrPerr      PCI__BIT(5) /* PERR* response to write data
0873                          * driven by the PCI master. */
0874 #define PCI_IC_MRdPerr      PCI__BIT(6) /* Bad data parity detected
0875                          * during the PCI master read
0876                          * transaction. */
0877 #define PCI_IC_MMabort      PCI__BIT(8) /* The PCI master generated
0878                          * master abort. */
0879 #define PCI_IC_MTabort      PCI__BIT(9) /* The PCI master detected
0880                          * target abort. */
0881 #define PCI_IC_MMasterEn    PCI__BIT(10)    /* An attempt to generate a PCI
0882                          * transaction while master is
0883                          * not enabled. */
0884 #define PCI_IC_MRetry       PCI__BIT(11)    /* The PCI master reached
0885                          * retry counter limit. */
0886 #define PCI_IC_SMabort      PCI__BIT(16)    /* The PCI slave detects an il-
0887                          * legal master termination. */
0888 #define PCI_IC_STabort      PCI__BIT(17)    /* The PCI slave terminates a
0889                          * transaction with Target
0890                          * Abort. */
0891 #define PCI_IC_SAccProt     PCI__BIT(18)    /* A PCI slave access protect
0892                          * violation. */
0893 #define PCI_IC_SWrProt      PCI__BIT(19)    /* A PCI slave write protect
0894                          * violation. */
0895 #define PCI_IC_SRdBuf       PCI__BIT(20)    /* A PCI slave read buffer
0896                          * discard timer expired. */
0897 #define PCI_IC_Arb      PCI__BIT(21)    /* Internal PCI arbiter detec-
0898                          * tion of a broken master. */
0899 #define PCI_IC_BIST     PCI__BIT(24)    /* PCI BIST Interrupt */
0900 #define PCI_IC_PMG      PCI__BIT(25)    /* PCI Power Management
0901                          * Interrupt */
0902 #define PCI_IC_PRST     PCI__BIT(26)    /* PCI Reset Assert */
0903
0904 /*
0905 31:27 Sel Specifies the error event currently being reported in the
0906 Error Address, Error Data, and Error Command registers.
0907 */
0908 #define PCI_IC_SEL_GET(v)   PCI__EXT((v), 27, 5)
0909 #define PCI_IC_SEL_SAPerr   0x00
0910 #define PCI_IC_SEL_SWrPerr  0x01
0911 #define PCI_IC_SEL_SRdPerr  0x02
0912 #define PCI_IC_SEL_MAPerr   0x04
0913 #define PCI_IC_SEL_MWrPerr  0x05
0914 #define PCI_IC_SEL_MRdPerr  0x06
0915 #define PCI_IC_SEL_MMabort  0x08
0916 #define PCI_IC_SEL_MTabort  0x09
0917 #define PCI_IC_SEL_MMasterEn    0x0a
0918 #define PCI_IC_SEL_MRetry   0x0b
0919 #define PCI_IC_SEL_SMabort  0x10
0920 #define PCI_IC_SEL_STabort  0x11
0921 #define PCI_IC_SEL_SAccProt 0x12
0922 #define PCI_IC_SEL_SWrProt  0x13
0923 #define PCI_IC_SEL_SRdBuf   0x14
0924 #define PCI_IC_SEL_Arb      0x15
0925 #define PCI_IC_SEL_BIST     0x18
0926 #define PCI_IC_SEL_PMG      0x19
0927 #define PCI_IC_SEL_PRST     0x1a
0928
0929 #define PCI_IC_SEL_Strings { \
0930     "SAPerr",  "SWrPerr", "SRdPerr",   "Rsvd#03", \
0931     "MAPerr",  "MWrPerr", "MRdPerr",   "Rsvd#07", \
0932     "MMabort", "MTabort", "MMasterEn", "MRetry", \
0933     "Rsvd#0c", "Rsvd#0d", "Rsvd#0e",   "Rsvd#0f", \
0934     "SMabort", "STabort", "SAccProt",  "SWrProt", \
0935     "SRdBuf",  "Arb",     "Rsvd#16",   "Rsvd#17", \
0936     "BIST",    "PMG",     "PRST",      "Rsvd#1b", \
0937     "Rsvd#1c", "Rsvd#1d", "Rsvd#1e",   "Rsvd#1f" }
0938
0939 /*
0940  * Table 315: PCI Error Mask
0941  * If the corresponding bit is 1, that interrupt is enabled
0942  * Bits 3, 7, 12:15, 22:23, 27:31 are reserved.
0943  */
0944 #define PCI_ERRMASK_SAPErr      PCI__BIT(0)
0945 #define PCI_ERRMASK_SWrPErr     PCI__BIT(1)
0946 #define PCI_ERRMASK_SRdPErr     PCI__BIT(2)
0947 #define PCI_ERRMASK_MAPErr      PCI__BIT(4)
0948 #define PCI_ERRMASK_MWRPErr     PCI__BIT(5)
0949 #define PCI_ERRMASK_MRDPErr     PCI__BIT(6)
0950 #define PCI_ERRMASK_MMAbort     PCI__BIT(8)
0951 #define PCI_ERRMASK_MTAbort     PCI__BIT(9)
0952 #define PCI_ERRMASK_MMasterEn       PCI__BIT(10)
0953 #define PCI_ERRMASK_MRetry      PCI__BIT(11)
0954 #define PCI_ERRMASK_SMAbort     PCI__BIT(16)
0955 #define PCI_ERRMASK_STAbort     PCI__BIT(17)
0956 #define PCI_ERRMASK_SAccProt        PCI__BIT(18)
0957 #define PCI_ERRMASK_SWrProt     PCI__BIT(19)
0958 #define PCI_ERRMASK_SRdBuf      PCI__BIT(20)
0959 #define PCI_ERRMASK_Arb         PCI__BIT(21)
0960 #define PCI_ERRMASK_BIST        PCI__BIT(24)
0961 #define PCI_ERRMASK_PMG         PCI__BIT(25)
0962 #define PCI_ERRMASK_PRST        PCI__BIT(26)
0963
0964 #endif /* _DEV_GTPCIREG_H_ */