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File indexing completed on 2025-05-11 08:23:51
0001 /* $NetBSD: gtintrreg.h,v 1.3 2005/02/27 00:27:21 perry Exp $ */ 0002 0003 /* 0004 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 0005 * All rights reserved. 0006 * 0007 * Redistribution and use in source and binary forms, with or without 0008 * modification, are permitted provided that the following conditions 0009 * are met: 0010 * 1. Redistributions of source code must retain the above copyright 0011 * notice, this list of conditions and the following disclaimer. 0012 * 2. Redistributions in binary form must reproduce the above copyright 0013 * notice, this list of conditions and the following disclaimer in the 0014 * documentation and/or other materials provided with the distribution. 0015 * 3. All advertising materials mentioning features or use of this software 0016 * must display the following acknowledgement: 0017 * This product includes software developed for the NetBSD Project by 0018 * Allegro Networks, Inc., and Wasabi Systems, Inc. 0019 * 4. The name of Allegro Networks, Inc. may not be used to endorse 0020 * or promote products derived from this software without specific prior 0021 * written permission. 0022 * 5. The name of Wasabi Systems, Inc. may not be used to endorse 0023 * or promote products derived from this software without specific prior 0024 * written permission. 0025 * 0026 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND 0027 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 0028 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 0029 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 0030 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC. 0031 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0032 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0033 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0034 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0035 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0036 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0037 * POSSIBILITY OF SUCH DAMAGE. 0038 */ 0039 0040 /* 0041 * gt64260intr.h: defines for GT-64260 system controller interrupts 0042 * 0043 * creation Sun Jan 7 18:05:59 PST 2001 cliff 0044 * 0045 * NOTE: 0046 * Galileo GT-64260 manual bit defines assume Little Endian 0047 * ordering of bits within bytes, i.e. 0048 * bit #0 --> 0x01 0049 * vs. Motorola Big Endian bit numbering where 0050 * bit #0 --> 0x80 0051 * Consequently we define bits in Little Endian format and plan 0052 * to swizzle bytes during programmed I/O by using lwbrx/swbrx 0053 * to load/store GT-64260 registers. 0054 */ 0055 0056 0057 #ifndef _DISCOVERY_GT64260INTR_H 0058 #define _DISCOVERY_GT64260INTR_H 0059 0060 #define BIT(n) (1<<(n)) 0061 0062 0063 /* 0064 * GT-64260 Interrupt Controller Register Map 0065 */ 0066 #define ICR_260_MIC_LO 0xc18 /* main interrupt cause low */ 0067 #define ICR_260_MIC_HI 0xc68 /* main interrupt cause high */ 0068 #define ICR_260_CIM_LO 0xc1c /* CPU interrupt mask low */ 0069 #define ICR_260_CIM_HI 0xc6c /* CPU interrupt mask high */ 0070 #define ICR_260_CSC 0xc70 /* CPU select cause */ 0071 #define ICR_260_P0IM_LO 0xc24 /* PCI_0 interrupt mask low */ 0072 #define ICR_260_P0IM_HI 0xc64 /* PCI_0 interrupt mask high */ 0073 #define ICR_260_P0SC 0xc74 /* PCI_0 select cause */ 0074 #define ICR_260_P1IM_LO 0xca4 /* PCI_1 interrupt mask low */ 0075 #define ICR_260_P1IM_HI 0xce4 /* PCI_1 interrupt mask high */ 0076 #define ICR_260_P1SC 0xcf4 /* PCI_1 select cause */ 0077 #define ICR_260_CI0M 0xe60 /* CPU int[0] mask */ 0078 #define ICR_260_CI1M 0xe64 /* CPU int[1] mask */ 0079 #define ICR_260_CI2M 0xe68 /* CPU int[2] mask */ 0080 #define ICR_260_CI3M 0xe6c /* CPU int[3] mask */ 0081 0082 /* 0083 * MV64360 Interrupt Controller Register Map 0084 */ 0085 #define ICR_360_MIC_LO 0x004 /* main interrupt cause low */ 0086 #define ICR_360_MIC_HI 0x00c /* main interrupt cause high */ 0087 #define ICR_360_C0IM_LO 0x014 /* CPU 0 interrupt mask low */ 0088 #define ICR_360_C0IM_HI 0x01c /* CPU 0 interrupt mask high */ 0089 #define ICR_360_C0SC 0x024 /* CPU 0 select cause */ 0090 #define ICR_360_C1IM_LO 0x034 /* CPU 1 interrupt mask low */ 0091 #define ICR_360_C1IM_HI 0x03c /* CPU 1 interrupt mask high */ 0092 #define ICR_360_C1SC 0x044 /* CPU 1 select cause */ 0093 #define ICR_360_I0M_LO 0x014 /* Int 0 mask low */ 0094 #define ICR_360_I0M_HI 0x01c /* Int 0 mask high */ 0095 #define ICR_360_I0SC 0x024 /* Int 0 select cause */ 0096 #define ICR_360_I1M_LO 0x034 /* Int 1 mask low */ 0097 #define ICR_360_I1M_HI 0x03c /* Int 1 mask high */ 0098 #define ICR_360_C1SC 0x044 /* Int 1 select cause */ 0099 0100 0101 /* 0102 * IRQs: 0103 * we define IRQs based on bit number in the 0104 * ICU_LEN dimensioned hardware portion of the imask_t bit vector 0105 * which consists of 64 bits of Main Cause and Mask register pairs 0106 * (ICR_MIC_LO, ICR_MIC_HI and ICR_CIM_LO, ICR_CIM_HI) 0107 * as well as 32 bits in GPP registers (see intr.h): 0108 * 0109 * IRQs: 0110 * 31.............................0 63.............................32 0111 * | | | 0112 * imask_t index: | | | 0113 * | | | | 0114 * ^--------- IM_PIC_LO ----------^ ^------ IM_PIC_HI ------------^ 0115 * | | | 0116 * Bitmasks: | | | 0117 * | | | | 0118 * ^--------- IML_* --------------^ ^------ IMH_* ----------------^ 0119 * | | | 0120 * Registers: | | | 0121 * | | | | 0122 * ^--------- ICR_MIC_LO ---------^ ^------ ICR_MIC_HI -----------^ 0123 * ^--------- ICR_CIM_LO ---------^ ^------ ICR_CIM_HI -----------^ 0124 * 0125 * IRQs: 0126 * 95............................64 127............................96 0127 * | | | 0128 * imask_t index: | | | 0129 * | | | | 0130 * ^-------- IMASK_GPP ----------^ ^----- IMASK_SOFTINT --------^ 0131 * | | | 0132 * Bitmasks: | | | 0133 * | | | | 0134 * ^--------- GPP_* --------------^ ^------ SIBIT(irq) -----------^ 0135 * | | | 0136 * Registers: | | | 0137 * | | | | 0138 * ^--- GT_GPP_Interrupt_Cause ---^ ^------- (none) -----------^ 0139 * ^--- GT_GPP_Interrupt_Mask ---^ 0140 * 0141 * 0142 * Note that GPP interrupts are summarized in the Main Cause Register. 0143 * 0144 * Some IRQs are "resvered" undefined due to gaps in HW register utilization. 0145 */ 0146 #define IRQ_DEV 1 /* device interface interrupt */ 0147 #define IRQ_DMA 2 /* DMA addres error interrupt */ 0148 #define IRQ_CPU 3 /* CPU interface interrupt */ 0149 #define IRQ_IDMA0_1 4 /* IDMA ch. 0..1 complete interrupt */ 0150 #define IRQ_IDMA2_3 5 /* IDMA ch. 2..3 complete interrupt */ 0151 #define IRQ_IDMA4_5 6 /* IDMA ch. 4..5 complete interrupt */ 0152 #define IRQ_IDMA6_7 7 /* IDMA ch. 6..7 complete interrupt */ 0153 #define IRQ_TIME0_1 8 /* Timer 0..1 interrupt */ 0154 #define IRQ_TIME2_3 9 /* Timer 2..3 interrupt */ 0155 #define IRQ_TIME4_5 10 /* Timer 4..5 interrupt */ 0156 #define IRQ_TIME6_7 11 /* Timer 6..7 interrupt */ 0157 #define IRQ_PCI0_0 12 /* PCI 0 interrupt 0 summary */ 0158 #define IRQ_PCI0_1 13 /* PCI 0 interrupt 1 summary */ 0159 #define IRQ_PCI0_2 14 /* PCI 0 interrupt 2 summary */ 0160 #define IRQ_PCI0_3 15 /* PCI 0 interrupt 3 summary */ 0161 #define IRQ_PCI1_0 16 /* PCI 1 interrupt 0 summary */ 0162 #define IRQ_ECC 17 /* ECC error interrupt */ 0163 #define IRQ_PCI1_1 18 /* PCI 1 interrupt 1 summary */ 0164 #define IRQ_PCI1_2 19 /* PCI 1 interrupt 2 summary */ 0165 #define IRQ_PCI1_3 20 /* PCI 1 interrupt 3 summary */ 0166 #define IRQ_PCI0OUT_LO 21 /* PCI 0 outbound interrupt summary */ 0167 #define IRQ_PCI0OUT_HI 22 /* PCI 0 outbound interrupt summary */ 0168 #define IRQ_PCI1OUT_LO 23 /* PCI 1 outbound interrupt summary */ 0169 #define IRQ_PCI1OUT_HI 24 /* PCI 1 outbound interrupt summary */ 0170 #define IRQ_PCI0IN_LO 26 /* PCI 0 inbound interrupt summary */ 0171 #define IRQ_PCI0IN_HI 27 /* PCI 0 inbound interrupt summary */ 0172 #define IRQ_PCI1IN_LO 28 /* PCI 1 inbound interrupt summary */ 0173 #define IRQ_PCI1IN_HI 29 /* PCI 1 inbound interrupt summary */ 0174 #define IRQ_ETH0 (32+0) /* Ethernet controller 0 interrupt */ 0175 #define IRQ_ETH1 (32+1) /* Ethernet controller 1 interrupt */ 0176 #define IRQ_ETH2 (32+2) /* Ethernet controller 2 interrupt */ 0177 #define IRQ_SDMA (32+4) /* SDMA interrupt */ 0178 #define IRQ_I2C (32+5) /* I2C interrupt */ 0179 #define IRQ_BRG (32+7) /* Baud Rate Generator interrupt */ 0180 #define IRQ_MPSC0 (32+8) /* MPSC 0 interrupt */ 0181 #define IRQ_MPSC1 (32+10) /* MPSC 1 interrupt */ 0182 #define IRQ_COMM (32+11) /* Comm unit interrupt */ 0183 #define IRQ_GPP7_0 (32+24) /* GPP[7..0] interrupt */ 0184 #define IRQ_GPP15_8 (32+25) /* GPP[15..8] interrupt */ 0185 #define IRQ_GPP23_16 (32+26) /* GPP[23..16] interrupt */ 0186 #define IRQ_GPP31_24 (32+27) /* GPP[31..24] interrupt */ 0187 0188 /* 0189 * low word interrupt mask register bits 0190 */ 0191 #define IML_SUM BIT(0) 0192 #define IML_DEV BIT(IRQ_DEV) 0193 #define IML_DMA BIT(IRQ_DMA) 0194 #define IML_CPU BIT(IRQ_CPU) 0195 #define IML_IDMA0_1 BIT(IRQ_IDMA0_1) 0196 #define IML_IDMA2_3 BIT(IRQ_IDMA2_3) 0197 #define IML_IDMA4_5 BIT(IRQ_IDMA4_5) 0198 #define IML_IDMA6_7 BIT(IRQ_IDMA6_7) 0199 #define IML_TIME0_1 BIT(IRQ_TIME0_1) 0200 #define IML_TIME2_3 BIT(IRQ_TIME2_3) 0201 #define IML_TIME4_5 BIT(IRQ_TIME4_5) 0202 #define IML_TIME6_7 BIT(IRQ_TIME6_7) 0203 #define IML_PCI0_0 BIT(IRQ_PCI0_0) 0204 #define IML_PCI0_1 BIT(IRQ_PCI0_1) 0205 #define IML_PCI0_2 BIT(IRQ_PCI0_2) 0206 #define IML_PCI0_3 BIT(IRQ_PCI0_3) 0207 #define IML_PCI1_0 BIT(IRQ_PCI1_0) 0208 #define IML_ECC BIT(IRQ_ECC) 0209 #define IML_PCI1_1 BIT(IRQ_PCI1_1) 0210 #define IML_PCI1_2 BIT(IRQ_PCI1_2) 0211 #define IML_PCI1_3 BIT(IRQ_PCI1_3) 0212 #define IML_PCI0OUT_LO BIT(IRQ_PCI0OUT_LO) 0213 #define IML_PCI0OUT_HI BIT(IRQ_PCI0OUT_HI) 0214 #define IML_PCI1OUT_LO BIT(IRQ_PCI1OUT_LO) 0215 #define IML_PCI1OUT_HI BIT(IRQ_PCI1OUT_HI) 0216 #define IML_PCI0IN_LO BIT(IRQ_PCI0IN_LO) 0217 #define IML_PCI0IN_HI BIT(IRQ_PCI0IN_HI) 0218 #define IML_PCI1IN_LO BIT(IRQ_PCI1IN_LO) 0219 #define IML_PCI1IN_HI BIT(IRQ_PCI1IN_HI) 0220 #define IML_RES (BIT(25)|BIT(30)|BIT(31)) 0221 0222 /* 0223 * high word interrupt mask register bits 0224 */ 0225 #define IMH_ETH0 BIT(IRQ_ETH0-32) 0226 #define IMH_ETH1 BIT(IRQ_ETH1-32) 0227 #define IMH_ETH2 BIT(IRQ_ETH2-32) 0228 #define IMH_SDMA BIT(IRQ_SDMA-32) 0229 #define IMH_I2C BIT(IRQ_I2C-32) 0230 #define IMH_BRG BIT(IRQ_BRG-32) 0231 #define IMH_MPSC0 BIT(IRQ_MPSC0-32) 0232 #define IMH_MPSC1 BIT(IRQ_MPSC1-32) 0233 #define IMH_COMM BIT(IRQ_COMM-32) 0234 #define IMH_GPP7_0 BIT(IRQ_GPP7_0-32) 0235 #define IMH_GPP15_8 BIT(IRQ_GPP15_8-32) 0236 #define IMH_GPP23_16 BIT(IRQ_GPP23_16-32) 0237 #define IMH_GPP31_24 BIT(IRQ_GPP31_24-32) 0238 #define IMH_GPP_SUM (IMH_GPP7_0|IMH_GPP15_8|IMH_GPP23_16|IMH_GPP31_24) 0239 #define IMH_RES (BIT(3) |BIT(6) |BIT(9) |BIT(12)|BIT(13)|BIT(14) \ 0240 |BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20) \ 0241 |BIT(21)|BIT(22)|BIT(23)|BIT(28)|BIT(29)|BIT(30) \ 0242 |BIT(31)) 0243 0244 /* 0245 * ICR_CSC "Select Cause" register bits 0246 */ 0247 #define CSC_SEL BIT(30) /* HI/LO select */ 0248 #define CSC_STAT BIT(31) /* ? "irq active" : "irq none" */ 0249 #define CSC_CAUSE ~(CSC_SEL|CSC_STAT) 0250 0251 0252 /* 0253 * CPU Int[n] Mask bit(s) 0254 */ 0255 #define CPUINT_SEL 0x80000000 /* HI/LO select */ 0256 0257 #endif /* _DISCOVERY_GT64260INTR_H */
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