include/bsp/gti2creg.h

0001 /*  $NetBSD: gti2creg.h,v 1.2 2005/02/27 00:27:21 perry Exp $   */
0002
0003 /*
0004  * Copyright (c) 2005 Brocade Communcations, inc.
0005  * All rights reserved.
0006  *
0007  * Written by Matt Thomas for Brocade Communcations, Inc.
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  * 3. The name of Brocade Communications, Inc. may not be used to endorse
0018  *    or promote products derived from this software without specific prior
0019  *    written permission.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY BROCADE COMMUNICATIONS, INC. ``AS IS'' AND
0022  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED.  IN NO EVENT SHALL EITHER BROCADE COMMUNICATIONS, INC. BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
0031  * OF THE POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #ifndef _DEV_MARVELL_GTI2CREG_H_
0035 #define _DEV_MARVELL_GTI2CREG_H_
0036
0037 #define I2C_REG_SlaveAddr   0xc000
0038 #define I2C_REG_ExtSlaveAddr    0xc010
0039 #define I2C_REG_Data        0xc004
0040 #define I2C_REG_Control     0xc008
0041 #define I2C_REG_Status      0xc00c
0042 #define I2C_REG_BaudRate    0xc00c
0043 #define I2C_REG_SoftReset   0xc01c
0044
0045 #define I2C_SlaveAddr_GCE   0x0001  /* Act as Slave */
0046 #define I2C_SlaveAddr_SAddr 0x7E
0047
0048 #define I2C_Control_ACK     0x04
0049 #define I2C_Control_IFlg    0x08
0050 #define I2C_Control_Stop    0x10
0051 #define I2C_Control_Start   0x20
0052 #define I2C_Control_TWSIEn  0x40
0053 #define I2C_Control_IntEn   0x80
0054
0055 /*
0056  * F(I2C) = F(Tclk) / ( 10 * (M + 1) * (2^(N+1)))
0057  * For Tclk = 100MHz, M =  4, N = 4: F = 62.5KHz
0058  * For Tclk = 100MHz, M = 13, N = 3: F = 96.2KHz
0059  */
0060 #define I2C_BaudRate(M, N)  (((M) << 3) | (N))
0061 #define I2C_BaudRate_62_5K  I2C_BaudRate(4, 4)
0062 #define I2C_BaudRate_96_2K  I2C_BaudRate(13, 3)
0063
0064 #define I2C_Status_BusError 0x00    /* Bus error */
0065 #define I2C_Status_Started  0x08    /* Start condition xmitted */
0066 #define I2C_Status_ReStarted    0x10    /* Repeated start condition xmitted */
0067 #define I2C_Status_AddrWriteAck 0x18    /* Adr + wr bit xmtd, ack rcvd */
0068 #define I2C_Status_AddrWriteNoAck 0x20  /* Adr + wr bit xmtd, NO ack rcvd */
0069 #define I2C_Status_MasterWriteAck 0x28  /* Master xmtd data byte, ack rcvd */
0070 #define I2C_Status_MasterWriteNoAck 0x30 /* Master xmtd data byte, NO ack rcvd*/
0071 #define I2C_Status_MasterLostArb 0x38   /* Master lost arbitration during
0072                        address or data transfer */
0073 #define I2C_Status_AddrReadAck  0x40    /* Adr + rd bit xmtd, ack rcvd */
0074 #define I2C_Status_AddrReadNoAck 0x48   /* Adr + rd bit xmtd, NO ack rcvd */
0075 #define I2C_Status_MasterReadAck 0x50   /* Master rcvd data bye, ack rcvd */
0076 #define I2C_Status_MasterReadNoAck 0x58 /* Master rcvd data bye, NO ack rcvd */
0077 #define I2C_Status_2ndAddrWriteAck 0xd0 /* 2nd adr + wr bit xmid, ack rcvd */
0078 #define I2C_Status_2ndAddrWriteNoAck 0xd8 /* 2nd adr + wr bit xmid, NO ack rcvd */
0079 #define I2C_Status_2ndAddrReadAck 0xe0  /* 2nd adr + rd bit xmid, ack rcvd */
0080 #define I2C_Status_2ndAddrReadNoAck 0xe8 /* 2nd adr + rd bit xmtd, NO ack rcvd */
0081 #define I2C_Status_Idle     0xf8    /* Idle */
0082
0083 #endif /* _DEV_MARVELL_GTI2CREG_H_ */