include/bsp/generic_or1k.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup generic_or1k_reg
0005  *
0006  * @brief Register definitions.
0007  */
0008
0009 /*
0010  * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
0011  *
0012  * The license and distribution terms for this file may be
0013  * found in the file LICENSE in this distribution or at
0014  * http://www.rtems.org/license/LICENSE
0015  */
0016
0017 #ifndef LIBBSP_GENERIC_OR1K_H
0018 #define LIBBSP_GENERIC_OR1K_H
0019
0020 #include <stdint.h>
0021
0022 /**
0023  * @defgroup generic_or1k_reg Register Definitions
0024  *
0025  * @ingroup RTEMSBSPsOR1K
0026  *
0027  * @brief Shared register definitions for or1k systems.
0028  *
0029  * @{
0030  */
0031
0032 /**
0033  * @name Register Macros
0034  *
0035  * @{
0036  */
0037
0038  #define OR1K_REG(x)           (*((volatile unsigned char *) (x)))
0039  #define OR1K_BIT(n)           (1 << (n))
0040
0041 /** @} */
0042
0043 /**
0044  * @name Internal OR1K UART Registers
0045  *
0046  * @{
0047  */
0048 #define OR1K_BSP_CLOCK_FREQ       50000000UL
0049 #define OR1K_BSP_UART_BASE        0x90000000
0050
0051 #define OR1K_BSP_UART_REG_TX              (OR1K_BSP_UART_BASE+0)
0052 #define OR1K_BSP_UART_REG_RX              (OR1K_BSP_UART_BASE+0)
0053 #define OR1K_BSP_UART_REG_DEV_LATCH_LOW   (OR1K_BSP_UART_BASE+0)
0054 #define OR1K_BSP_UART_REG_DEV_LATCH_HIGH  (OR1K_BSP_UART_BASE+1)
0055 #define OR1K_BSP_UART_REG_INT_ENABLE      (OR1K_BSP_UART_BASE+1)
0056 #define OR1K_BSP_UART_REG_INT_ID          (OR1K_BSP_UART_BASE+2)
0057 #define OR1K_BSP_UART_REG_FIFO_CTRL       (OR1K_BSP_UART_BASE+2)
0058 #define OR1K_BSP_UART_REG_LINE_CTRL       (OR1K_BSP_UART_BASE+3)
0059 #define OR1K_BSP_UART_REG_MODEM_CTRL      (OR1K_BSP_UART_BASE+4)
0060 #define OR1K_BSP_UART_REG_LINE_STATUS     (OR1K_BSP_UART_BASE+5)
0061 #define OR1K_BSP_UART_REG_MODEM_STATUS    (OR1K_BSP_UART_BASE+6)
0062 #define OR1K_BSP_UART_REG_SCRATCH         (OR1K_BSP_UART_BASE+7)
0063
0064 /* FIFO Control Register */
0065 #define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_1    (0x00)
0066 #define OR1K_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO  (0x01)
0067 #define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR   (0x02)
0068 #define OR1K_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT   (0x03)
0069 #define OR1K_BSP_UART_REG_FIFO_CTRL_DMA_SELECT   (0x08)
0070 #define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_4    (0x40)
0071 #define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_8    (0x80)
0072 #define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_14   (0xC0)
0073 #define OR1K_BSP_UART_REG_FIFO_CTRL_TRIGGER_MASK (0xC0)
0074
0075 /* Line Control Register */
0076 #define OR1K_BSP_UART_REG_LINE_CTRL_WLEN5  (0x00)
0077 #define OR1K_BSP_UART_REG_LINE_CTRL_WLEN6  (0x01)
0078 #define OR1K_BSP_UART_REG_LINE_CTRL_WLEN7  (0x02)
0079 #define OR1K_BSP_UART_REG_LINE_CTRL_WLEN8  (0x03)
0080 #define OR1K_BSP_UART_REG_LINE_CTRL_STOP   (0x04)
0081 #define OR1K_BSP_UART_REG_LINE_CTRL_PARITY (0x08)
0082 #define OR1K_BSP_UART_REG_LINE_CTRL_EPAR   (0x10)
0083 #define OR1K_BSP_UART_REG_LINE_CTRL_SPAR   (0x20)
0084 #define OR1K_BSP_UART_REG_LINE_CTRL_SBC    (0x40)
0085 #define OR1K_BSP_UART_REG_LINE_CTRL_DLAB   (0x80)
0086
0087 /* Line Status Register */
0088 #define OR1K_BSP_UART_REG_LINE_STATUS_DR   (0x01)
0089 #define OR1K_BSP_UART_REG_LINE_STATUS_OE   (0x02)
0090 #define OR1K_BSP_UART_REG_LINE_STATUS_PE   (0x04)
0091 #define OR1K_BSP_UART_REG_LINE_STATUS_FE   (0x08)
0092 #define OR1K_BSP_UART_REG_LINE_STATUS_BI   (0x10)
0093 #define OR1K_BSP_UART_REG_LINE_STATUS_THRE (0x20)
0094 #define OR1K_BSP_UART_REG_LINE_STATUS_TEMT (0x40)
0095
0096 /* Modem Control Register */
0097 #define OR1K_BSP_UART_REG_MODEM_CTRL_DTR  (0x01)
0098 #define OR1K_BSP_UART_REG_MODEM_CTRL_RTS  (0x02)
0099 #define OR1K_BSP_UART_REG_MODEM_CTRL_OUT1 (0x04)
0100 #define OR1K_BSP_UART_REG_MODEM_CTRL_OUT2 (0x08)
0101 #define OR1K_BSP_UART_REG_MODEM_CTRL_LOOP (0x10)
0102
0103 /* Modem Status Register */
0104 #define OR1K_BSP_UART_REG_MODEM_STATUS_DCTS (0x01)
0105 #define OR1K_BSP_UART_REG_MODEM_STATUS_DDSR (0x02)
0106 #define OR1K_BSP_UART_REG_MODEM_STATUS_TERI (0x04)
0107 #define OR1K_BSP_UART_REG_MODEM_STATUS_DDCD (0x08)
0108 #define OR1K_BSP_UART_REG_MODEM_STATUS_CTS  (0x10)
0109 #define OR1K_BSP_UART_REG_MODEM_STATUS_DSR  (0x20)
0110 #define OR1K_BSP_UART_REG_MODEM_STATUS_RI   (0x40)
0111 #define OR1K_BSP_UART_REG_MODEM_STATUS_DCD  (0x80)
0112 #define OR1K_BSP_UART_REG_MODEM_STATUS_ANY_DELTA (0x0F)
0113
0114 /** @} */
0115
0116 /** @} */
0117
0118 #endif /* LIBBSP_GENERIC_OR1K_H */