Warning, /bsps/nios2/nios2_iss/nios2_iss.ptf is written in an unsupported language. File is not indexed.
0001 SYSTEM Nios2_system
0002 {
0003 System_Wizard_Version = "4.10";
0004 System_Wizard_Build = "181";
0005 WIZARD_SCRIPT_ARGUMENTS
0006 {
0007 device_family = "STRATIX";
0008 clock_freq = "50000000";
0009 generate_hdl = "0";
0010 generate_sdk = "0";
0011 do_build_sim = "0";
0012 hdl_language = "vhdl";
0013 view_master_columns = "1";
0014 view_master_priorities = "0";
0015 board_class = "";
0016 name_column_width = "75";
0017 desc_column_width = "75";
0018 bustype_column_width = "0";
0019 base_column_width = "75";
0020 end_column_width = "75";
0021 view_frame_window = "170:208:1280:900";
0022 do_log_history = "0";
0023 device_family_id = "STRATIX";
0024 BOARD_INFO
0025 {
0026 device_is_engineering_sample = "";
0027 }
0028 }
0029 MODULE cpu_0
0030 {
0031 class = "altera_nios2";
0032 class_version = "1.0";
0033 iss_model_name = "altera_nios2";
0034 HDL_INFO
0035 {
0036 PLI_Files = "";
0037 Simulation_HDL_Files = "";
0038 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";
0039 Precompiled_Simulation_Library_Files = "";
0040 Synthesis_Only_Files = "";
0041 }
0042 MASTER instruction_master
0043 {
0044 PORT_WIRING
0045 {
0046 PORT i_address
0047 {
0048 direction = "output";
0049 type = "address";
0050 width = "28";
0051 }
0052 PORT i_read
0053 {
0054 direction = "output";
0055 type = "read";
0056 width = "1";
0057 }
0058 PORT i_readdata
0059 {
0060 direction = "input";
0061 type = "readdata";
0062 width = "32";
0063 }
0064 PORT i_readdatavalid
0065 {
0066 direction = "input";
0067 type = "readdatavalid";
0068 width = "1";
0069 }
0070 PORT i_waitrequest
0071 {
0072 direction = "input";
0073 type = "waitrequest";
0074 width = "1";
0075 }
0076 }
0077 SYSTEM_BUILDER_INFO
0078 {
0079 Bus_Type = "avalon";
0080 Data_Width = "32";
0081 Max_Address_Width = "32";
0082 Address_Width = "8";
0083 Is_Instruction_Master = "1";
0084 Has_IRQ = "0";
0085 Irq_Scheme = "individual_requests";
0086 Interrupt_Range = "0-0";
0087 Is_Enabled = "1";
0088 }
0089 }
0090 MASTER data_master
0091 {
0092 PORT_WIRING
0093 {
0094 PORT clk
0095 {
0096 direction = "input";
0097 type = "clk";
0098 width = "1";
0099 }
0100 PORT d_address
0101 {
0102 direction = "output";
0103 type = "address";
0104 width = "28";
0105 }
0106 PORT d_byteenable
0107 {
0108 direction = "output";
0109 type = "byteenable";
0110 width = "4";
0111 }
0112 PORT d_irq
0113 {
0114 direction = "input";
0115 type = "irq";
0116 width = "32";
0117 }
0118 PORT d_read
0119 {
0120 direction = "output";
0121 type = "read";
0122 width = "1";
0123 }
0124 PORT d_readdata
0125 {
0126 direction = "input";
0127 type = "readdata";
0128 width = "32";
0129 }
0130 PORT d_waitrequest
0131 {
0132 direction = "input";
0133 type = "waitrequest";
0134 width = "1";
0135 }
0136 PORT d_write
0137 {
0138 direction = "output";
0139 type = "write";
0140 width = "1";
0141 }
0142 PORT d_writedata
0143 {
0144 direction = "output";
0145 type = "writedata";
0146 width = "32";
0147 }
0148 PORT jtag_debug_module_debugaccess_to_roms
0149 {
0150 direction = "output";
0151 type = "debugaccess";
0152 width = "1";
0153 }
0154 }
0155 SYSTEM_BUILDER_INFO
0156 {
0157 Register_Incoming_Signals = "1";
0158 Bus_Type = "avalon";
0159 Data_Width = "32";
0160 Max_Address_Width = "32";
0161 Address_Width = "8";
0162 Is_Data_Master = "1";
0163 Has_IRQ = "1";
0164 Irq_Scheme = "individual_requests";
0165 Interrupt_Range = "0-31";
0166 Is_Enabled = "1";
0167 }
0168 }
0169 SLAVE oci_core
0170 {
0171 PORT_WIRING
0172 {
0173 PORT byteenable
0174 {
0175 direction = "input";
0176 type = "byteenable";
0177 width = "4";
0178 }
0179 PORT oci_core_address
0180 {
0181 direction = "input";
0182 type = "address";
0183 width = "9";
0184 }
0185 PORT oci_core_begintransfer
0186 {
0187 direction = "input";
0188 type = "begintransfer";
0189 width = "1";
0190 }
0191 PORT oci_core_clk
0192 {
0193 direction = "input";
0194 type = "clk";
0195 width = "1";
0196 }
0197 PORT oci_core_readdata
0198 {
0199 direction = "output";
0200 type = "readdata";
0201 width = "32";
0202 }
0203 PORT oci_core_reset
0204 {
0205 direction = "input";
0206 type = "reset";
0207 width = "1";
0208 }
0209 PORT oci_core_resetrequest
0210 {
0211 direction = "output";
0212 type = "resetrequest";
0213 width = "1";
0214 }
0215 PORT oci_core_select
0216 {
0217 direction = "input";
0218 type = "chipselect";
0219 width = "1";
0220 }
0221 PORT oci_core_write
0222 {
0223 direction = "input";
0224 type = "write";
0225 width = "1";
0226 }
0227 PORT oci_core_writedata
0228 {
0229 direction = "input";
0230 type = "writedata";
0231 width = "32";
0232 }
0233 PORT reset_n
0234 {
0235 direction = "input";
0236 type = "reset_n";
0237 width = "1";
0238 }
0239 }
0240 SYSTEM_BUILDER_INFO
0241 {
0242 Read_Wait_States = "1";
0243 Write_Wait_States = "1";
0244 Register_Incoming_Signals = "1";
0245 Bus_Type = "avalon";
0246 Data_Width = "32";
0247 Address_Width = "9";
0248 Accepts_Internal_Connections = "1";
0249 Requires_Internal_Connections = "instruction_master,data_master";
0250 Accepts_External_Connections = "0";
0251 Is_Enabled = "1";
0252 Address_Alignment = "dynamic";
0253 Base_Address = "0x08100000";
0254 Is_Memory_Device = "1";
0255 Is_Printable_Device = "1";
0256 Uses_Tri_State_Data_Bus = "0";
0257 Has_IRQ = "0";
0258 JTAG_Hub_Base_Id = "69702";
0259 JTAG_Hub_Instance_Id = "0";
0260 MASTERED_BY cpu_0/instruction_master
0261 {
0262 priority = "1";
0263 }
0264 MASTERED_BY cpu_0/data_master
0265 {
0266 priority = "1";
0267 }
0268 IRQ_MASTER cpu_0/data_master
0269 {
0270 IRQ_Number = "NC";
0271 }
0272 }
0273 }
0274 WIZARD_SCRIPT_ARGUMENTS
0275 {
0276 CPU_Architecture = "nios2";
0277 do_generate = "1";
0278 cpu_selection = "f";
0279 CPU_Implementation = "fast";
0280 cache_has_dcache = "1";
0281 cache_has_icache = "1";
0282 cache_dcache_size = "2048";
0283 cache_icache_size = "4096";
0284 include_debug = "0";
0285 include_trace = "0";
0286 include_oci = "1";
0287 debug_level = "2";
0288 oci_offchip_trace = "0";
0289 oci_onchip_trace = "0";
0290 oci_trace_addr_width = "7";
0291 oci_num_xbrk = "0";
0292 oci_num_dbrk = "0";
0293 oci_dbrk_trace = "0";
0294 oci_dbrk_pairs = "0";
0295 oci_debugreq_signals = "0";
0296 oci_instance_number = "1";
0297 hardware_multiply_present = "1";
0298 hardware_divide_present = "0";
0299 bht_ptr_sz = "8";
0300 reset_slave = "onchip_memory_0/s1";
0301 reset_offset = "0x00000000";
0302 exc_slave = "onchip_memory_0/s1";
0303 exc_offset = "0x00000600";
0304 break_slave = "cpu_0/jtag_debug_module";
0305 break_offset = "0x00000020";
0306 altera_internal_test = "0";
0307 full_waveform_signals = "0";
0308 activate_model_checker = "0";
0309 bit_31_bypass_dcache = "1";
0310 always_bypass_dcache = "0";
0311 always_unsigned_mul = "0";
0312 consistent_synthesis = "0";
0313 ibuf_ptr_sz = "4";
0314 jtb_ptr_sz = "5";
0315 performance_counters_present = "0";
0316 performance_counters_width = "32";
0317 ras_ptr_sz = "4";
0318 inst_decode_in_submodule = "0";
0319 register_dependency_in_submodule = "0";
0320 source_operands_in_submodule = "0";
0321 alu_in_submodule = "0";
0322 stdata_in_submodule = "0";
0323 shift_rot_2N_in_submodule = "0";
0324 control_regs_in_submodule = "0";
0325 mult_cell_in_submodule = "0";
0326 M_inst_result_mux_in_submodule = "0";
0327 dcache_load_aligner_in_submodule = "0";
0328 hardware_divide_in_submodule = "0";
0329 mult_result_mux_in_submodule = "0";
0330 shift_rotate_in_submodule = "0";
0331 register_file_write_data_mux_in_submodule = "0";
0332 avalon_imaster_in_submodule = "0";
0333 avalon_dmaster_in_submodule = "0";
0334 avalon_load_aligner_in_submodule = "0";
0335 hbreak_test = "0";
0336 iss_trace_on = "0";
0337 iss_trace_warning = "1";
0338 iss_trace_info = "1";
0339 iss_trace_disassembly = "0";
0340 iss_trace_registers = "0";
0341 iss_trace_instr_count = "0";
0342 iss_software_debug = "0";
0343 iss_software_debug_port = "9996";
0344 iss_memory_dump_start = "";
0345 iss_memory_dump_end = "";
0346 CONSTANTS
0347 {
0348 CONSTANT __nios_catch_irqs__
0349 {
0350 value = "1";
0351 comment = "Include panic handler for all irqs (needs uart)";
0352 }
0353 CONSTANT __nios_use_constructors__
0354 {
0355 value = "1";
0356 comment = "Call c++ static constructors";
0357 }
0358 CONSTANT __nios_use_small_printf__
0359 {
0360 value = "1";
0361 comment = "Smaller non-ANSI printf, with no floating point";
0362 }
0363 CONSTANT nasys_has_icache
0364 {
0365 value = "0";
0366 comment = "True if instruction cache present";
0367 }
0368 CONSTANT nasys_icache_size
0369 {
0370 value = "4096";
0371 comment = "Size in bytes of instruction cache";
0372 }
0373 CONSTANT nasys_icache_line_size
0374 {
0375 value = "32";
0376 comment = "Size in bytes of each icache line";
0377 }
0378 CONSTANT nasys_icache_line_size_log2
0379 {
0380 value = "5";
0381 comment = "Log2 size in bytes of each icache line";
0382 }
0383 CONSTANT nasys_has_dcache
0384 {
0385 value = "0";
0386 comment = "True if instruction cache present";
0387 }
0388 CONSTANT nasys_dcache_size
0389 {
0390 value = "2048";
0391 comment = "Size in bytes of data cache";
0392 }
0393 CONSTANT nasys_dcache_line_size
0394 {
0395 value = "4";
0396 comment = "Size in bytes of each dcache line";
0397 }
0398 CONSTANT nasys_dcache_line_size_log2
0399 {
0400 value = "2";
0401 comment = "Log2 size in bytes of each dcache line";
0402 }
0403 }
0404 mainmem_slave = "";
0405 datamem_slave = "";
0406 maincomm_slave = "";
0407 debugcomm_slave = "";
0408 germs_monitor_id = "";
0409 asp_debug = "0";
0410 asp_core_debug = "0";
0411 include_third_party_debug_port = "0";
0412 oci_data_trace = "0";
0413 oci_num_pm = "0";
0414 oci_pm_width = "40";
0415 oci_trigger_arming = "1";
0416 break_slave_override = "";
0417 break_offset_override = "0x20";
0418 legacy_sdk_support = "0";
0419 altera_show_unreleased_features = "0";
0420 illegal_instructions_trap = "0";
0421 remove_hardware_multiplier = "0";
0422 large_dcache_allow_mram = "0";
0423 cache_omit_dcache = "0";
0424 cache_omit_icache = "0";
0425 omit_instruction_master = "0";
0426 omit_data_master = "0";
0427 num_local_data_masters = "0";
0428 num_local_instruction_masters = "0";
0429 gui_branch_prediction_type = "Automatic";
0430 branch_prediction_type = "Dynamic";
0431 bht_index_pc_only = "0";
0432 mmu_present = "0";
0433 process_id_num_bits = "10";
0434 dtlb_ptr_sz = "7";
0435 dtlb_num_ways = "4";
0436 udtlb_num_entries = "6";
0437 itlb_ptr_sz = "7";
0438 itlb_num_ways = "4";
0439 uitlb_num_entries = "4";
0440 fast_tlb_miss_exc_slave = "onchip_memory_0/s1";
0441 fast_tlb_miss_exc_offset = "0x00000000";
0442 always_encrypt = "1";
0443 activate_monitors = "1";
0444 activate_test_end_checker = "0";
0445 activate_trace = "1";
0446 clear_x_bits_ld_non_bypass = "1";
0447 hdl_sim_caches_cleared = "1";
0448 allow_full_address_range = "0";
0449 Boot_Copier = "boot_loader_cfi.srec";
0450 Boot_Copier_EPCS = "boot_loader_epcs.srec";
0451 license_status = "ocp";
0452 }
0453 SYSTEM_BUILDER_INFO
0454 {
0455 Parameters_Signature = "";
0456 Is_CPU = "1";
0457 Is_Enabled = "1";
0458 Instantiate_In_System_Module = "1";
0459 Default_Module_Name = "cpu";
0460 View
0461 {
0462 MESSAGES
0463 {
0464 }
0465 Is_Collapsed = "0";
0466 Settings_Summary = "Nios II/f
0467 <br> 4-Kbyte Instruction Cache
0468 <br> 2-Kbyte Data Cache
0469 <br> JTAG Debug Module
0470 ";
0471 }
0472 Required_Device_Family = "STRATIX,STRATIXII,CYCLONE";
0473 }
0474 SOFTWARE_COMPONENT altera_hal
0475 {
0476 class = "altera_hal";
0477 class_version = "1.0";
0478 WIZARD_SCRIPT_ARGUMENTS
0479 {
0480 }
0481 SYSTEM_BUILDER_INFO
0482 {
0483 Is_Enabled = "1";
0484 }
0485 }
0486 SOFTWARE_COMPONENT altera_nios2_test
0487 {
0488 class = "altera_nios2_test";
0489 class_version = "2.0";
0490 WIZARD_SCRIPT_ARGUMENTS
0491 {
0492 CONSTANTS
0493 {
0494 CONSTANT debug_on
0495 {
0496 value = "0";
0497 comment = "Enable debug features";
0498 }
0499 }
0500 }
0501 SYSTEM_BUILDER_INFO
0502 {
0503 Is_Enabled = "0";
0504 }
0505 }
0506 SOFTWARE_COMPONENT altera_plugs_library
0507 {
0508 class = "altera_plugs_library";
0509 class_version = "2.1";
0510 WIZARD_SCRIPT_ARGUMENTS
0511 {
0512 CONSTANTS
0513 {
0514 CONSTANT PLUGS_PLUG_COUNT
0515 {
0516 value = "5";
0517 comment = "Maximum number of plugs";
0518 }
0519 CONSTANT PLUGS_ADAPTER_COUNT
0520 {
0521 value = "2";
0522 comment = "Maximum number of adapters";
0523 }
0524 CONSTANT PLUGS_DNS
0525 {
0526 value = "1";
0527 comment = "Have routines for DNS lookups";
0528 }
0529 CONSTANT PLUGS_PING
0530 {
0531 value = "1";
0532 comment = "Respond to icmp echo (ping) messages";
0533 }
0534 CONSTANT PLUGS_TCP
0535 {
0536 value = "1";
0537 comment = "Support tcp in/out connections";
0538 }
0539 CONSTANT PLUGS_IRQ
0540 {
0541 value = "1";
0542 comment = "Run at interrupte level";
0543 }
0544 CONSTANT PLUGS_DEBUG
0545 {
0546 value = "1";
0547 comment = "Support debug routines";
0548 }
0549 }
0550 }
0551 SYSTEM_BUILDER_INFO
0552 {
0553 Is_Enabled = "1";
0554 }
0555 }
0556 PORT_WIRING
0557 {
0558 }
0559 SIMULATION
0560 {
0561 DISPLAY
0562 {
0563 SIGNAL aaa
0564 {
0565 format = "Logic";
0566 name = "i_readdata";
0567 radix = "hexadecimal";
0568 }
0569 SIGNAL aab
0570 {
0571 format = "Logic";
0572 name = "i_readdatavalid";
0573 radix = "hexadecimal";
0574 }
0575 SIGNAL aac
0576 {
0577 format = "Logic";
0578 name = "i_waitrequest";
0579 radix = "hexadecimal";
0580 }
0581 SIGNAL aad
0582 {
0583 format = "Logic";
0584 name = "i_address";
0585 radix = "hexadecimal";
0586 }
0587 SIGNAL aae
0588 {
0589 format = "Logic";
0590 name = "i_read";
0591 radix = "hexadecimal";
0592 }
0593 SIGNAL aaf
0594 {
0595 format = "Logic";
0596 name = "clk";
0597 radix = "hexadecimal";
0598 }
0599 SIGNAL aag
0600 {
0601 format = "Logic";
0602 name = "reset_n";
0603 radix = "hexadecimal";
0604 }
0605 SIGNAL aah
0606 {
0607 format = "Logic";
0608 name = "d_readdata";
0609 radix = "hexadecimal";
0610 }
0611 SIGNAL aai
0612 {
0613 format = "Logic";
0614 name = "d_waitrequest";
0615 radix = "hexadecimal";
0616 }
0617 SIGNAL aaj
0618 {
0619 format = "Logic";
0620 name = "d_irq";
0621 radix = "hexadecimal";
0622 }
0623 SIGNAL aak
0624 {
0625 format = "Logic";
0626 name = "d_address";
0627 radix = "hexadecimal";
0628 }
0629 SIGNAL aal
0630 {
0631 format = "Logic";
0632 name = "d_byteenable";
0633 radix = "hexadecimal";
0634 }
0635 SIGNAL aam
0636 {
0637 format = "Logic";
0638 name = "d_read";
0639 radix = "hexadecimal";
0640 }
0641 SIGNAL aan
0642 {
0643 format = "Logic";
0644 name = "d_write";
0645 radix = "hexadecimal";
0646 }
0647 SIGNAL aao
0648 {
0649 format = "Logic";
0650 name = "d_writedata";
0651 radix = "hexadecimal";
0652 }
0653 SIGNAL aap
0654 {
0655 format = "Divider";
0656 name = "base pipeline";
0657 radix = "";
0658 }
0659 SIGNAL aaq
0660 {
0661 format = "Logic";
0662 name = "clk";
0663 radix = "hexadecimal";
0664 }
0665 SIGNAL aar
0666 {
0667 format = "Logic";
0668 name = "reset_n";
0669 radix = "hexadecimal";
0670 }
0671 SIGNAL aas
0672 {
0673 format = "Logic";
0674 name = "D_stall";
0675 radix = "hexadecimal";
0676 }
0677 SIGNAL aat
0678 {
0679 format = "Logic";
0680 name = "A_stall";
0681 radix = "hexadecimal";
0682 }
0683 SIGNAL aau
0684 {
0685 format = "Logic";
0686 name = "F_pcb_nxt";
0687 radix = "hexadecimal";
0688 }
0689 SIGNAL aav
0690 {
0691 format = "Logic";
0692 name = "F_pcb";
0693 radix = "hexadecimal";
0694 }
0695 SIGNAL aaw
0696 {
0697 format = "Logic";
0698 name = "D_pcb";
0699 radix = "hexadecimal";
0700 }
0701 SIGNAL aax
0702 {
0703 format = "Logic";
0704 name = "E_pcb";
0705 radix = "hexadecimal";
0706 }
0707 SIGNAL aay
0708 {
0709 format = "Logic";
0710 name = "M_pcb";
0711 radix = "hexadecimal";
0712 }
0713 SIGNAL aaz
0714 {
0715 format = "Logic";
0716 name = "A_pcb";
0717 radix = "hexadecimal";
0718 }
0719 SIGNAL aba
0720 {
0721 format = "Logic";
0722 name = "W_pcb";
0723 radix = "hexadecimal";
0724 }
0725 SIGNAL abb
0726 {
0727 format = "Logic";
0728 name = "F_vinst";
0729 radix = "ascii";
0730 }
0731 SIGNAL abc
0732 {
0733 format = "Logic";
0734 name = "D_vinst";
0735 radix = "ascii";
0736 }
0737 SIGNAL abd
0738 {
0739 format = "Logic";
0740 name = "E_vinst";
0741 radix = "ascii";
0742 }
0743 SIGNAL abe
0744 {
0745 format = "Logic";
0746 name = "M_vinst";
0747 radix = "ascii";
0748 }
0749 SIGNAL abf
0750 {
0751 format = "Logic";
0752 name = "A_vinst";
0753 radix = "ascii";
0754 }
0755 SIGNAL abg
0756 {
0757 format = "Logic";
0758 name = "W_vinst";
0759 radix = "ascii";
0760 }
0761 SIGNAL abh
0762 {
0763 format = "Logic";
0764 name = "F_inst_ram_hit";
0765 radix = "hexadecimal";
0766 }
0767 SIGNAL abi
0768 {
0769 format = "Logic";
0770 name = "F_issue";
0771 radix = "hexadecimal";
0772 }
0773 SIGNAL abj
0774 {
0775 format = "Logic";
0776 name = "F_kill";
0777 radix = "hexadecimal";
0778 }
0779 SIGNAL abk
0780 {
0781 format = "Logic";
0782 name = "D_kill";
0783 radix = "hexadecimal";
0784 }
0785 SIGNAL abl
0786 {
0787 format = "Logic";
0788 name = "D_refetch";
0789 radix = "hexadecimal";
0790 }
0791 SIGNAL abm
0792 {
0793 format = "Logic";
0794 name = "D_issue";
0795 radix = "hexadecimal";
0796 }
0797 SIGNAL abn
0798 {
0799 format = "Logic";
0800 name = "D_valid";
0801 radix = "hexadecimal";
0802 }
0803 SIGNAL abo
0804 {
0805 format = "Logic";
0806 name = "E_valid";
0807 radix = "hexadecimal";
0808 }
0809 SIGNAL abp
0810 {
0811 format = "Logic";
0812 name = "M_valid";
0813 radix = "hexadecimal";
0814 }
0815 SIGNAL abq
0816 {
0817 format = "Logic";
0818 name = "A_valid";
0819 radix = "hexadecimal";
0820 }
0821 SIGNAL abr
0822 {
0823 format = "Logic";
0824 name = "W_valid";
0825 radix = "hexadecimal";
0826 }
0827 SIGNAL abs
0828 {
0829 format = "Logic";
0830 name = "W_wr_dst_reg";
0831 radix = "hexadecimal";
0832 }
0833 SIGNAL abt
0834 {
0835 format = "Logic";
0836 name = "W_dst_regnum";
0837 radix = "hexadecimal";
0838 }
0839 SIGNAL abu
0840 {
0841 format = "Logic";
0842 name = "W_wr_data";
0843 radix = "hexadecimal";
0844 }
0845 SIGNAL abv
0846 {
0847 format = "Logic";
0848 name = "D_en";
0849 radix = "hexadecimal";
0850 }
0851 SIGNAL abw
0852 {
0853 format = "Logic";
0854 name = "E_en";
0855 radix = "hexadecimal";
0856 }
0857 SIGNAL abx
0858 {
0859 format = "Logic";
0860 name = "M_en";
0861 radix = "hexadecimal";
0862 }
0863 SIGNAL aby
0864 {
0865 format = "Logic";
0866 name = "A_en";
0867 radix = "hexadecimal";
0868 }
0869 SIGNAL abz
0870 {
0871 format = "Logic";
0872 name = "F_iw";
0873 radix = "hexadecimal";
0874 }
0875 SIGNAL aca
0876 {
0877 format = "Logic";
0878 name = "D_iw";
0879 radix = "hexadecimal";
0880 }
0881 SIGNAL acb
0882 {
0883 format = "Logic";
0884 name = "E_iw";
0885 radix = "hexadecimal";
0886 }
0887 SIGNAL acc
0888 {
0889 format = "Logic";
0890 name = "E_cancel";
0891 radix = "hexadecimal";
0892 }
0893 SIGNAL acd
0894 {
0895 format = "Logic";
0896 name = "E_pipe_flush";
0897 radix = "hexadecimal";
0898 }
0899 SIGNAL ace
0900 {
0901 format = "Logic";
0902 name = "E_pipe_flush_baddr";
0903 radix = "hexadecimal";
0904 }
0905 SIGNAL acf
0906 {
0907 format = "Logic";
0908 name = "A_status_reg_pie";
0909 radix = "hexadecimal";
0910 }
0911 SIGNAL acg
0912 {
0913 format = "Logic";
0914 name = "A_ienable_reg";
0915 radix = "hexadecimal";
0916 }
0917 SIGNAL ach
0918 {
0919 format = "Logic";
0920 name = "intr_req";
0921 radix = "hexadecimal";
0922 }
0923 }
0924 }
0925 MASTER data_master2
0926 {
0927 PORT_WIRING
0928 {
0929 }
0930 SYSTEM_BUILDER_INFO
0931 {
0932 Register_Incoming_Signals = "1";
0933 Bus_Type = "avalon";
0934 Data_Width = "32";
0935 Max_Address_Width = "31";
0936 Address_Width = "8";
0937 Is_Data_Master = "1";
0938 Has_IRQ = "0";
0939 Is_Enabled = "0";
0940 }
0941 }
0942 MASTER local_data_master_0
0943 {
0944 PORT_WIRING
0945 {
0946 }
0947 SYSTEM_BUILDER_INFO
0948 {
0949 Register_Incoming_Signals = "0";
0950 Bus_Type = "avalon";
0951 Data_Width = "32";
0952 Max_Address_Width = "31";
0953 Address_Width = "8";
0954 Is_Data_Master = "1";
0955 Has_IRQ = "0";
0956 Is_Enabled = "0";
0957 }
0958 }
0959 MASTER local_data_master_1
0960 {
0961 PORT_WIRING
0962 {
0963 }
0964 SYSTEM_BUILDER_INFO
0965 {
0966 Register_Incoming_Signals = "0";
0967 Bus_Type = "avalon";
0968 Data_Width = "32";
0969 Max_Address_Width = "31";
0970 Address_Width = "8";
0971 Is_Data_Master = "1";
0972 Has_IRQ = "0";
0973 Is_Enabled = "0";
0974 }
0975 }
0976 MASTER local_data_master_2
0977 {
0978 PORT_WIRING
0979 {
0980 }
0981 SYSTEM_BUILDER_INFO
0982 {
0983 Register_Incoming_Signals = "0";
0984 Bus_Type = "avalon";
0985 Data_Width = "32";
0986 Max_Address_Width = "31";
0987 Address_Width = "8";
0988 Is_Data_Master = "1";
0989 Has_IRQ = "0";
0990 Is_Enabled = "0";
0991 }
0992 }
0993 MASTER local_data_master_3
0994 {
0995 PORT_WIRING
0996 {
0997 }
0998 SYSTEM_BUILDER_INFO
0999 {
1000 Register_Incoming_Signals = "0";
1001 Bus_Type = "avalon";
1002 Data_Width = "32";
1003 Max_Address_Width = "31";
1004 Address_Width = "8";
1005 Is_Data_Master = "1";
1006 Has_IRQ = "0";
1007 Is_Enabled = "0";
1008 }
1009 }
1010 MASTER local_instruction_master_0
1011 {
1012 PORT_WIRING
1013 {
1014 }
1015 SYSTEM_BUILDER_INFO
1016 {
1017 Register_Incoming_Signals = "0";
1018 Bus_Type = "avalon";
1019 Data_Width = "32";
1020 Max_Address_Width = "31";
1021 Address_Width = "8";
1022 Is_Instruction_Master = "1";
1023 Has_IRQ = "0";
1024 Is_Enabled = "0";
1025 }
1026 }
1027 MASTER custom_instruction_master
1028 {
1029 PORT_WIRING
1030 {
1031 }
1032 SYSTEM_BUILDER_INFO
1033 {
1034 Bus_Type = "nios_custom_instruction";
1035 Data_Width = "32";
1036 Address_Width = "8";
1037 Max_Address_Width = "8";
1038 Base_Address = "N/A";
1039 Is_Visible = "0";
1040 Is_Custom_Instruction = "0";
1041 Is_Enabled = "0";
1042 }
1043 }
1044 SLAVE jtag_debug_module
1045 {
1046 PORT_WIRING
1047 {
1048 PORT jtag_debug_module_address
1049 {
1050 direction = "input";
1051 type = "address";
1052 width = "9";
1053 }
1054 PORT jtag_debug_module_begintransfer
1055 {
1056 direction = "input";
1057 type = "begintransfer";
1058 width = "1";
1059 }
1060 PORT jtag_debug_module_byteenable
1061 {
1062 direction = "input";
1063 type = "byteenable";
1064 width = "4";
1065 }
1066 PORT jtag_debug_module_clk
1067 {
1068 direction = "input";
1069 type = "clk";
1070 width = "1";
1071 }
1072 PORT jtag_debug_module_debugaccess
1073 {
1074 direction = "input";
1075 type = "debugaccess";
1076 width = "1";
1077 }
1078 PORT jtag_debug_module_readdata
1079 {
1080 direction = "output";
1081 type = "readdata";
1082 width = "32";
1083 }
1084 PORT jtag_debug_module_reset
1085 {
1086 direction = "input";
1087 type = "reset";
1088 width = "1";
1089 }
1090 PORT jtag_debug_module_resetrequest
1091 {
1092 direction = "output";
1093 type = "resetrequest";
1094 width = "1";
1095 }
1096 PORT jtag_debug_module_select
1097 {
1098 direction = "input";
1099 type = "chipselect";
1100 width = "1";
1101 }
1102 PORT jtag_debug_module_write
1103 {
1104 direction = "input";
1105 type = "write";
1106 width = "1";
1107 }
1108 PORT jtag_debug_module_writedata
1109 {
1110 direction = "input";
1111 type = "writedata";
1112 width = "32";
1113 }
1114 PORT reset_n
1115 {
1116 direction = "input";
1117 type = "reset_n";
1118 width = "1";
1119 }
1120 }
1121 SYSTEM_BUILDER_INFO
1122 {
1123 Read_Wait_States = "1";
1124 Write_Wait_States = "1";
1125 Register_Incoming_Signals = "1";
1126 Bus_Type = "avalon";
1127 Data_Width = "32";
1128 Address_Width = "9";
1129 Accepts_Internal_Connections = "1";
1130 Requires_Internal_Connections = "instruction_master,data_master";
1131 Accepts_External_Connections = "0";
1132 Is_Enabled = "1";
1133 Address_Alignment = "dynamic";
1134 Base_Address = "0x08200800";
1135 Is_Memory_Device = "1";
1136 Is_Printable_Device = "0";
1137 Uses_Tri_State_Data_Bus = "0";
1138 Has_IRQ = "0";
1139 JTAG_Hub_Base_Id = "593990";
1140 JTAG_Hub_Instance_Id = "0";
1141 MASTERED_BY cpu_0/instruction_master
1142 {
1143 priority = "1";
1144 }
1145 MASTERED_BY cpu_0/data_master
1146 {
1147 priority = "1";
1148 }
1149 IRQ_MASTER cpu_0/data_master
1150 {
1151 IRQ_Number = "NC";
1152 }
1153 }
1154 }
1155 }
1156 MODULE onchip_memory_0
1157 {
1158 class = "altera_avalon_onchip_memory2";
1159 class_version = "4.0";
1160 iss_model_name = "altera_memory";
1161 HDL_INFO
1162 {
1163 Precompiled_Simulation_Library_Files = "";
1164 Simulation_HDL_Files = "";
1165 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory_1.vhd";
1166 Synthesis_Only_Files = "";
1167 }
1168 WIZARD_SCRIPT_ARGUMENTS
1169 {
1170 allow_mram_sim_contents_only_file = "0";
1171 ram_block_type = "M-RAM";
1172 gui_ram_block_type = "Automatic";
1173 Writeable = "1";
1174 dual_port = "0";
1175 Size_Value = "8192";
1176 Size_Multiple = "1024";
1177 MAKE
1178 {
1179 TARGET delete_placeholder_warning
1180 {
1181 onchip_memory_1
1182 {
1183 Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
1184 Is_Phony = "1";
1185 Target_File = "do_delete_placeholder_warning";
1186 }
1187 }
1188 TARGET hex
1189 {
1190 onchip_memory_1
1191 {
1192 Command1 = "@echo Post-processing to create $(notdir $@)";
1193 Command2 = "elf2hex $(ELF) 0x00000000 0x7FF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex --create-lanes=0";
1194 Dependency = "$(ELF)";
1195 Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory_1.hex";
1196 }
1197 }
1198 TARGET sim
1199 {
1200 onchip_memory_1
1201 {
1202 Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
1203 Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \(Note: This does not affect the instruction set simulator.\)";
1204 Command3 = "touch $(SIMDIR)/dummy_file";
1205 Dependency = "$(ELF)";
1206 Target_File = "$(SIMDIR)/dummy_file";
1207 }
1208 }
1209 }
1210 contents_info = "QUARTUS_PROJECT_DIR/onchip_memory_1.hex 1092402177 ";
1211 }
1212 SYSTEM_BUILDER_INFO
1213 {
1214 Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM";
1215 Instantiate_In_System_Module = "1";
1216 Is_Enabled = "1";
1217 Default_Module_Name = "onchip_memory";
1218 View
1219 {
1220 MESSAGES
1221 {
1222 }
1223 Is_Collapsed = "1";
1224 }
1225 }
1226 SLAVE s1
1227 {
1228 PORT_WIRING
1229 {
1230 PORT address
1231 {
1232 direction = "input";
1233 type = "address";
1234 width = "9";
1235 }
1236 PORT byteenable
1237 {
1238 direction = "input";
1239 type = "byteenable";
1240 width = "4";
1241 }
1242 PORT chipselect
1243 {
1244 direction = "input";
1245 type = "chipselect";
1246 width = "1";
1247 }
1248 PORT clk
1249 {
1250 direction = "input";
1251 type = "clk";
1252 width = "1";
1253 }
1254 PORT readdata
1255 {
1256 direction = "output";
1257 type = "readdata";
1258 width = "32";
1259 }
1260 PORT write
1261 {
1262 direction = "input";
1263 type = "write";
1264 width = "1";
1265 }
1266 PORT writedata
1267 {
1268 direction = "input";
1269 type = "writedata";
1270 width = "32";
1271 }
1272 }
1273 SYSTEM_BUILDER_INFO
1274 {
1275 Bus_Type = "avalon";
1276 Is_Memory_Device = "1";
1277 Address_Alignment = "dynamic";
1278 Address_Width = "21";
1279 Data_Width = "32";
1280 Has_IRQ = "0";
1281 Read_Wait_States = "0";
1282 Write_Wait_States = "0";
1283 Address_Span = "134217728";
1284 Read_Latency = "1";
1285 MASTERED_BY cpu_0/instruction_master
1286 {
1287 priority = "1";
1288 }
1289 MASTERED_BY cpu_0/data_master
1290 {
1291 priority = "1";
1292 }
1293 Base_Address = "0x00000000";
1294 IRQ_MASTER cpu_0/data_master
1295 {
1296 IRQ_Number = "NC";
1297 }
1298 }
1299 }
1300 SLAVE s2
1301 {
1302 PORT_WIRING
1303 {
1304 }
1305 SYSTEM_BUILDER_INFO
1306 {
1307 Bus_Type = "avalon";
1308 Is_Memory_Device = "1";
1309 Address_Alignment = "dynamic";
1310 Address_Width = "21";
1311 Data_Width = "32";
1312 Has_IRQ = "0";
1313 Read_Wait_States = "0";
1314 Write_Wait_States = "0";
1315 Address_Span = "8388608";
1316 Read_Latency = "1";
1317 Is_Enabled = "0";
1318 }
1319 }
1320 SIMULATION
1321 {
1322 DISPLAY
1323 {
1324 SIGNAL a
1325 {
1326 name = "chipselect";
1327 conditional = "1";
1328 }
1329 SIGNAL b
1330 {
1331 name = "write";
1332 conditional = "1";
1333 }
1334 SIGNAL c
1335 {
1336 name = "address";
1337 radix = "hexadecimal";
1338 }
1339 SIGNAL d
1340 {
1341 name = "byteenable";
1342 radix = "binary";
1343 conditional = "1";
1344 }
1345 SIGNAL e
1346 {
1347 name = "readdata";
1348 radix = "hexadecimal";
1349 }
1350 SIGNAL f
1351 {
1352 name = "writedata";
1353 radix = "hexadecimal";
1354 conditional = "1";
1355 }
1356 }
1357 }
1358 PORT_WIRING
1359 {
1360 }
1361 }
1362 MODULE jtag_uart_0
1363 {
1364 class = "altera_avalon_jtag_uart";
1365 class_version = "1.0";
1366 iss_model_name = "altera_avalon_jtag_uart";
1367 SLAVE avalon_jtag_slave
1368 {
1369 SYSTEM_BUILDER_INFO
1370 {
1371 Bus_Type = "avalon";
1372 Is_Printable_Device = "1";
1373 Address_Alignment = "native";
1374 Address_Width = "1";
1375 Data_Width = "32";
1376 Has_IRQ = "1";
1377 Read_Wait_States = "peripheral_controlled";
1378 Write_Wait_States = "peripheral_controlled";
1379 JTAG_Hub_Base_Id = "0x04006E";
1380 JTAG_Hub_Instance_Id = "0";
1381 MASTERED_BY cpu_0/data_master
1382 {
1383 priority = "1";
1384 }
1385 IRQ_MASTER cpu_0/data_master
1386 {
1387 IRQ_Number = "2";
1388 }
1389 Base_Address = "0x08000000";
1390 }
1391 PORT_WIRING
1392 {
1393 PORT clk
1394 {
1395 type = "clk";
1396 direction = "input";
1397 width = "1";
1398 }
1399 PORT rst_n
1400 {
1401 type = "reset_n";
1402 direction = "input";
1403 width = "1";
1404 }
1405 PORT av_chipselect
1406 {
1407 type = "chipselect";
1408 direction = "input";
1409 width = "1";
1410 }
1411 PORT av_address
1412 {
1413 type = "address";
1414 direction = "input";
1415 width = "1";
1416 }
1417 PORT av_read_n
1418 {
1419 type = "read_n";
1420 direction = "input";
1421 width = "1";
1422 }
1423 PORT av_readdata
1424 {
1425 type = "readdata";
1426 direction = "output";
1427 width = "32";
1428 }
1429 PORT av_write_n
1430 {
1431 type = "write_n";
1432 direction = "input";
1433 width = "1";
1434 }
1435 PORT av_writedata
1436 {
1437 type = "writedata";
1438 direction = "input";
1439 width = "32";
1440 }
1441 PORT av_waitrequest
1442 {
1443 type = "waitrequest";
1444 direction = "output";
1445 width = "1";
1446 }
1447 PORT av_irq
1448 {
1449 type = "irq";
1450 direction = "output";
1451 width = "1";
1452 }
1453 PORT dataavailable
1454 {
1455 direction = "output";
1456 type = "dataavailable";
1457 width = "1";
1458 }
1459 PORT readyfordata
1460 {
1461 direction = "output";
1462 type = "readyfordata";
1463 width = "1";
1464 }
1465 }
1466 }
1467 SYSTEM_BUILDER_INFO
1468 {
1469 Instantiate_In_System_Module = "1";
1470 Is_Enabled = "1";
1471 Iss_Launch_Telnet = "0";
1472 View
1473 {
1474 Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
1475 <br>Read Depth: 64; Read IRQ Threshold: 8";
1476 MESSAGES
1477 {
1478 }
1479 Is_Collapsed = "1";
1480 }
1481 }
1482 WIZARD_SCRIPT_ARGUMENTS
1483 {
1484 write_depth = "64";
1485 read_depth = "64";
1486 write_threshold = "8";
1487 read_threshold = "8";
1488 read_char_stream = "";
1489 showascii = "1";
1490 read_le = "0";
1491 write_le = "0";
1492 }
1493 SIMULATION
1494 {
1495 Fix_Me_Up = "";
1496 DISPLAY
1497 {
1498 SIGNAL av_chipselect
1499 {
1500 name = "av_chipselect";
1501 }
1502 SIGNAL av_address
1503 {
1504 name = "av_address";
1505 radix = "hexadecimal";
1506 }
1507 SIGNAL av_read_n
1508 {
1509 name = "av_read_n";
1510 }
1511 SIGNAL av_readdata
1512 {
1513 name = "av_readdata";
1514 radix = "hexadecimal";
1515 }
1516 SIGNAL av_write_n
1517 {
1518 name = "av_write_n";
1519 }
1520 SIGNAL av_writedata
1521 {
1522 name = "av_writedata";
1523 radix = "hexadecimal";
1524 }
1525 SIGNAL av_waitrequest
1526 {
1527 name = "av_waitrequest";
1528 }
1529 SIGNAL av_irq
1530 {
1531 name = "av_irq";
1532 }
1533 SIGNAL dataavailable
1534 {
1535 name = "dataavailable";
1536 }
1537 SIGNAL readyfordata
1538 {
1539 name = "readyfordata";
1540 }
1541 }
1542 INTERACTIVE_IN drive
1543 {
1544 enable = "0";
1545 file = "_input_data_stream.dat";
1546 mutex = "_input_data_mutex.dat";
1547 log = "_in.log";
1548 rate = "100";
1549 signals = "temp,list";
1550 exe = "nios2-terminal";
1551 }
1552 INTERACTIVE_OUT log
1553 {
1554 enable = "1";
1555 exe = "perl -- atail-f.pl";
1556 file = "_output_stream.dat";
1557 radix = "ascii";
1558 signals = "temp,list";
1559 }
1560 }
1561 HDL_INFO
1562 {
1563 Precompiled_Simulation_Library_Files = "";
1564 Simulation_HDL_Files = "";
1565 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";
1566 Synthesis_Only_Files = "";
1567 }
1568 PORT_WIRING
1569 {
1570 }
1571 }
1572 MODULE timer_0
1573 {
1574 class = "altera_avalon_timer";
1575 class_version = "2.1";
1576 iss_model_name = "altera_avalon_timer";
1577 SLAVE s1
1578 {
1579 SYSTEM_BUILDER_INFO
1580 {
1581 Bus_Type = "avalon";
1582 Is_Printable_Device = "0";
1583 Address_Alignment = "native";
1584 Address_Width = "3";
1585 Data_Width = "16";
1586 Has_IRQ = "1";
1587 Read_Wait_States = "1";
1588 Write_Wait_States = "0";
1589 MASTERED_BY cpu_0/data_master
1590 {
1591 priority = "1";
1592 }
1593 IRQ_MASTER cpu_0/data_master
1594 {
1595 IRQ_Number = "1";
1596 }
1597 Base_Address = "0x08001000";
1598 }
1599 PORT_WIRING
1600 {
1601 PORT address
1602 {
1603 direction = "input";
1604 type = "address";
1605 width = "3";
1606 }
1607 PORT chipselect
1608 {
1609 direction = "input";
1610 type = "chipselect";
1611 width = "1";
1612 }
1613 PORT clk
1614 {
1615 direction = "input";
1616 type = "clk";
1617 width = "1";
1618 }
1619 PORT irq
1620 {
1621 direction = "output";
1622 type = "irq";
1623 width = "1";
1624 }
1625 PORT readdata
1626 {
1627 direction = "output";
1628 type = "readdata";
1629 width = "16";
1630 }
1631 PORT reset_n
1632 {
1633 direction = "input";
1634 type = "reset_n";
1635 width = "1";
1636 }
1637 PORT write_n
1638 {
1639 direction = "input";
1640 type = "write_n";
1641 width = "1";
1642 }
1643 PORT writedata
1644 {
1645 direction = "input";
1646 type = "writedata";
1647 width = "16";
1648 }
1649 }
1650 }
1651 SYSTEM_BUILDER_INFO
1652 {
1653 Instantiate_In_System_Module = "1";
1654 Is_Enabled = "1";
1655 View
1656 {
1657 Settings_Summary = "Timer with 1 ms timeout period.";
1658 MESSAGES
1659 {
1660 }
1661 Is_Collapsed = "1";
1662 }
1663 }
1664 WIZARD_SCRIPT_ARGUMENTS
1665 {
1666 always_run = "0";
1667 fixed_period = "0";
1668 snapshot = "1";
1669 period = "1";
1670 period_units = "ms";
1671 reset_output = "0";
1672 timeout_pulse_output = "0";
1673 mult = "0.001";
1674 }
1675 HDL_INFO
1676 {
1677 Simulation_HDL_Files = "";
1678 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.vhd";
1679 Precompiled_Simulation_Library_Files = "";
1680 Synthesis_Only_Files = "";
1681 }
1682 PORT_WIRING
1683 {
1684 }
1685 }
1686 MODULE timer_1
1687 {
1688 class = "altera_avalon_timer";
1689 class_version = "2.1";
1690 iss_model_name = "altera_avalon_timer";
1691 SLAVE s1
1692 {
1693 SYSTEM_BUILDER_INFO
1694 {
1695 Bus_Type = "avalon";
1696 Is_Printable_Device = "0";
1697 Address_Alignment = "native";
1698 Address_Width = "3";
1699 Data_Width = "16";
1700 Has_IRQ = "1";
1701 Read_Wait_States = "1";
1702 Write_Wait_States = "0";
1703 MASTERED_BY cpu_0/data_master
1704 {
1705 priority = "1";
1706 }
1707 IRQ_MASTER cpu_0/data_master
1708 {
1709 IRQ_Number = "3";
1710 }
1711 Base_Address = "0x08002000";
1712 }
1713 PORT_WIRING
1714 {
1715 PORT address
1716 {
1717 direction = "input";
1718 type = "address";
1719 width = "3";
1720 }
1721 PORT chipselect
1722 {
1723 direction = "input";
1724 type = "chipselect";
1725 width = "1";
1726 }
1727 PORT clk
1728 {
1729 direction = "input";
1730 type = "clk";
1731 width = "1";
1732 }
1733 PORT irq
1734 {
1735 direction = "output";
1736 type = "irq";
1737 width = "1";
1738 }
1739 PORT readdata
1740 {
1741 direction = "output";
1742 type = "readdata";
1743 width = "16";
1744 }
1745 PORT reset_n
1746 {
1747 direction = "input";
1748 type = "reset_n";
1749 width = "1";
1750 }
1751 PORT write_n
1752 {
1753 direction = "input";
1754 type = "write_n";
1755 width = "1";
1756 }
1757 PORT writedata
1758 {
1759 direction = "input";
1760 type = "writedata";
1761 width = "16";
1762 }
1763 }
1764 }
1765 SYSTEM_BUILDER_INFO
1766 {
1767 Instantiate_In_System_Module = "1";
1768 Is_Enabled = "1";
1769 View
1770 {
1771 Settings_Summary = "Timer with 1 ms timeout period.";
1772 MESSAGES
1773 {
1774 }
1775 Is_Collapsed = "1";
1776 }
1777 }
1778 WIZARD_SCRIPT_ARGUMENTS
1779 {
1780 always_run = "0";
1781 fixed_period = "0";
1782 snapshot = "1";
1783 period = "1";
1784 period_units = "ms";
1785 reset_output = "0";
1786 timeout_pulse_output = "0";
1787 mult = "0.001";
1788 }
1789 HDL_INFO
1790 {
1791 Simulation_HDL_Files = "";
1792 Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_1.vhd";
1793 Precompiled_Simulation_Library_Files = "";
1794 Synthesis_Only_Files = "";
1795 }
1796 PORT_WIRING
1797 {
1798 }
1799 }
1800 }
