shared/irq/isr_entries.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This file contains the raw entry points for the exceptions.
0005  *
0006  *  COPYRIGHT (c) 1989-2000.
0007  *  On-Line Applications Research Corporation (OAR).
0008  *
0009  * Redistribution and use in source and binary forms, with or without
0010  * modification, are permitted provided that the following conditions
0011  * are met:
0012  * 1. Redistributions of source code must retain the above copyright
0013  *    notice, this list of conditions and the following disclaimer.
0014  * 2. Redistributions in binary form must reproduce the above copyright
0015  *    notice, this list of conditions and the following disclaimer in the
0016  *    documentation and/or other materials provided with the distribution.
0017  *
0018  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0019  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0020  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0021  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0022  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0023  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0024  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0025  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0026  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0027  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0028  * POSSIBILITY OF SUCH DAMAGE.
0029  */
0030
0031 #include <rtems/asm.h>
0032 #include <rtems/mips/iregdef.h>
0033 #include <rtems/mips/idtcpu.h>
0034
0035 /*
0036  *  MIPS ISA Level 1 entries
0037  */
0038
0039 #if __mips == 1
0040
0041 FRAME(exc_norm_code,sp,0,ra)
0042     la  k0, _ISR_Handler /* generic external int hndlr */
0043     j   k0
0044     nop
0045 ENDFRAME(exc_norm_code)
0046
0047 FRAME(exc_dbg_code,sp,0,ra)
0048         la      k0, _DBG_Handler /* debug interrupt */
0049         j       k0
0050     nop
0051 ENDFRAME(exc_dbg_code)
0052
0053 /* XXX this is dependent on IDT/SIM and needs to be addressed */
0054 FRAME(exc_utlb_code,sp,0,ra)
0055         la      k0, (R_VEC+((48)*8))
0056         j       k0
0057     nop
0058 ENDFRAME(exc_utlb_code)
0059
0060 /*
0061  * MIPS ISA Level 32
0062  * XXX Again, reliance on SIM. Not good.??????????
0063  */
0064 #elif __mips == 32
0065 FRAME(exc_tlb_code,sp,0,ra)
0066         la      k0, _ISR_Handler
0067         j       k0
0068     nop
0069 ENDFRAME(exc_tlb_code)
0070
0071 FRAME(exc_xtlb_code,sp,0,ra)
0072         la      k0, _ISR_Handler
0073         j       k0
0074     nop
0075
0076 ENDFRAME(exc_xtlb_code)
0077
0078 FRAME(exc_cache_code,sp,0,ra)
0079         la      k0, _ISR_Handler
0080         j       k0
0081     nop
0082 ENDFRAME(exc_cache_code)
0083
0084 FRAME(exc_norm_code,sp,0,ra)
0085     la  k0, _ISR_Handler /* generic external int hndlr */
0086     j   k0
0087     nop
0088 ENDFRAME(exc_norm_code)
0089
0090 /*
0091  * MIPS ISA Level 3
0092  * XXX Again, reliance on SIM. Not good.
0093  */
0094 #elif __mips == 3
0095
0096 FRAME(exc_tlb_code,sp,0,ra)
0097         la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
0098         j       k0
0099     nop
0100 ENDFRAME(exc_tlb_code)
0101
0102 FRAME(exc_xtlb_code,sp,0,ra)
0103         la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
0104         j       k0
0105     nop
0106
0107 ENDFRAME(exc_xtlb_code)
0108
0109 FRAME(exc_cache_code,sp,0,ra)
0110         la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
0111         j       k0
0112     nop
0113 ENDFRAME(exc_cache_code)
0114
0115 FRAME(exc_norm_code,sp,0,ra)
0116     la  k0, _ISR_Handler /* generic external int hndlr */
0117     j   k0
0118     nop
0119 ENDFRAME(exc_norm_code)
0120
0121 #else
0122
0123 #error "isr_entries.S: ISA support problem"
0124
0125 #endif