include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSImplClassicIntr
0007  *
0008  * @brief interrupt definitions.
0009  */
0010
0011 /*
0012  *  COPYRIGHT (c) 1989-2012.
0013  *  On-Line Applications Research Corporation (OAR).
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBBSP_MIPS_TX4938_IRQ_H
0038 #define LIBBSP_MIPS_TX4938_IRQ_H
0039
0040 #ifndef ASM
0041   #include <rtems.h>
0042   #include <rtems/irq.h>
0043   #include <rtems/irq-extension.h>
0044   #include <rtems/score/mips.h>
0045 #endif
0046
0047 /**
0048  * @addtogroup RTEMSImplClassicIntr
0049  *
0050  * @{
0051  */
0052
0053 /*
0054  *  Interrupt Vector Numbers
0055  *
0056  */
0057 #define TX4938_IRQ_ECC         MIPS_INTERRUPT_BASE+0
0058 #define TX4938_IRQ_WTE         MIPS_INTERRUPT_BASE+1
0059 #define TX4938_IRQ_INT0        MIPS_INTERRUPT_BASE+2
0060 #define TX4938_IRQ_INT1        MIPS_INTERRUPT_BASE+3
0061 #define TX4938_IRQ_INT2        MIPS_INTERRUPT_BASE+4
0062 #define TX4938_IRQ_INT3        MIPS_INTERRUPT_BASE+5
0063 #define TX4938_IRQ_INT4        MIPS_INTERRUPT_BASE+6
0064 #define TX4938_IRQ_INT5        MIPS_INTERRUPT_BASE+7
0065 #define TX4938_IRQ_SIO0        MIPS_INTERRUPT_BASE+8
0066 #define TX4938_IRQ_SIO1        MIPS_INTERRUPT_BASE+9
0067 #define TX4938_IRQ_DMAC00      MIPS_INTERRUPT_BASE+10
0068 #define TX4938_IRQ_DMAC01      MIPS_INTERRUPT_BASE+11
0069 #define TX4938_IRQ_DMAC02      MIPS_INTERRUPT_BASE+12
0070 #define TX4938_IRQ_DMAC03      MIPS_INTERRUPT_BASE+13
0071 #define TX4938_IRQ_IRC         MIPS_INTERRUPT_BASE+14
0072 #define TX4938_IRQ_PDMAC       MIPS_INTERRUPT_BASE+15
0073 #define TX4938_IRQ_PCIC        MIPS_INTERRUPT_BASE+16
0074 #define TX4938_IRQ_TMR0        MIPS_INTERRUPT_BASE+17
0075 #define TX4938_IRQ_TMR1        MIPS_INTERRUPT_BASE+18
0076 #define TX4938_IRQ_TMR2        MIPS_INTERRUPT_BASE+19
0077 #define TX4938_IRQ_RSV1        MIPS_INTERRUPT_BASE+20
0078 #define TX4938_IRQ_NDFMC       MIPS_INTERRUPT_BASE+21
0079 #define TX4938_IRQ_PCIERR      MIPS_INTERRUPT_BASE+22
0080 #define TX4938_IRQ_PCIPMC      MIPS_INTERRUPT_BASE+23
0081 #define TX4938_IRQ_ACLC        MIPS_INTERRUPT_BASE+24
0082 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+25
0083 #define TX4938_IRQ_PCIC1NT     MIPS_INTERRUPT_BASE+26
0084 #define TX4938_IRQ_ACLCPME     MIPS_INTERRUPT_BASE+27
0085 #define TX4938_IRQ_DMAC10      MIPS_INTERRUPT_BASE+28
0086 #define TX4938_IRQ_DMAC11      MIPS_INTERRUPT_BASE+29
0087 #define TX4938_IRQ_DMAC12      MIPS_INTERRUPT_BASE+30
0088 #define TX4938_IRQ_DMAC13      MIPS_INTERRUPT_BASE+31
0089
0090 #define TX4938_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+32
0091 #define TX4938_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+33
0092 #define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34
0093
0094 #define BSP_INTERRUPT_VECTOR_COUNT (TX4938_MAXIMUM_VECTORS + 1)
0095
0096 /** @} */
0097
0098 #endif /* LIBBSP_MIPS_JMR3904_IRQ_H */