rbtx4938/clock/clockdrv.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  Instantiate the clock driver shell.
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #include <rtems.h>
0036 #include <bsp/irq.h>
0037 #include <bsp.h>
0038
0039 #include <stdio.h>
0040 #include <stdlib.h>
0041
0042 #include "yamon_api.h"
0043
0044
0045 /* #define CLOCK_DRIVER_USE_FAST_IDLE 1 */
0046
0047 #define CLOCK_VECTOR TX4938_IRQ_TMR0
0048
0049 #define TX4938_TIMER_INTERVAL_MODE 1
0050
0051 #define TX4938_TIMER_MODE TX4938_TIMER_INTERVAL_MODE
0052
0053 #if (TX4938_TIMER_MODE == TX4938_TIMER_INTERVAL_MODE)
0054 #define TX4938_TIMER_INTERRUPT_FLAG TIIS
0055 #define Clock_driver_support_initialize_hardware() \
0056           Initialize_timer0_in_interval_mode()
0057 #else
0058 #error "Build Error: unsupported timer mode"
0059 #endif
0060
0061 void new_brk_esr(void);
0062
0063 t_yamon_retfunc esr_retfunc = 0;
0064 t_yamon_ref original_brk_esr = 0;
0065 t_yamon_ref original_tmr0_isr = 0;
0066
0067 void new_brk_esr(void)
0068 {
0069     if (original_tmr0_isr)
0070     {
0071         YAMON_FUNC_DEREGISTER_IC_ISR( original_tmr0_isr );
0072         original_tmr0_isr = 0;
0073     }
0074     if (esr_retfunc)
0075         esr_retfunc();
0076 }
0077
0078
0079 #define Clock_driver_support_install_isr( _new ) \
0080   do { \
0081     rtems_interrupt_handler_install( \
0082       CLOCK_VECTOR, \
0083       "clock", \
0084       0, \
0085       _new, \
0086       NULL \
0087     ); \
0088     YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
0089   } while(0)
0090
0091
0092 #define Clock_driver_support_at_tick(arg) \
0093   do { \
0094     uint32_t interrupt_flag; \
0095     do { \
0096         int loop_count; \
0097         TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \
0098             loop_count = 0; \
0099             do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \
0100                 /* Read back interrupt status register and isolate interval timer flag */ \
0101                 interrupt_flag = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR ) & TX4938_TIMER_INTERRUPT_FLAG; \
0102             } while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \
0103     } while(interrupt_flag); \
0104   } while(0)
0105
0106
0107 /* Setup timer in interval mode to generate peiodic interrupts */
0108 #define Initialize_timer0_in_interval_mode() \
0109   do { \
0110     uint32_t temp; \
0111     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0x0 ); /* Disable timer */ \
0112     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
0113     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \
0114     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CPRA, 0x3d090 ); /* Set tmier period ,10.0 msec (25 MHz timer clock) */ \
0115     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \
0116     temp = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR ); /* Enable interval timer interrupts */ \
0117     temp |= TIMER_INT_ENABLE_MASK; \
0118     TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, temp ); \
0119   } while(0)
0120
0121
0122 #define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
0123
0124 #include "../../../shared/dev/clock/clockimpl.h"