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0001 /*
0002 
0003 Based upon IDT provided code with the following release:
0004 
0005 This source code has been made available to you by IDT on an AS-IS
0006 basis. Anyone receiving this source is licensed under IDT copyrights
0007 to use it in any way he or she deems fit, including copying it,
0008 modifying it, compiling it, and redistributing it either with or
0009 without modifications.  No license under IDT patents or patent
0010 applications is to be implied by the copyright license.
0011 
0012 Any user of this software should understand that IDT cannot provide
0013 technical support for this software and will not be responsible for
0014 any consequences resulting from the use of this software.
0015 
0016 Any person who transfers this source code or any derivative work must
0017 include the IDT copyright notice, this paragraph, and the preceeding
0018 two paragraphs in the transferred software.
0019 
0020 COPYRIGHT IDT CORPORATION 1996
0021 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
0022 */
0023 
0024 
0025 /*
0026 **  idttlb.s - fetch the registers associated with and the contents
0027 **         of the tlb.
0028 **
0029 */
0030 /* 950308: Ketan patched a few tlb functions that would not have worked.*/
0031 #include <rtems/mips/iregdef.h>
0032 #include <rtems/mips/idtcpu.h>
0033 #include <rtems/asm.h>
0034 
0035 
0036     .text
0037 
0038 #if __mips == 1
0039 /*
0040 ** ret_tlblo -- returns the 'entrylo' contents for the TLB
0041 **  'c' callable - as ret_tlblo(index) - where index is the
0042 **  tlb entry to return the lo value for - if called from assembly
0043 **  language then index should be in register a0.
0044 */
0045 FRAME(ret_tlblo,sp,0,ra)
0046     .set    noreorder
0047     mfc0    t0,C0_SR        # save sr
0048     nop
0049     and t0,~SR_PE       # dont inadvertantly clear PE
0050     mtc0    zero,C0_SR      # clear interrupts
0051     mfc0    t1,C0_TLBHI     # save pid
0052     sll a0,TLBINX_INXSHIFT  # position index
0053     mtc0    a0,C0_INX       # write to index register
0054     nop
0055     tlbr                # put tlb entry in entrylo and hi
0056     nop
0057     mfc0    v0,C0_TLBLO     # get the requested entry lo
0058     mtc0    t1,C0_TLBHI     # restore pid
0059     mtc0    t0,C0_SR        # restore status register
0060     j   ra
0061     nop
0062     .set    reorder
0063 ENDFRAME(ret_tlblo)
0064 #endif
0065 #if __mips == 3
0066 /*
0067 ** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
0068 **  'c' callable - as ret_tlblo(index) - where index is the
0069 **  tlb entry to return the lo value for - if called from assembly
0070 **  language then index should be in register a0.
0071 */
0072 FRAME(ret_tlblo0,sp,0,ra)
0073     mfc0    t0,C0_SR        # save sr
0074     mtc0    zero,C0_SR      # clear interrupts
0075     mfc0    t1,C0_TLBHI     # save pid
0076     mtc0    a0,C0_INX       # write to index register
0077     .set noreorder
0078     nop; nop; nop; nop; nop; nop; nop; nop
0079     .set reorder
0080     tlbr                # put tlb entry in entrylo and hi
0081     .set noreorder
0082     nop; nop; nop; nop; nop; nop; nop; nop
0083     .set reorder
0084     mfc0    v0,C0_TLBLO0        # get the requested entry lo
0085     mtc0    t1,C0_TLBHI     # restore pid
0086     mtc0    t0,C0_SR        # restore status register
0087     j   ra
0088 ENDFRAME(ret_tlblo0)
0089 
0090 FRAME(ret_tlblo1,sp,0,ra)
0091     mfc0    t0,C0_SR        # save sr
0092     mtc0    zero,C0_SR      # clear interrupts
0093     mfc0    t1,C0_TLBHI     # save pid
0094     mtc0    a0,C0_INX       # write to index register
0095     .set noreorder
0096     nop; nop; nop; nop; nop; nop; nop; nop
0097     .set reorder
0098     tlbr                # put tlb entry in entrylo and hi
0099     .set noreorder
0100     nop; nop; nop; nop; nop; nop; nop; nop
0101     .set reorder
0102     mfc0    v0,C0_TLBLO1        # get the requested entry lo
0103     mtc0    t1,C0_TLBHI     # restore pid
0104     mtc0    t0,C0_SR        # restore status register
0105     j   ra
0106 ENDFRAME(ret_tlblo1)
0107 
0108 /*
0109 ** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
0110 */
0111 FRAME(ret_pagemask,sp,0,ra)
0112     mfc0    t0,C0_SR        # save sr
0113     mtc0    zero,C0_SR      # disable interrupts
0114     mfc0    t1,C0_TLBHI     # save current pid
0115     mtc0    a0,C0_INX       # drop it in C0 register
0116     .set noreorder
0117     nop; nop; nop; nop; nop; nop; nop; nop
0118     .set reorder
0119     tlbr                # read entry to entry hi/lo
0120     .set noreorder
0121     nop; nop; nop; nop; nop; nop; nop; nop
0122     .set reorder
0123     mfc0    v0,C0_PAGEMASK      # to return value
0124     mtc0    t1,C0_TLBHI     # restore current pid
0125     mtc0    t0,C0_SR        # restore sr
0126     j   ra
0127 ENDFRAME(ret_pagemask)
0128 
0129 /*
0130 ** ret_tlbwired(void) -- return wired register
0131 */
0132 FRAME(ret_tlbwired,sp,0,ra)
0133     mfc0    v0,C0_WIRED
0134     j   ra
0135 ENDFRAME(ret_tlbwired)
0136 #endif
0137 
0138 /*
0139 ** ret_tlbhi -- return the tlb entry high content for tlb entry
0140 **          index
0141 */
0142 FRAME(ret_tlbhi,sp,0,ra)
0143 #if __mips == 1
0144     .set    noreorder
0145     mfc0    t0,C0_SR        # save sr
0146     nop
0147     and t0,~SR_PE
0148     mtc0    zero,C0_SR      # disable interrupts
0149     mfc0    t1,C0_TLBHI     # save current pid
0150     sll a0,TLBINX_INXSHIFT  # position index
0151     mtc0    a0,C0_INX       # drop it in C0 register
0152     nop
0153     tlbr                # read entry to entry hi/lo
0154     nop
0155     mfc0    v0,C0_TLBHI     # to return value
0156     mtc0    t1,C0_TLBHI     # restore current pid
0157     mtc0    t0,C0_SR        # restore sr
0158     j   ra
0159     nop
0160     .set    reorder
0161 #endif
0162 #if __mips == 3
0163     mfc0    t0,C0_SR        # save sr
0164     mtc0    zero,C0_SR      # disable interrupts
0165     mfc0    t1,C0_TLBHI     # save current pid
0166     mtc0    a0,C0_INX       # drop it in C0 register
0167     .set noreorder
0168     nop; nop; nop; nop; nop; nop; nop; nop
0169     .set reorder
0170     tlbr                # read entry to entry hi/lo0/lo1/mask
0171     .set noreorder
0172     nop; nop; nop; nop; nop; nop; nop; nop
0173     .set reorder
0174     mfc0    v0,C0_TLBHI     # to return value
0175     mtc0    t1,C0_TLBHI     # restore current pid
0176     mtc0    t0,C0_SR        # restore sr
0177     j   ra
0178 #endif
0179 ENDFRAME(ret_tlbhi)
0180 
0181 /*
0182 ** ret_tlbpid() -- return tlb pid contained in the current entry hi
0183 */
0184 FRAME(ret_tlbpid,sp,0,ra)
0185 #if __mips == 1
0186     .set    noreorder
0187     mfc0    v0,C0_TLBHI     # fetch tlb high
0188     nop
0189     and v0,TLBHI_PIDMASK    # isolate and position
0190     srl v0,TLBHI_PIDSHIFT
0191     j   ra
0192     nop
0193     .set    reorder
0194 #endif
0195 #if __mips == 3
0196     mfc0    v0,C0_TLBHI # to return value
0197     nop
0198     and v0,TLBHI_PIDMASK
0199     j   ra
0200 #endif
0201 ENDFRAME(ret_tlbpid)
0202 
0203 /*
0204 ** tlbprobe(address, pid) -- probe the tlb to see if address is currently
0205 **              mapped
0206 **  a0 = vpn  - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
0207 **          virtual page numbers for the r3000 are in
0208 **          entry hi bits 31-12
0209 **  a1 = pid  - this is a process id ranging from 0 to 63
0210 **          this process id is shifted left 6 bits and or'ed into
0211 **          the entry hi register
0212 **  returns an index value (0-63) if successful -1 -f not
0213 */
0214 FRAME(tlbprobe,sp,0,ra)
0215 #if __mips == 1
0216     .set    noreorder
0217     mfc0    t0,C0_SR        /* fetch status reg */
0218     and a0,TLBHI_VPNMASK    /* isolate just the vpn */
0219     and t0,~SR_PE       /* don't inadvertantly clear pe */
0220     mtc0    zero,C0_SR
0221     mfc0    t1,C0_TLBHI
0222     sll a1,TLBHI_PIDSHIFT   /* possition the pid */
0223     and a1,TLBHI_PIDMASK
0224     or  a0,a1           /* build entry hi value */
0225     mtc0    a0,C0_TLBHI
0226     nop
0227     tlbp                /* do the probe */
0228     nop
0229     mfc0    v1,C0_INX
0230     li  v0,-1
0231     bltz    v1,1f
0232     nop
0233     sra v0,v1,TLBINX_INXSHIFT   /* get index positioned for return */
0234 1:
0235     mtc0    t1,C0_TLBHI     /* restore tlb hi */
0236     mtc0    t0,C0_SR        /* restore the status reg */
0237     j   ra
0238     nop
0239     .set    reorder
0240 #endif
0241 #if __mips == 3
0242     mfc0    t0,C0_SR        # save sr
0243     mtc0    zero,C0_SR      # disable interrupts
0244     mfc0    t1,C0_TLBHI     # save current pid
0245     and a0,TLBHI_VPN2MASK   # construct tlbhi for probe
0246     and a1,TLBHI_PIDMASK
0247     or  a0,a1
0248     mtc0    a0,C0_TLBHI
0249     .set noreorder
0250     nop; nop; nop; nop; nop; nop; nop; nop
0251     .set reorder
0252     tlbp                # probe entry to entry hi/lo0/lo1/mask
0253     .set noreorder
0254     nop; nop; nop; nop; nop; nop; nop; nop
0255     .set reorder
0256     mfc0    v1,C0_INX
0257     li  v0,-1
0258     bltz    v1,1f
0259     move    v0,v1
0260 1:  mtc0    t1,C0_TLBHI     # restore current pid
0261     mtc0    t0,C0_SR        # restore sr
0262     j   ra
0263 #endif
0264 ENDFRAME(tlbprobe)
0265 
0266 /*
0267 ** resettlb(index) Invalidate the  TLB entry specified by index
0268 */
0269 FRAME(resettlb,sp,0,ra)
0270 #if __mips == 1
0271     .set    noreorder
0272     mfc0    t0,C0_TLBHI     # fetch the current hi
0273     mfc0    v0,C0_SR        # fetch the status reg.
0274     li  t2,K0BASE&TLBHI_VPNMASK
0275     and v0,~SR_PE       # dont inadvertantly clear PE
0276     mtc0    zero,C0_SR
0277     mtc0    t2,C0_TLBHI     # set up tlbhi
0278     mtc0    zero,C0_TLBLO
0279     sll a0,TLBINX_INXSHIFT
0280     mtc0    a0,C0_INX
0281     nop
0282     tlbwi               # do actual invalidate
0283     nop
0284     mtc0    t0,C0_TLBHI
0285     mtc0    v0,C0_SR
0286     j   ra
0287     nop
0288     .set    reorder
0289 #endif
0290 #if __mips == 3
0291     li  t2,K0BASE&TLBHI_VPN2MASK
0292     mfc0    t0,C0_TLBHI     # save current TLBHI
0293     mfc0    v0,C0_SR        # save SR and disable interrupts
0294     mtc0    zero,C0_SR
0295     mtc0    t2,C0_TLBHI     # invalidate entry
0296     mtc0    zero,C0_TLBLO0
0297     mtc0    zero,C0_TLBLO1
0298     mtc0    a0,C0_INX
0299     .set noreorder
0300     nop; nop; nop; nop; nop; nop; nop; nop
0301     .set reorder
0302     tlbwi
0303     .set noreorder
0304     nop; nop; nop; nop; nop; nop; nop; nop
0305     .set reorder
0306     mtc0    t0,C0_TLBHI
0307     mtc0    v0,C0_SR
0308     j   ra
0309 #endif
0310 ENDFRAME(resettlb)
0311 
0312 #if __mips == 1
0313 /*
0314 ** Setup TLB entry
0315 **
0316 ** map_tlb(index, tlbhi, phypage)
0317 **  a0  =  TLB entry index
0318 **  a1  =  virtual page number and PID
0319 **  a2  =  physical page
0320 */
0321 FRAME(map_tlb,sp,0,ra)
0322     .set    noreorder
0323     sll a0,TLBINX_INXSHIFT
0324     mfc0    v0,C0_SR        # fetch the current status
0325     mfc0    a3,C0_TLBHI     # save the current hi
0326     and v0,~SR_PE       # dont inadvertantly clear parity
0327 
0328     mtc0    zero,C0_SR
0329     mtc0    a1,C0_TLBHI     # set the hi entry
0330     mtc0    a2,C0_TLBLO     # set the lo entry
0331     mtc0    a0,C0_INX       # load the index
0332     nop
0333     tlbwi               # put the hi/lo in tlb entry indexed
0334     nop
0335     mtc0    a3,C0_TLBHI     # put back the tlb hi reg
0336     mtc0    v0,C0_SR        # restore the status register
0337     j   ra
0338     nop
0339     .set    reorder
0340 ENDFRAME(map_tlb)
0341 #endif
0342 #if __mips == 3
0343 /*
0344 ** Setup R4000 TLB entry
0345 **
0346 ** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
0347 **  a0  =  TLB entry index and page mask
0348 **  a1  =  virtual page number and PID
0349 **      a2  =  pte -- contents of even pte
0350 **      a3  =  pte -- contents of odd pte
0351 */
0352 FRAME(map_tlb4000,sp,0,ra)
0353     and t2,a0,TLBPGMASK_MASK
0354     and a0,TLBINX_INXMASK
0355     mfc0    t1,C0_TLBHI     # save current TLBPID
0356     mfc0    v0,C0_SR        # save SR and disable interrupts
0357     mtc0    zero,C0_SR
0358     mtc0    t2,C0_PAGEMASK      # set
0359     mtc0    a1,C0_TLBHI     # set VPN and TLBPID
0360     mtc0    a2,C0_TLBLO0        # set PPN and access bits
0361     mtc0    a3,C0_TLBLO1        # set PPN and access bits
0362     mtc0    a0,C0_INX       # set INDEX to wired entry
0363     .set noreorder
0364     nop; nop; nop; nop; nop; nop; nop; nop
0365     .set reorder
0366     tlbwi               # drop it in
0367     .set noreorder
0368     nop; nop; nop; nop; nop; nop; nop; nop
0369     .set reorder
0370     mtc0    t1,C0_TLBHI     # restore TLBPID
0371     mtc0    v0,C0_SR        # restore SR
0372     j   ra
0373 ENDFRAME(map_tlb4000)
0374 #endif
0375 
0376 
0377 /*
0378 ** Set current TLBPID. This assumes PID is positioned correctly in reg.
0379 **          a0.
0380 */
0381 FRAME(set_tlbpid,sp,0,ra)
0382     .set    noreorder
0383     mtc0    a0,C0_TLBHI
0384     j   ra
0385     nop
0386     .set    reorder
0387 ENDFRAME(set_tlbpid)
0388
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