rbtx4925/clock/clockdrv.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  Instantiate the clock driver shell.
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #include <rtems.h>
0036 #include <bsp/irq.h>
0037 #include <bsp.h>
0038
0039 /* #define CLOCK_DRIVER_USE_FAST_IDLE 1 */
0040
0041 #define CLOCK_VECTOR TX4925_IRQ_TMR0
0042
0043 #define TX4925_TIMER_INTERVAL_MODE 1
0044 #define TX4925_TIMER_PULSE_MODE 2
0045 #define TX4925_TIMER_MODE TX4925_TIMER_INTERVAL_MODE
0046
0047 #if (TX4925_TIMER_MODE == TX4925_TIMER_INTERVAL_MODE)
0048 #define TX4925_TIMER_INTERRUPT_FLAG TIIS
0049 #define Clock_driver_support_initialize_hardware() \
0050           Initialize_timer0_in_interval_mode()
0051 #elif (TX4925_TIMER_MODE == TX4925_TIMER_PULSE_MODE)
0052 #define TX4925_TIMER_INTERRUPT_FLAG TPIBS
0053 #define Clock_driver_support_initialize_hardware() \
0054           Initialize_timer0_in_pulse_mode()
0055 #else
0056 #error "Build Error: need to select timer mode"
0057 #endif
0058
0059
0060 #define Clock_driver_support_install_isr( _new ) \
0061   rtems_interrupt_handler_install( CLOCK_VECTOR, "clock", 0, _new, NULL )
0062
0063
0064 #define Clock_driver_support_at_tick(arg) \
0065   do { \
0066     uint32_t interrupt_flag; \
0067     do { \
0068         int loop_count; \
0069         TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \
0070             loop_count = 0; \
0071             do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \
0072                 /* Read back interrupt status register and isolate interval timer flag */ \
0073                 interrupt_flag = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TISR ) & TX4925_TIMER_INTERRUPT_FLAG; \
0074             } while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \
0075     } while(interrupt_flag); \
0076   } while(0)
0077
0078
0079 /* Setup timer in interval mode to generate peiodic interrupts */
0080 #define Initialize_timer0_in_interval_mode() \
0081   do { \
0082     uint32_t temp; \
0083     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \
0084     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
0085     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \
0086     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x30d40 ); /* Set tmier period ,10.0 msec (20 MHz timer clock) */ \
0087     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \
0088     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \
0089     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \
0090     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \
0091     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \
0092     temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR ); /* Enable interval timer interrupts */ \
0093     temp |= TIMER_INT_ENABLE_MASK; \
0094     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_ITMR, temp ); \
0095   } while(0)
0096
0097
0098 /* This mode is used to generate periodic interrupts and also output a pulse on PIO20 pin */
0099 #define Initialize_timer0_in_pulse_mode() \
0100   do { \
0101     uint32_t temp; \
0102     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0x0 ); /* Disable timer */ \
0103     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
0104     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, FFI ); /* Set pulse generator mode register */ \
0105     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRA, 0x3e8 ); /* Set pulse high duration ,0.05 msec (20 MHz timer clock) */ \
0106 /*    TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x1388 ); */ /* Set pulse total period, 0.25 msec (20 MHz timer clock) */ \
0107     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_CPRB, 0x30d40 ); /* Set pulse total period, 10 msec (20 MHz timer clock) */ \
0108     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_TCR, 0xC1 ); /* Enable timer in pulse generator mode */ \
0109  \
0110     /* Enable timer 0 output pulses on PIO20 */ \
0111     temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_CFG_PCFG ); \
0112     temp = (temp & ~ SELCHI) | SELTMR0; /* Enable timer 0 pulses on PIO20 */ \
0113     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_CFG_PCFG, temp ); \
0114  \
0115     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DM0, 0x0 ); /* Set interrupt controller detection mode */ \
0116     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_LVL2, 0x1000000 ); /* Set interrupt controller level */ \
0117     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_MSK, 0x0 ); /* Set interrupt controller mask */ \
0118     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_IRQCTL_DEN, 0x1 ); /* Enable interrupts from controller */ \
0119     temp = TX4925_REG_READ( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR ); /* Enable pulse generator interrupt */ \
0120     temp |= TPIBE;  /* Only want interrupts on B compare (where clock count is cleared) */ \
0121     TX4925_REG_WRITE( TX4925_REG_BASE, TX4925_TIMER0_BASE + TX4925_TIMER_PGMR, temp ); \
0122   } while(0)
0123
0124
0125 #define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
0126
0127 #include "../../../shared/dev/clock/clockimpl.h"