malta/irq/vectorisrs.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  */
0007
0008 /*
0009  *  COPYRIGHT (c) 1989-2012.
0010  *  On-Line Applications Research Corporation (OAR).
0011  *
0012  * Redistribution and use in source and binary forms, with or without
0013  * modification, are permitted provided that the following conditions
0014  * are met:
0015  * 1. Redistributions of source code must retain the above copyright
0016  *    notice, this list of conditions and the following disclaimer.
0017  * 2. Redistributions in binary form must reproduce the above copyright
0018  *    notice, this list of conditions and the following disclaimer in the
0019  *    documentation and/or other materials provided with the distribution.
0020  *
0021  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0024  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0025  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0026  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0027  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0028  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0029  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0030  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0031  * POSSIBILITY OF SUCH DAMAGE.
0032  */
0033
0034 #include <rtems.h>
0035 #include <stdlib.h>
0036 #include <bsp/irq-generic.h>
0037 #include <bsp/pci.h>
0038 #include <bsp/i8259.h>
0039 #include <bsp.h>
0040 #include <libcpu/isr_entries.h>
0041
0042 void mips_default_isr( int vector );
0043
0044 #include <rtems/bspIo.h>  /* for printk */
0045
0046 void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
0047 {
0048   unsigned int sr;
0049   unsigned int cause;
0050   unsigned int pending;
0051
0052   mips_get_sr( sr );
0053   mips_get_cause( cause );
0054
0055   pending = (cause & sr & 0xff00) >> CAUSE_IPSHIFT;
0056
0057   /* SW Bits */
0058   if ( pending & 0x01) {
0059     printk("Pending IRQ Q 0x%x\n", pending );
0060   }
0061
0062   if ( pending & 0x02) {
0063     printk("Pending IRQ Q 0x%x\n", pending );
0064   }
0065
0066   /* South Bridge Interrupt */
0067   if ( pending & 0x04) {
0068      BSP_i8259s_int_process();
0069   }
0070
0071   /* South Bridge SMI */
0072   if (pending & 0x08){
0073     printk( "Pending IRQ 0x%x\n", pending );
0074   }
0075
0076   /* TTY 2 */
0077   if (pending & 0x10) {
0078     printk( "Pending IRQ 0x%x\n", pending );
0079   }
0080   /* Core HI */
0081   if (pending & 0x20) {
0082     printk( "Pending IRQ 0x%x\n", pending );
0083   }
0084    /* Core LO */
0085   if (pending & 0x40) {
0086     printk( "Pending IRQ 0x%x\n", pending );
0087   }
0088
0089   if ( pending & 0x80 ) {
0090     bsp_interrupt_handler_dispatch( MALTA_INT_TICKER );
0091   }
0092 }
0093
0094 void mips_default_isr( int vector )
0095 {
0096   unsigned int sr;
0097   unsigned int cause;
0098
0099   mips_get_sr( sr );
0100   mips_get_cause( cause );
0101
0102   printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
0103       vector, cause, sr );
0104
0105   while(1);      /* Lock it up */
0106
0107   rtems_fatal_error_occurred(1);
0108 }
0109