Warning, /bsps/mips/malta/README.md is written in an unsupported language. File is not indexed.
0001 Status
0002 ======
0003
0004 17 Februrary 2011
0005
0006 XXX
0007
0008 This is a BSP for the MIPS Malta board with a 24K CPU on it.
0009 It has ONLY been tested on Qemu.
0010
0011 Anything not mentioned has not been touched at all and will
0012 most likely not be in the first release of the BSP.
0013
0014 Working
0015 -------
0016 + Board initialization and shutdown
0017 + tty0 working polled
0018 + tty1 working polled (see note in issues)
0019 + tty2 working polled (see notes in issues)
0020 + Clock Tick
0021
0022
0023 Issues
0024 ------
0025 + We have small hack to Qemu so reset will exit. This needs to be
0026 fixed to follow the PC386 Qemu model where a command line argument
0027 selects reset or exit on reset.
0028
0029 + tty2 is generating an interrupt which causes a TLB fault. We have
0030 disabled the interrupt in the CPU interrupt mask for now.
0031
0032 + tty1 and tty2 are not showing any data on the screen. This is
0033 most likely an issue with qemu since the status bit is changing
0034 as the characters are polled out.
0035
0036 TBD
0037 ---
0038 + Conversion to Programmable Interrupt Controller IRQ model
0039 using shared infrastructure
0040 + tty0 working interrupt driver
0041 + tty1 working interrupt driver
0042 + tty2 working interrupt driver
0043 + PCI Bus Support
0044 + AMD AM79C973 NIC
0045 + Consider moving mips_interrupt_mask() into BSP.
