include/libcpu/tx4938.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  MIPS Tx4938 specific information
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef __TX4938_h
0036 #define __TX4938_h
0037
0038 #define TX4938_REG_BASE 0xFF1F0000
0039
0040 /* PCI1 Registers */
0041 #define TX4938_PCI1_PCIID       0x7000
0042 #define TX4938_PCI1_PCISTATUS   0x7004
0043 #define TX4938_PCI1_PCICFG1     0x700c
0044 #define TX4938_PCI1_P2GM1PLBASE 0x7018
0045 #define TX4938_PCI1_P2GCFG      0x7090
0046 #define TX4938_PCI1_PBAREQPORT  0x7100
0047 #define TX4938_PCI1_PBACFG      0x7104
0048 #define TX4938_PCI1_G2PM0GBASE  0x7120
0049 #define TX4938_PCI1_G2PIOGBASE  0x7138
0050 #define TX4938_PCI1_G2PM0MASK   0x7140
0051 #define TX4938_PCI1_G2PIOMASK   0x714c
0052 #define TX4938_PCI1_G2PM0PBASE  0x7150
0053 #define TX4938_PCI1_G2PIOPBASE  0x7168
0054 #define TX4938_PCI1_PCICCFG     0x7170
0055 #define TX4938_PCI1_PCICSTATUS  0x7174
0056 #define TX4938_PCI1_P2GM1GBASE  0x7188
0057 #define TX4938_PCI1_G2PCFGADRS  0x71a0
0058 #define TX4938_PCI1_G2PCFGDATA  0x71a4
0059
0060 /*
0061  *  Configuration Registers
0062  */
0063 #define TX4938_CFG_CCFG 0xE000      /* Chip Configuration Register */
0064 #define TX4938_CFG_REVID 0xE008     /* Chip Revision ID Register */
0065 #define TX4938_CFG_PCFG 0xE010      /* Pin Configuration Register */
0066 #define TX4938_CFG_TOEA 0xE018      /* TimeOut Error Access Address Register */
0067 #define TX4938_CFG_CLKCTR 0xE020        /* Clock Control Register */
0068 #define TX4938_CFG_GARBC 0xE030     /* GBUS Arbiter Control Register */
0069 #define TX4938_CFG_RAMP 0xE048      /* Register Address Mapping Register */
0070
0071 /* Pin Configuration register bits */
0072 #define SELCHI  0x00100000
0073 #define SELTMR0 0x00000200
0074
0075
0076 /*
0077  *  Timer Registers
0078  */
0079
0080 #define TX4938_TIMER0_BASE 0xF000
0081 #define TX4938_TIMER1_BASE 0xF100
0082 #define TX4938_TIMER2_BASE 0xF200
0083
0084 #define TX4938_TIMER_TCR  0x00          /* Timer Control Register */
0085 #define TX4938_TIMER_TISR 0x04          /* Timer Interrupt Status Register */
0086 #define TX4938_TIMER_CPRA 0x08          /* Compare Register A */
0087 #define TX4938_TIMER_CPRB 0x0C          /* Compare Register B */
0088 #define TX4938_TIMER_ITMR 0x10          /* Interval Timer Mode Register */
0089 #define TX4938_TIMER_CCDR 0x20          /* Divide Cycle Register */
0090 #define TX4938_TIMER_PGMR 0x30          /* Pulse Generator Mode Register */
0091 #define TX4938_TIMER_WTMR 0x40          /* Reserved Register */
0092 #define TX4938_TIMER_TRR  0xF0          /* Timer Read Register */
0093
0094 /* ITMR register bits */
0095 #define TIMER_CLEAR_ENABLE_MASK     0x1
0096 #define TIMER_INT_ENABLE_MASK   0x8000
0097
0098 /* PGMR register bits */
0099 #define FFI         0x1
0100 #define TPIAE       0x4000
0101 #define TPIBE       0x8000
0102
0103 /* TISR register bits */
0104 #define TIIS    0x1
0105 #define TPIAS   0x2
0106 #define TPIBS   0x4
0107 #define TWIS    0x8
0108
0109
0110 /*
0111  *  Interrupt Controller Registers
0112  */
0113 #define TX4938_IRQCTL_DEN 0xF600        /* Interrupt Detection Enable Register */
0114 #define TX4938_IRQCTL_DM0 0xF604        /* Interrupt Detection Mode Register 0 */
0115 #define TX4938_IRQCTL_DM1 0xF608        /* Interrupt Detection Mode Register 1 */
0116 #define TX4938_IRQCTL_LVL0 0xF610       /* Interrupt Level Register 0 */
0117 #define TX4938_IRQCTL_LVL1 0xF614       /* Interrupt Level Register 1 */
0118 #define TX4938_IRQCTL_LVL2 0xF618       /* Interrupt Level Register 2 */
0119 #define TX4938_IRQCTL_LVL3 0xF61C       /* Interrupt Level Register 3 */
0120 #define TX4938_IRQCTL_LVL4 0xF620       /* Interrupt Level Register 4 */
0121 #define TX4938_IRQCTL_LVL5 0xF624       /* Interrupt Level Register 5 */
0122 #define TX4938_IRQCTL_LVL6 0xF628       /* Interrupt Level Register 6 */
0123 #define TX4938_IRQCTL_LVL7 0xF62C       /* Interrupt Level Register 7 */
0124 #define TX4938_IRQCTL_MSK 0xF640        /* Interrupt Mask Register */
0125 #define TX4938_IRQCTL_EDC 0xF660        /* Interrupt Edge Detection Clear Register */
0126 #define TX4938_IRQCTL_PND 0xF680        /* Interrupt Pending Register */
0127 #define TX4938_IRQCTL_CS 0xF6A0         /* Interrupt Current Status Register */
0128 #define TX4938_IRQCTL_FLAG0 0xF510      /* Interrupt Request Flag Register 0 */
0129 #define TX4938_IRQCTL_FLAG1 0xF514      /* Interrupt Request Flag Register 1 */
0130 #define TX4938_IRQCTL_POL 0xF518        /* Interrupt Request Polarity Control Register */
0131 #define TX4938_IRQCTL_RCNT 0xF51C       /* Interrupt Request Control Register */
0132 #define TX4938_IRQCTL_MASKINT 0xF520    /* Interrupt Request Internal Interrupt Mask Register */
0133 #define TX4938_IRQCTL_MASKEXT 0xF524    /* Interrupt Request External Interrupt Mask Register */
0134
0135 #define TX4938_REG_READ( _base, _register ) \
0136   *((volatile uint32_t *)((_base) + (_register)))
0137
0138 #define TX4938_REG_WRITE( _base, _register, _value ) \
0139   *((volatile uint32_t *)((_base) + (_register))) = (_value)
0140
0141 /************************************************************************
0142  *      TX49 Register field encodings
0143 *************************************************************************/
0144 /******** reg: CCFG ********/
0145 /* field: PCIDIVMODE */
0146 #define TX4938_CCFG_SYSSP_SHF  6
0147 #define TX4938_CCFG_SYSSP_MSK  (MSK(2) << TX4938_CCFG_SYSSP_SHF)
0148
0149 /* field: PCI1DMD */
0150 #define TX4938_CCFG_PCI1DMD_SHF  8
0151 #define TX4938_CCFG_PCI1DMD_MSK  (MSK(1) << TX4938_CCFG_PCI1DMD_SHF)
0152
0153 /* field: PCIDIVMODE */
0154 #define TX4938_CCFG_PCIDIVMODE_SHF  10
0155 #define TX4938_CCFG_PCIDIVMODE_MSK  (MSK(3) << TX4938_CCFG_PCIDIVMODE_SHF)
0156
0157 /* field: PCI1-66 */
0158 #define TX4938_CCFG_PCI166_SHF  21
0159 #define TX4938_CCFG_PCI166_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCI166_SHF)
0160
0161 /* field: PCIMODE */
0162 #define TX4938_CCFG_PCIMODE_SHF  22
0163 #define TX4938_CCFG_PCIMODE_MSK  ((UINT64)MSK(1) << TX4938_CCFG_PCIMODE_SHF)
0164
0165 /* field: BRDTY */
0166 #define TX4938_CCFG_BRDTY_SHF  36
0167 #define TX4938_CCFG_RRDTY_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDTY_SHF)
0168
0169 /* field: BRDRV */
0170 #define TX4938_CCFG_BRDRV_SHF  32
0171 #define TX4938_CCFG_BRDRV_MSK  ((UINT64)MSK(4) << TX4938_CCFG_BRDRV_SHF)
0172
0173 /******** reg: CLKCTR ********/
0174 /* field: PCIC1RST */
0175 #define TX4938_CLKCTR_PCIC1RST_SHF  11
0176 #define TX4938_CLKCTR_PCIC1RST_MSK  (MSK(1) << TX4938_CLKCTR_PCIC1RST_SHF)
0177
0178 /******** reg: PCISTATUS ********/
0179 /* field: MEMSP */
0180 #define TX4938_PCI_PCISTATUS_MEMSP_SHF 1
0181 #define TX4938_PCI_PCISTATUS_MEMSP_MSK (MSK(1) << TX4938_PCI_PCISTATUS_MEMSP_SHF)
0182
0183 /* field: BM */
0184 #define TX4938_PCI_PCISTATUS_BM_SHF    2
0185 #define TX4938_PCI_PCISTATUS_BM_MSK    (MSK(1) << TX4938_PCI_PCISTATUS_BM_SHF)
0186
0187 /******** reg: PBACFG ********/
0188 /* field: RPBA */
0189 #define TX4938_PCI_PBACFG_RPBA_SHF     2
0190 #define TX4938_PCI_PBACFG_RPBA_MSK    (MSK(1) << TX4938_PCI_PBACFG_RPBA_SHF)
0191
0192 /* field: PBAEN */
0193 #define TX4938_PCI_PBACFG_PBAEN_SHF    1
0194 #define TX4938_PCI_PBACFG_PBAEN_MSK   (MSK(1) << TX4938_PCI_PBACFG_PBAEN_SHF)
0195
0196 /******** reg: PCICFG ********/
0197 /* field: G2PM0EN */
0198 #define TX4938_PCI_PCICFG_G2PM0EN_SHF  6
0199 #define TX4938_PCI_PCICFG_G2PM0EN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PM0EN_SHF)
0200
0201 /* field: G2PIOEN */
0202 #define TX4938_PCI_PCICFG_G2PIOEN_SHF  5
0203 #define TX4938_PCI_PCICFG_G2PIOEN_MSK (MSK(1) << TX4938_PCI_PCICFG_G2PIOEN_SHF)
0204
0205 /* field: TCAR */
0206 #define TX4938_PCI_PCICFG_TCAR_SHF  4
0207 #define TX4938_PCI_PCICFG_TCAR_MSK (MSK(1) << TX4938_PCI_PCICFG_TCAR_SHF)
0208
0209
0210 #endif