include/libcpu/tx4925.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  MIPS Tx4925 specific information
0007  */
0008
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  *
0022  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0023  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0024  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0025  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0026  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0027  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0028  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0029  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0030  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0031  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0032  * POSSIBILITY OF SUCH DAMAGE.
0033  */
0034
0035 #ifndef __TX4925_h
0036 #define __TX4925_h
0037
0038 #define TX4925_REG_BASE 0xFF1F0000
0039
0040
0041 /*
0042  *  Configuration Registers
0043  */
0044 #define TX4925_CFG_CCFG 0xE000      /* Chip Configuration Register */
0045 #define TX4925_CFG_REVID 0xE004     /* Chip Revision ID Register */
0046 #define TX4925_CFG_PCFG 0xE008      /* Pin Configuration Register */
0047 #define TX4925_CFG_TOEA 0xE00C      /* TimeOut Error Access Address Register */
0048 #define TX4925_CFG_PDNCTR 0xE010    /* Power Down Control Register */
0049 #define TX4925_CFG_GARBP 0xE018     /* GBUS Arbiter Priority Register */
0050 #define TX4925_CFG_TOCNT 0xE020     /* Timeout Count Register */
0051 #define TX4925_CFG_DRQCTR 0xE024        /* DMA Request Control Register */
0052 #define TX4925_CFG_CLKCTR 0xE028        /* Clock Control Register */
0053 #define TX4925_CFG_GARBC 0xE02C     /* GBUS Arbiter Control Register */
0054 #define TX4925_CFG_RAMP 0xE030      /* Register Address Mapping Register */
0055
0056 /* Pin Configuration register bits */
0057 #define SELCHI  0x00100000
0058 #define SELTMR0 0x00000200
0059
0060
0061 /*
0062  *  Timer Registers
0063  */
0064
0065 #define TX4925_TIMER0_BASE 0xF000
0066 #define TX4925_TIMER1_BASE 0xF100
0067 #define TX4925_TIMER2_BASE 0xF200
0068
0069 #define TX4925_TIMER_TCR  0x00          /* Timer Control Register */
0070 #define TX4925_TIMER_TISR 0x04          /* Timer Interrupt Status Register */
0071 #define TX4925_TIMER_CPRA 0x08          /* Compare Register A */
0072 #define TX4925_TIMER_CPRB 0x0C          /* Compare Register B */
0073 #define TX4925_TIMER_ITMR 0x10          /* Interval Timer Mode Register */
0074 #define TX4925_TIMER_CCDR 0x20          /* Divide Cycle Register */
0075 #define TX4925_TIMER_PGMR 0x30          /* Pulse Generator Mode Register */
0076 #define TX4925_TIMER_WTMR 0x40          /* Reserved Register */
0077 #define TX4925_TIMER_TRR  0xF0          /* Timer Read Register */
0078
0079 /* ITMR register bits */
0080 #define TIMER_CLEAR_ENABLE_MASK     0x1
0081 #define TIMER_INT_ENABLE_MASK   0x8000
0082
0083 /* PGMR register bits */
0084 #define FFI         0x1
0085 #define TPIAE       0x4000
0086 #define TPIBE       0x8000
0087
0088 /* TISR register bits */
0089 #define TIIS    0x1
0090 #define TPIAS   0x2
0091 #define TPIBS   0x4
0092 #define TWIS    0x8
0093
0094
0095 /*
0096  *  Interrupt Controller Registers
0097  */
0098 #define TX4925_IRQCTL_DEN 0xF600        /* Interrupt Detection Enable Register */
0099 #define TX4925_IRQCTL_DM0 0xF604        /* Interrupt Detection Mode Register 0 */
0100 #define TX4925_IRQCTL_DM1 0xF608        /* Interrupt Detection Mode Register 1 */
0101 #define TX4925_IRQCTL_LVL0 0xF610       /* Interrupt Level Register 0 */
0102 #define TX4925_IRQCTL_LVL1 0xF614       /* Interrupt Level Register 1 */
0103 #define TX4925_IRQCTL_LVL2 0xF618       /* Interrupt Level Register 2 */
0104 #define TX4925_IRQCTL_LVL3 0xF61C       /* Interrupt Level Register 3 */
0105 #define TX4925_IRQCTL_LVL4 0xF620       /* Interrupt Level Register 4 */
0106 #define TX4925_IRQCTL_LVL5 0xF624       /* Interrupt Level Register 5 */
0107 #define TX4925_IRQCTL_LVL6 0xF628       /* Interrupt Level Register 6 */
0108 #define TX4925_IRQCTL_LVL7 0xF62C       /* Interrupt Level Register 7 */
0109 #define TX4925_IRQCTL_MSK 0xF640        /* Interrupt Mask Register */
0110 #define TX4925_IRQCTL_EDC 0xF660        /* Interrupt Edge Detection Clear Register */
0111 #define TX4925_IRQCTL_PND 0xF680        /* Interrupt Pending Register */
0112 #define TX4925_IRQCTL_CS 0xF6A0         /* Interrupt Current Status Register */
0113 #define TX4925_IRQCTL_FLAG0 0xF510      /* Interrupt Request Flag Register 0 */
0114 #define TX4925_IRQCTL_FLAG1 0xF514      /* Interrupt Request Flag Register 1 */
0115 #define TX4925_IRQCTL_POL 0xF518        /* Interrupt Request Polarity Control Register */
0116 #define TX4925_IRQCTL_RCNT 0xF51C       /* Interrupt Request Control Register */
0117 #define TX4925_IRQCTL_MASKINT 0xF520    /* Interrupt Request Internal Interrupt Mask Register */
0118 #define TX4925_IRQCTL_MASKEXT 0xF524    /* Interrupt Request External Interrupt Mask Register */
0119
0120 #define TX4925_REG_READ( _base, _register ) \
0121   *((volatile uint32_t *)((_base) + (_register)))
0122
0123 #define TX4925_REG_WRITE( _base, _register, _value ) \
0124   *((volatile uint32_t *)((_base) + (_register))) = (_value)
0125
0126 #endif