include/libcpu/tx3904.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  MIPS Tx3904 specific information
0007  *
0008  *  NOTE: This is far from complete.  --joel (13 Dec 2000)
0009  */
0010
0011 /*
0012  *  COPYRIGHT (c) 1989-2012.
0013  *  On-Line Applications Research Corporation (OAR).
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef __TX3904_h
0038 #define __TX3904_h
0039
0040 /*
0041  *  Timer Base Addresses and Offsets
0042  */
0043
0044 #define TX3904_TIMER0_BASE 0xFFFFF000
0045 #define TX3904_TIMER1_BASE 0xFFFFF100
0046 #define TX3904_TIMER2_BASE 0xFFFFF200
0047
0048 #define TX3904_TIMER_TCR  0x00
0049 #define TX3904_TIMER_TISR 0x04
0050 #define TX3904_TIMER_CPRA 0x08
0051 #define TX3904_TIMER_CPRB 0x0C
0052 #define TX3904_TIMER_ITMR 0x10
0053 #define TX3904_TIMER_CCDR 0x20
0054 #define TX3904_TIMER_PGMR 0x30
0055 #define TX3904_TIMER_WTMR 0x40
0056 #define TX3904_TIMER_TRR  0xF0
0057
0058 #define TX3904_TIMER_READ( _base, _register ) \
0059   *((volatile uint32_t*)((_base) + (_register)))
0060
0061 #define TX3904_TIMER_WRITE( _base, _register, _value ) \
0062   *((volatile uint32_t*)((_base) + (_register))) = (_value)
0063
0064 #endif