include/bsp/regs.h

0001 /**
0002  * @file
0003  * @ingroup mips_regs
0004  * @brief Standard MIPS register names.
0005  */
0006
0007 /*
0008  * regs.S -- standard MIPS register names.
0009  *
0010  * Copyright (c) 1995 Cygnus Support
0011  *
0012  * The authors hereby grant permission to use, copy, modify, distribute,
0013  * and license this software and its documentation for any purpose, provided
0014  * that existing copyright notices are retained in all copies and that this
0015  * notice is included verbatim in any distributions. No written agreement,
0016  * license, or royalty fee is required for any of the authorized uses.
0017  * Modifications to this software may be copyrighted by their authors
0018  * and need not follow the licensing terms described here, provided that
0019  * the new terms are clearly indicated on the first page of each file where
0020  * they apply.
0021  */
0022
0023 /**
0024  * @defgroup mips_regs MIPS Registers
0025  * @ingroup RTEMSBSPsMIPSShared
0026  * @brief MIPS Registers
0027  * @{
0028  */
0029
0030 /**
0031  * @name Standard MIPS register names:
0032  * @{
0033  */
0034
0035 #define zero    $0
0036 #define z0  $0
0037 #define v0  $2
0038 #define v1  $3
0039 #define a0  $4
0040 #define a1  $5
0041 #define a2  $6
0042 #define a3  $7
0043 #define t0  $8
0044 #define t1  $9
0045 #define t2  $10
0046 #define t3  $11
0047 #define t4  $12
0048 #define t5  $13
0049 #define t6  $14
0050 #define t7  $15
0051 #define s0  $16
0052 #define s1  $17
0053 #define s2  $18
0054 #define s3  $19
0055 #define s4  $20
0056 #define s5  $21
0057 #define s6  $22
0058 #define s7  $23
0059 #define t8  $24
0060 #define t9  $25
0061 #define k0  $26 ///< @brief kernel private register 0 */
0062 #define k1  $27 ///< @brief kernel private register 1 */
0063 #define gp  $28 ///< @brief global data pointer */
0064 #define sp  $29 ///< @brief stack-pointer */
0065 #define fp  $30 ///< @brief frame-pointer */
0066 #define ra  $31 ///< @brief return address */
0067 #define pc  $pc ///< @brief pc, used on mips16 */
0068
0069 #define fp0 $f0
0070 #define fp1 $f1
0071
0072 /** @} */
0073
0074 /**
0075  * @name Useful memory constants:
0076  * @{
0077  */
0078
0079 #define K0BASE      0x80000000
0080 #ifndef __mips64
0081 #define K1BASE      0xA0000000
0082 #else
0083 #define K1BASE      0xFFFFFFFFA0000000LL
0084 #endif
0085
0086 /** @} */
0087
0088 #define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
0089
0090 /**
0091  * @name Standard Co-Processor 0 register numbers:
0092  * @{
0093  */
0094
0095 #define C0_COUNT    $9      ///< @brief Count Register */
0096 #define C0_SR       $12     ///< @brief Status Register */
0097 #define C0_CAUSE    $13     ///< @brief last exception description */
0098 #define C0_EPC      $14     ///< @brief Exception error address */
0099 #define C0_CONFIG   $16     ///< @brief CPU configuration */
0100
0101 /** @} */
0102
0103 /**
0104  * @name Standard Status Register bitmasks:
0105  * @{
0106  */
0107
0108 #define SR_CU1      0x20000000  ///< @brief Mark CP1 as usable */
0109 #define SR_FR       0x04000000  ///< @brief Enable MIPS III FP registers */
0110 #define SR_BEV      0x00400000  ///< @brief Controls location of exception vectors */
0111 #define SR_PE       0x00100000  ///< @brief Mark soft reset (clear parity error) */
0112
0113 #define SR_KX       0x00000080  ///< @brief Kernel extended addressing enabled */
0114 #define SR_SX       0x00000040  ///< @brief Supervisor extended addressing enabled */
0115 #define SR_UX       0x00000020  ///< @brief User extended addressing enabled */
0116
0117 /** @} */
0118
0119 /**
0120  * @name Standard (R4000) cache operations.
0121  * @brief Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
0122  * @{
0123  */
0124
0125 #define CACHE_I     (0) ///< @brief primary instruction */
0126 #define CACHE_D     (1) ///< @brief primary data */
0127 #define CACHE_SI    (2) ///< @brief secondary instruction */
0128 #define CACHE_SD    (3) ///< @brief secondary data (or combined instruction/data) */
0129
0130 #define INDEX_INVALIDATE        (0) ///< @brief also encodes WRITEBACK if CACHE_D or CACHE_SD */
0131 #define INDEX_LOAD_TAG          (1)
0132 #define INDEX_STORE_TAG         (2)
0133 #define CREATE_DIRTY_EXCLUSIVE      (3) ///< @brief CACHE_D and CACHE_SD only */
0134 #define HIT_INVALIDATE          (4)
0135 #define CACHE_FILL          (5) ///< @brief CACHE_I only */
0136 #define HIT_WRITEBACK_INVALIDATE    (5) ///< @brief CACHE_D and CACHE_SD only */
0137 #define HIT_WRITEBACK           (6) ///< @brief CACHE_I, CACHE_D and CACHE_SD only */
0138 #define HIT_SET_VIRTUAL         (7) ///< @brief CACHE_SI and CACHE_SD only */
0139
0140 #define BUILD_CACHE_OP(o,c)     (((o) << 2) | (c))
0141
0142 /** @} */
0143
0144 /**
0145  * @name Individual cache operations:
0146  * @{
0147  */
0148
0149 #define INDEX_INVALIDATE_I      BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
0150 #define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
0151 #define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
0152 #define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
0153
0154 #define INDEX_LOAD_TAG_I        BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
0155 #define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
0156 #define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
0157 #define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
0158
0159 #define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
0160 #define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
0161 #define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
0162 #define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
0163
0164 #define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
0165 #define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
0166
0167 #define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
0168 #define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
0169 #define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
0170 #define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
0171
0172 #define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
0173 #define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
0174 #define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
0175
0176 #define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
0177 #define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
0178 #define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
0179
0180 #define HIT_SET_VIRTUAL_SI      BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
0181 #define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
0182
0183 /** @} */
0184
0185 /** @} */
0186
0187 /*> EOF regs.S <*/