include/bsp/i8259.h

0001 /**
0002  * @file
0003  * @ingroup mips_i8259_irq
0004  * @brief Data structure and functions used to control i8259 chip.
0005  */
0006
0007 /* irq.h
0008  *
0009  *  This include file describe the data structure and the functions implemented
0010  *  by RTEMS to control the i8259 chip.
0011  *
0012  *  Copyright (C) 1999 valette@crf.canon.fr
0013  *
0014  *  This code is heavilly inspired by the public specification of STREAM V2
0015  *  that can be found at :
0016  *
0017  *      <http://www.chorus.com/Documentation/index.html> by following
0018  *  the STREAM API Specification Document link.
0019  *
0020  *  The license and distribution terms for this file may be
0021  *  found in the file LICENSE in this distribution or at
0022  *  http://www.rtems.org/license/LICENSE.
0023  */
0024
0025 #ifndef I8259_H
0026 #define I8259_H
0027
0028 /**
0029  * @defgroup mips_i8259_irq i8259 Chip Support
0030  * @ingroup RTEMSBSPsMIPSShared
0031  * @brief i8259 Chip Support
0032  * @{
0033  */
0034
0035 /**
0036  * @name 8259 edge/level control definitions at VIA
0037  * @{
0038  */
0039
0040 #if 1
0041 #define ISA8259_M_ELCR      0x4d0
0042 #define ISA8259_S_ELCR      0x4d1
0043 #endif
0044
0045 #define ELCRS_INT15_LVL         0x80
0046 #define ELCRS_INT14_LVL         0x40
0047 #define ELCRS_INT13_LVL         0x20
0048 #define ELCRS_INT12_LVL         0x10
0049 #define ELCRS_INT11_LVL         0x08
0050 #define ELCRS_INT10_LVL         0x04
0051 #define ELCRS_INT9_LVL          0x02
0052 #define ELCRS_INT8_LVL          0x01
0053 #define ELCRM_INT7_LVL          0x80
0054 #define ELCRM_INT6_LVL          0x40
0055 #define ELCRM_INT5_LVL          0x20
0056 #define ELCRM_INT4_LVL          0x10
0057 #define ELCRM_INT3_LVL          0x8
0058 #define ELCRM_INT2_LVL          0x4
0059 #define ELCRM_INT1_LVL          0x2
0060 #define ELCRM_INT0_LVL          0x1
0061
0062 /** @} */
0063
0064 /**
0065  * @name PIC's command and mask registers
0066  * @{
0067  */
0068
0069 #define PIC_MASTER_COMMAND_IO_PORT      0x20    ///< @brief Master PIC command register */
0070 #define PIC_SLAVE_COMMAND_IO_PORT       0xa0    ///< @brief Slave PIC command register */
0071 #define PIC_MASTER_IMR_IO_PORT          0x21    ///< @brief Master PIC Interrupt Mask Register */
0072 #define PIC_SLAVE_IMR_IO_PORT           0xa1    ///< @brief Slave PIC Interrupt Mask Register */
0073
0074 /** @} */
0075
0076 /**
0077  * @name Command for specific EOI (End Of Interrupt): Interrupt acknowledge
0078  * @{
0079  */
0080
0081 #define PIC_EOSI    0x60    ///< @brief End of Specific Interrupt (EOSI) */
0082 #define SLAVE_PIC_EOSI  0x62    ///< @brief End of Specific Interrupt (EOSI) for cascade */
0083 #define PIC_EOI     0x20    ///< @brief Generic End of Interrupt (EOI) */
0084
0085 /** @} */
0086
0087 #ifndef ASM
0088
0089 #ifdef __cplusplus
0090 extern "C" {
0091 #endif
0092
0093 /*
0094  * rtems_irq_number Definitions
0095  */
0096 #if 0
0097
0098 /**
0099  * @name ISA IRQ handler related definitions
0100  * @{
0101  */
0102
0103 #define BSP_ISA_IRQ_NUMBER      (16)
0104 #define BSP_ISA_IRQ_LOWEST_OFFSET   (0)
0105 #define BSP_ISA_IRQ_MAX_OFFSET      (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
0106
0107 /** @} */
0108
0109 #ifndef qemu
0110 #define BSP_PCI_IRQ_NUMBER      (16)
0111 #else
0112 #define BSP_PCI_IRQ_NUMBER      (0)
0113 #endif
0114 #define BSP_PCI_IRQ_LOWEST_OFFSET   (BSP_ISA_IRQ_NUMBER)
0115 #define BSP_PCI_IRQ_MAX_OFFSET      (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
0116
0117 /*
0118  * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
0119  * handler might be connected
0120  */
0121 #define BSP_PROCESSOR_IRQ_NUMBER    (1)
0122 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
0123 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
0124 /* Misc vectors for OPENPIC irqs (IPI, timers)
0125  */
0126 #ifndef qemu
0127 #define BSP_MISC_IRQ_NUMBER     (8)
0128 #else
0129 #define BSP_MISC_IRQ_NUMBER     (0)
0130 #endif
0131
0132 #define BSP_MISC_IRQ_LOWEST_OFFSET  (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
0133 #define BSP_MISC_IRQ_MAX_OFFSET     (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
0134
0135 /**
0136  * @name Summary
0137  * @{
0138  */
0139
0140 #define BSP_IRQ_NUMBER          (BSP_MISC_IRQ_MAX_OFFSET + 1)
0141 #define BSP_LOWEST_OFFSET       (BSP_ISA_IRQ_LOWEST_OFFSET)
0142 #define BSP_MAX_OFFSET          (BSP_MISC_IRQ_MAX_OFFSET)
0143
0144 /** @} */
0145
0146 /**
0147  * @name Some ISA IRQ symbolic name definition
0148  * @{
0149  */
0150
0151 #define BSP_ISA_PERIODIC_TIMER          (0)
0152 #define BSP_ISA_KEYBOARD            (1)
0153 #define BSP_ISA_UART_COM2_IRQ       (3)
0154 #define BSP_ISA_UART_COM1_IRQ       (4)
0155 #define BSP_ISA_RT_TIMER1           (8)
0156 #define BSP_ISA_RT_TIMER3       (10)
0157
0158 /** @} */
0159
0160 /**
0161  * @name Some PCI IRQ symbolic name definition
0162  * @{
0163  */
0164
0165 #define BSP_PCI_IRQ0            (BSP_PCI_IRQ_LOWEST_OFFSET)
0166 #if     BSP_PCI_IRQ_NUMBER > 0
0167 #define BSP_PCI_ISA_BRIDGE_IRQ      (BSP_PCI_IRQ0)
0168 #endif
0169
0170 /** @} */
0171
0172 #if defined(mot_ppc_mvme2100)
0173 #define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
0174 #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
0175 #define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
0176 #define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
0177 #define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
0178 #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
0179 #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
0180 #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
0181 #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
0182 #define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
0183 #define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
0184 #define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
0185 #else
0186 #define BSP_UART_COM1_IRQ       BSP_ISA_UART_COM1_IRQ
0187 #define BSP_UART_COM2_IRQ       BSP_ISA_UART_COM2_IRQ
0188 #endif
0189
0190 /**
0191  * @brief Some Processor execption handled as RTEMS IRQ symbolic name definition
0192  */
0193 #define BSP_DECREMENTER         (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
0194 #endif
0195
0196 /**
0197  * @name Type definition for RTEMS managed interrupts
0198  * @{
0199  */
0200
0201 typedef unsigned short rtems_i8259_masks;
0202 extern  volatile rtems_i8259_masks i8259s_cache;
0203
0204 /** @} */
0205
0206 /*-------------------------------------------------------------------------+
0207 | Function Prototypes.
0208 +--------------------------------------------------------------------------*/
0209 /*
0210  * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
0211  */
0212
0213 /**
0214  * @name Function Prototypes
0215  * @{
0216  */
0217
0218 void BSP_i8259s_init(void);
0219
0220 /**
0221  * @brief function to disable a particular irq at 8259 level.
0222  *
0223  * After calling this function, even if the device asserts the interrupt
0224  * line it will not be propagated further to the processor.
0225  *
0226  * @retval 1 the interrupt was enabled originally
0227  * @retval 0 the interrupt was disabled originally
0228  * @retval <0 error
0229  */
0230 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
0231
0232 /**
0233  * @brief function to enable a particular irq at 8259 level.
0234  *
0235  * After calling this function, if the device asserts the interrupt line
0236  * it will be propagated further to the processor.
0237  */
0238 int BSP_irq_enable_at_i8259s        (const rtems_irq_number irqLine);
0239
0240 /**
0241  * @brief function to acknowledge a particular irq at 8259 level.
0242  *
0243  * After calling this function, if a device asserts an enabled interrupt
0244  * line it will be propagated further to the processor. Mainly useful for
0245  * people writing raw handlers as this is automagically done for RTEMS managed
0246  * handlers.
0247  */
0248 int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
0249
0250 /**
0251  * @brief function to check if a particular irq is enabled at 8259 level.
0252  */
0253 int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
0254
0255 int BSP_i8259s_int_process(void);
0256
0257 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
0258 extern void BSP_i8259s_init(void);
0259
0260 /** @} */
0261
0262 /** @} */
0263
0264 #ifdef __cplusplus
0265 };
0266 #endif
0267
0268 #endif
0269 #endif