hurricane/start/usc.S

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*  usc.S
0004  *
0005  *  COPYRIGHT (c) 1989-2010.
0006  *  On-Line Applications Research Corporation (OAR).
0007  *
0008  * Redistribution and use in source and binary forms, with or without
0009  * modification, are permitted provided that the following conditions
0010  * are met:
0011  * 1. Redistributions of source code must retain the above copyright
0012  *    notice, this list of conditions and the following disclaimer.
0013  * 2. Redistributions in binary form must reproduce the above copyright
0014  *    notice, this list of conditions and the following disclaimer in the
0015  *    documentation and/or other materials provided with the distribution.
0016  *
0017  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0020  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0021  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0022  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0023  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0024  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0025  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0026  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0027  * POSSIBILITY OF SUCH DAMAGE.
0028  */
0029
0030 #include <bspopts.h>
0031 #include <rtems/asm.h>
0032 #include <rtems/mips/iregdef.h>
0033 #include <rtems/mips/idtcpu.h>
0034 #if BSP_HAS_USC320
0035   #include <usc.h>
0036 #endif
0037
0038
0039 /***************************************************************************
0040 **
0041 **   The following code was added to support boards using V3 USC320
0042 **     system controller chip.
0043 **
0044 ****************************************************************************/
0045
0046 /*************************************************************
0047 *  init_hbt()
0048 *   Initialize the heartbeat timer
0049 */
0050 FRAME(init_hbt,sp,0,ra)
0051     .set noreorder
0052     la  t0,SYSTEM   # Unlock USC registers
0053     li  t1,0xA5
0054     sb  t1,(t0)
0055
0056     la  t0,WD_HBI   # Initialize heatbeat and watchdog timers
0057
0058                 # (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
0059                 # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
0060                 # Watchdog period = 4000 * 5 = 20000 microseconds
0061     li  t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
0062
0063                 # (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
0064                 # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
0065                 # Watchdog period = 1000 * 20 = 20000 microseconds
0066     li  t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
0067
0068                 # (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
0069                 # Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
0070                 # Watchdog period = 10000 * 20 = 200000 microseconds
0071     li  t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14)
0072
0073     sw  t1,(t0)
0074
0075     la  t0,SYSTEM   # Lock USC registers
0076     li  t1,0x60
0077     sb  t1,(t0)
0078
0079     .set reorder
0080     j   ra
0081     nop
0082     .set reorder
0083 ENDFRAME(init_hbt)
0084
0085 /*************************************************************
0086 *  reset_wdt()
0087 *   Reset the watchdog timer
0088 */
0089 FRAME(reset_wdt,sp,0,ra)
0090     .set noreorder
0091
0092     la  t0,WD_HBI+2 # Load address watchdog timer reset byte
0093     li  t1,WD_INIT
0094     sb  t1,(t0)
0095
0096     .set reorder
0097     j   ra
0098     nop
0099     .set reorder
0100 ENDFRAME(reset_wdt)
0101
0102 /*************************************************************
0103 *  disable_wdt()
0104 *   Disable watchdog timer
0105 */
0106 FRAME(disable_wdt,sp,0,ra)
0107     .set noreorder
0108     la  t0,WD_HBI   # Clear watchdog enable bit in control register
0109     lw  t1,(t0)
0110     li  t2,~WD_EN
0111     and t1,t1,t2
0112     sw  t1,(t0)
0113
0114     .set reorder
0115     j   ra
0116     nop
0117     .set reorder
0118 ENDFRAME(disable_wdt)
0119
0120 /*************************************************************
0121 *  enable_hbi(ints)
0122 *   Enable the heartbeat interrupt
0123 */
0124 FRAME(enable_hbi,sp,0,ra)
0125     .set noreorder
0126
0127     la  t0,INT_CFG3 # Enable heartbeat interrupt in USC320
0128     lw  t1,(t0)
0129     li  t2,(HBI_MASK | MODE_TOTEM_POLE)
0130     or  t1,t1,t2
0131     sw  t1,(t0)
0132
0133     .set reorder
0134     j   ra
0135     nop
0136     .set reorder
0137 ENDFRAME(enable_hbi)
0138
0139 /*************************************************************
0140 *  disable_hbi(ints)
0141 *   Disable the heartbeat interrupt
0142 */
0143 FRAME(disable_hbi,sp,0,ra)
0144     .set noreorder
0145     la  t0,INT_CFG3 # Disable heartbeat interrupt in USC320
0146     lw  t1,(t0)
0147     li  t2,~HBI_MASK
0148     and t1,t1,t2
0149     sw  t1,(t0)
0150
0151     .set reorder
0152     j   ra
0153     nop
0154     .set reorder
0155 ENDFRAME(disable_hbi)
0156
0157
0158 /*************************************************************
0159 *  enable_wdi()
0160 *   Enable the watchdog interrupt
0161 */
0162 FRAME(enable_wdi,sp,0,ra)
0163     .set noreorder
0164
0165     la  t0,INT_CFG1 # Enable watchdog interrupt in USC320
0166     lw  t1,(t0)
0167     li  t2,(WDI_MASK | MODE_TOTEM_POLE)
0168     or  t1,t1,t2
0169     sw  t1,(t0)
0170
0171     .set reorder
0172     j   ra
0173     nop
0174     .set reorder
0175 ENDFRAME(enable_wdi)
0176
0177 /*************************************************************
0178 *  disable_wdi(ints)
0179 *   Disable the watchdog interrupt
0180 */
0181 FRAME(disable_wdi,sp,0,ra)
0182     .set noreorder
0183
0184     la  t0,INT_CFG1 # Disable watchdog interrupt in USC320
0185     lw  t1,(t0)
0186     li  t2,~(WDI_MASK | MODE_TOTEM_POLE)
0187     and t1,t1,t2
0188     sw  t1,(t0)
0189
0190     la  t0,INT_STAT # Clear watchdog interrupt status bit
0191     li  t1,WDI_MASK
0192     sw  t1,(t0)
0193
0194     .set reorder
0195     j   ra
0196     nop
0197     .set reorder
0198 ENDFRAME(disable_wdi)
0199