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File indexing completed on 2025-05-11 08:23:50
0001 /* 0002 0003 Based upon IDT provided code with the following release: 0004 0005 This source code has been made available to you by IDT on an AS-IS 0006 basis. Anyone receiving this source is licensed under IDT copyrights 0007 to use it in any way he or she deems fit, including copying it, 0008 modifying it, compiling it, and redistributing it either with or 0009 without modifications. No license under IDT patents or patent 0010 applications is to be implied by the copyright license. 0011 0012 Any user of this software should understand that IDT cannot provide 0013 technical support for this software and will not be responsible for 0014 any consequences resulting from the use of this software. 0015 0016 Any person who transfers this source code or any derivative work must 0017 include the IDT copyright notice, this paragraph, and the preceeding 0018 two paragraphs in the transferred software. 0019 0020 COPYRIGHT IDT CORPORATION 1996 0021 LICENSED MATERIAL - PROGRAM PROPERTY OF IDT 0022 */ 0023 0024 /************************************************************************* 0025 ** 0026 ** Copyright 1991-95 Integrated Device Technology, Inc. 0027 ** All Rights Reserved 0028 ** 0029 **************************************************************************/ 0030 0031 0032 #include <rtems/mips/iregdef.h> 0033 #include <rtems/mips/idtcpu.h> 0034 #include <rtems/asm.h> 0035 0036 #include <bsp.h> 0037 0038 #if 0 0039 .extern _fdata,4 /* this is defined by the linker */ 0040 .extern _edata,4 /* this is defined by the linker */ 0041 .extern _idata,4 /* this is defined by the linker */ 0042 #endif 0043 .extern _fbss,4 /* this is defined by the linker */ 0044 .extern end,4 /* this is defined by the linker */ 0045 0046 .lcomm sim_mem_cfg_struct,12 0047 0048 .text 0049 0050 /* For the V3 Eval board, we can safely assume that we have 0051 at least 16 megabytes of RAM */ 0052 #define HARD_CODED_MEM_SIZE 0x1000000 0053 0054 #define TMP_STKSIZE 1024 0055 0056 /* 0057 ** P_STACKSIZE is the size of the Prom Stack. 0058 ** the prom stack grows downward 0059 */ 0060 #define P_STACKSIZE 0x2000 /* sets stack size to 8k */ 0061 0062 /************************************************************************** 0063 ** 0064 ** start - Typical standalone start up code required for R3000/R4000 0065 ** 0066 ** 0067 ** 1) Initialize the STATUS Register 0068 ** a) Clear parity error bit 0069 ** b) Set co_processor 1 usable bit ON 0070 ** c) Clear all IntMask Enables 0071 ** d) Set kernel/disabled mode 0072 ** 2) Initialize Cause Register 0073 ** a) clear software interrupt bits 0074 ** 3) Determine FPU installed or not 0075 ** if not, clear CoProcessor 1 usable bit 0076 ** 4) Clear bss area 0077 ** 5) MUST allocate temporary stack until memory size determined 0078 ** It MUST be uncached to prevent overwriting when caches are cleared 0079 ** 6) Install exception handlers 0080 ** 7) Determine memory and cache sizes 0081 ** 8) Establish permanent stack (cached or uncached as defined by bss) 0082 ** 9) Flush Instruction and Data caches 0083 ** 10) If there is a Translation Lookaside Buffer, Clear the TLB 0084 ** 11) Execute initialization code if the IDT/c library is to be used 0085 ** 0086 ** 12) Jump to user's "main()" (boot_card() for RTEMS) 0087 ** 13) Jump to promexit 0088 ** 0089 ** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. 0090 ** This is used to mark code specific to R3xxx or R4xxx processors. 0091 ** IDT/C 6.x defines __mips to be the ISA level for which we're 0092 ** generating code. This is used to make sure the stack etc. is 0093 ** double word aligned, when using -mips3 (default) or -mips2, 0094 ** when compiling with IDT/C6.x 0095 ** 0096 ***************************************************************************/ 0097 0098 FRAME(start,sp,0,ra) 0099 0100 .set noreorder 0101 #if __mips_fpr == 64 0102 li v0,SR_CU1|SR_FR|SR_DE /* initally clear ERL, enable FPU with 64 bit regs, disable cache errors */ 0103 #else 0104 li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPU with 32 bit regs, disable cache errors */ 0105 #endif 0106 0107 mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ 0108 nop 0109 mtc0 zero,C0_CAUSE /* clear software interrupts */ 0110 nop 0111 0112 la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */ 0113 li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */ 0114 sw t1,0x10(t0) 0115 0116 li v0,CFG_C_NONCOHERENT # initialise default cache mode 0117 mtc0 v0,C0_CONFIG 0118 0119 /* 0120 ** check to see if an fpu is really plugged in 0121 */ 0122 li t3,0xaaaa5555 /* put a's and 5's in t3 */ 0123 mtc1 t3,fp0 /* try to write them into fp0 */ 0124 mtc1 zero,fp1 /* try to write zero in fp */ 0125 mfc1 t0,fp0 0126 mfc1 t1,fp1 0127 nop 0128 bne t0,t3,1f /* branch if no match */ 0129 nop 0130 bne t1,zero,1f /* double check for positive id */ 0131 nop 0132 /* We have a FPU. clear fcsr */ 0133 ctc1 zero, fcr31 0134 j 2f /* status register already correct */ 0135 nop 0136 1: 0137 li v0,SR_DE /* clear ERL and disable FPA */ 0138 0139 mtc0 v0, C0_SR /* reset status register */ 0140 2: 0141 la gp, _gp 0142 0143 #if 0 0144 /* Initialize data sections from "rom" copy */ 0145 la t0,_idata /* address of initialization data (copy of data sections placed in ROM) */ 0146 la t1,_fdata /* start of initialized data section */ 0147 la t2,_edata /* end of initialized data section */ 0148 3: 0149 lw t3,0(t0) 0150 sw t3,0(t1) 0151 addiu t1,t1,4 0152 bne t1,t2,3b 0153 addiu t0,t0,4 0154 #endif 0155 0156 /* clear bss before using it */ 0157 la v0,_fbss /* start of bss */ 0158 la v1,end /* end of bss */ 0159 4: sw zero,0(v0) 0160 bltu v0,v1,4b 0161 add v0,4 0162 0163 0164 /************************************************************************ 0165 ** 0166 ** Temporary Stack - needed to handle stack saves until 0167 ** memory size is determined and permanent stack set 0168 ** 0169 ** MUST be uncached to avoid confusion at cache 0170 ** switching during memory sizing 0171 ** 0172 *************************************************************************/ 0173 /* For MIPS 3, we need to be sure that the stack is aligned on a 0174 * double word boundary. 0175 */ 0176 andi t0, v0, 0x7 0177 beqz t0, 11f /* Last three bits Zero, already aligned */ 0178 nop 0179 add v0, 4 0180 11: 0181 0182 or v0, K1BASE /* switch to uncached */ 0183 add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ 0184 sub v1, v1, (4*4) /* overhead */ 0185 move sp, v1 /* set sp to top of stack */ 0186 4: sw zero, 0(v0) 0187 bltu v0, v1, 4b /* clear out temp stack */ 0188 add v0, 4 0189 0190 /* jal init_exc_vecs */ /* install exception handlers */ 0191 /* nop */ /* MUST do before memory probes */ 0192 0193 /* Force processor into uncached space during memory/cache probes */ 0194 la v0, 5f 0195 li v1, K1BASE 0196 or v0, v1 0197 j v0 0198 nop 0199 5: 0200 0201 li a0, HARD_CODED_MEM_SIZE /* Set memory size global */ 0202 jal set_memory_size 0203 nop 0204 0205 la a0, sim_mem_cfg_struct 0206 jal get_mem_conf /* Make call to get mem size */ 0207 nop 0208 la a0, sim_mem_cfg_struct 0209 lw a0, 0(a0) /* Get memory size from struct */ 0210 0211 jal config_cache /* determine size of D & I caches */ 0212 nop 0213 0214 move v0, a0 /* mem_size */ 0215 0216 /* For MIPS 3, we need to be sure that the stack (and hence v0 0217 * here) is aligned on a double word boundary. 0218 */ 0219 andi t0, v0, 0x7 0220 beqz t0, 12f /* Last three bits Zero, already aligned */ 0221 nop 0222 subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ 0223 12: 0224 0225 0226 0227 /************************************************************************** 0228 ** 0229 ** Permanent Stack - now know top of memory, put permanent stack there 0230 ** 0231 ***************************************************************************/ 0232 0233 la t2, _fbss /* cache mode as linked */ 0234 and t2, 0xF0000000 /* isolate segment */ 0235 la t1, 6f 0236 j t1 /* back to original cache mode */ 0237 nop 0238 6: 0239 or v0, t2 /* stack back to original cache mode */ 0240 addiu v0,v0,-16 /* overhead */ 0241 move sp, v0 /* now replace count w top of memory */ 0242 move v1, v0 0243 subu v1, P_STACKSIZE /* clear requested stack size */ 0244 0245 7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ 0246 bltu v1,v0,7b 0247 add v1, 4 0248 .set reorder 0249 0250 /* FIX THIS - This corrupts memory spaces */ 0251 /* jal flush_cache_nowrite */ /* flush Data & Instruction caches */ 0252 0253 /* jal mon_flush_cache */ 0254 0255 /************************************************************************** 0256 ** 0257 ** If this chip supports a Translation Lookaside Buffer, clear it 0258 ** 0259 ***************************************************************************/ 0260 0261 .set noreorder 0262 mfc0 t1, C0_SR /* look at Status Register */ 0263 nop 0264 .set reorder 0265 0266 jal init_tlb /* clear the tlb */ 0267 0268 /* Force processor into cached instruction space for rest of initialization */ 0269 #if 0 0270 la t0, 1f 0271 li t1, K0BASE /* force into cached space */ 0272 or t0, t1 0273 j t0 0274 nop 0275 1: 0276 #endif 0277 0278 /************************************************************************ 0279 ** 0280 ** Initialization required if using IDT/c or libc.a, standard C Lib 0281 ** 0282 ** can SKIP if not necessary for application 0283 ** 0284 ************************************************************************/ 0285 8: 0286 0287 /* FIX THIS - Need the pmon equivalent 0288 jal idtsim_init_sbrk 0289 jal idtsim_init_file 0290 */ 0291 0292 /*********************** END I/O initialization **********************/ 0293 0294 0295 move a0,zero /* Set command line passed to main */ 0296 la sp,_ISR_Stack_area_end # Use configuration defined stack 0297 subu sp,sp,32 0298 jal boot_card 0299 nop 0300 0301 # jump to the "exit" routine 0302 jal idtsim__exit 0303 move a0,v0 # pass through the exit code 0304 0305 0306 # FIX THIS - Need the pmon equivalent 0307 # jal idtsim_promexit 0308 0309 1: 0310 beq zero,zero,1b 0311 nop 0312 0313 ENDFRAME(start) 0314 0315 /* 0316 * _sys_exit -- Exit from the application. Normally we cause a user trap 0317 * to return to the ROM monitor for another run. NOTE: This is 0318 * the only other routine we provide in the crt0.o object, since 0319 * it may be tied to the "_start" routine. It also allows 0320 * executables that contain a complete world to be linked with 0321 * just the crt0.o object. 0322 */ 0323 FRAME(_sys_exit,sp,0,ra) 0324 0325 break 1023 0326 nop 0327 13: 0328 b 13b # but loop back just in-case 0329 nop 0330 0331 ENDFRAME(_sys_exit) 0332 0333 0334 0335 .globl __sizemem 0336 .ent __sizemem 0337 __sizemem: 0338 li v0,HARD_CODED_MEM_SIZE 0339 j ra 0340 nop 0341 .end __sizemem
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