include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSImplClassicIntr
0007  *
0008  * @brief interrupt definitions.
0009  */
0010
0011 /*
0012  *  COPYRIGHT (c) 1989-2012.
0013  *  On-Line Applications Research Corporation (OAR).
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #ifndef LIBBSP_MIPS_AU1X00_IRQ_H
0038 #define LIBBSP_MIPS_AU1X00_IRQ_H
0039
0040 #ifndef ASM
0041   #include <rtems.h>
0042   #include <rtems/irq.h>
0043   #include <rtems/irq-extension.h>
0044   #include <rtems/score/mips.h>
0045 #endif
0046
0047 /**
0048  * @addtogroup RTEMSImplClassicIntr
0049  *
0050  * @{
0051  */
0052
0053 /*
0054  *  Interrupt Vector Numbers
0055  *
0056  */
0057 /* MIPS_INTERRUPT_BASE should be 32 (0x20) */
0058 #define AU1X00_IRQ_SW0                (MIPS_INTERRUPT_BASE + 0)
0059 #define AU1X00_IRQ_SW1                (MIPS_INTERRUPT_BASE + 1)
0060 #define AU1X00_IRQ_IC0_REQ0           (MIPS_INTERRUPT_BASE + 2)
0061 #define AU1X00_IRQ_IC0_REQ1           (MIPS_INTERRUPT_BASE + 3)
0062 #define AU1X00_IRQ_IC1_REQ0           (MIPS_INTERRUPT_BASE + 4)
0063 #define AU1X00_IRQ_IC1_REQ1           (MIPS_INTERRUPT_BASE + 5)
0064 #define AU1X00_IRQ_PERF               (MIPS_INTERRUPT_BASE + 6)
0065 #define AU1X00_IRQ_CNT                (MIPS_INTERRUPT_BASE + 7)
0066
0067 #define AU1X00_IRQ_IC0_BASE           (MIPS_INTERRUPT_BASE + 8)
0068 #define AU1X00_IRQ_UART0              (MIPS_INTERRUPT_BASE + 8)
0069 #define AU1X00_IRQ_INTA               (MIPS_INTERRUPT_BASE + 9)
0070 #define AU1X00_IRQ_INTB               (MIPS_INTERRUPT_BASE + 10)
0071 #define AU1X00_IRQ_UART3              (MIPS_INTERRUPT_BASE + 11)
0072 #define AU1X00_IRQ_INTC               (MIPS_INTERRUPT_BASE + 12)
0073 #define AU1X00_IRQ_INTD               (MIPS_INTERRUPT_BASE + 13)
0074 #define AU1X00_IRQ_DMA0               (MIPS_INTERRUPT_BASE + 14)
0075 #define AU1X00_IRQ_DMA1               (MIPS_INTERRUPT_BASE + 15)
0076 #define AU1X00_IRQ_DMA2               (MIPS_INTERRUPT_BASE + 16)
0077 #define AU1X00_IRQ_DMA3               (MIPS_INTERRUPT_BASE + 17)
0078 #define AU1X00_IRQ_DMA4               (MIPS_INTERRUPT_BASE + 18)
0079 #define AU1X00_IRQ_DMA5               (MIPS_INTERRUPT_BASE + 19)
0080 #define AU1X00_IRQ_DMA6               (MIPS_INTERRUPT_BASE + 20)
0081 #define AU1X00_IRQ_DMA7               (MIPS_INTERRUPT_BASE + 21)
0082 #define AU1X00_IRQ_TOY_TICK           (MIPS_INTERRUPT_BASE + 22)
0083 #define AU1X00_IRQ_TOY_MATCH0         (MIPS_INTERRUPT_BASE + 23)
0084 #define AU1X00_IRQ_TOY_MATCH1         (MIPS_INTERRUPT_BASE + 24)
0085 #define AU1X00_IRQ_TOY_MATCH2         (MIPS_INTERRUPT_BASE + 25)
0086 #define AU1X00_IRQ_RTC_TICK           (MIPS_INTERRUPT_BASE + 26)
0087 #define AU1X00_IRQ_RTC_MATCH0         (MIPS_INTERRUPT_BASE + 27)
0088 #define AU1X00_IRQ_RTC_MATCH1         (MIPS_INTERRUPT_BASE + 28)
0089 #define AU1X00_IRQ_RTC_MATCH2         (MIPS_INTERRUPT_BASE + 29)
0090 #define AU1X00_IRQ_PCI_ERR            (MIPS_INTERRUPT_BASE + 30)
0091 #define AU1X00_IRQ_RSV0               (MIPS_INTERRUPT_BASE + 31)
0092 #define AU1X00_IRQ_USB_DEV            (MIPS_INTERRUPT_BASE + 32)
0093 #define AU1X00_IRQ_USB_SUSPEND        (MIPS_INTERRUPT_BASE + 33)
0094 #define AU1X00_IRQ_USB_HOST           (MIPS_INTERRUPT_BASE + 34)
0095 #define AU1X00_IRQ_AC97_ACSYNC        (MIPS_INTERRUPT_BASE + 35)
0096 #define AU1X00_IRQ_MAC0               (MIPS_INTERRUPT_BASE + 36)
0097 #define AU1X00_IRQ_MAC1               (MIPS_INTERRUPT_BASE + 37)
0098 #define AU1X00_IRQ_RSV1               (MIPS_INTERRUPT_BASE + 38)
0099 #define AU1X00_IRQ_AC97_CMD           (MIPS_INTERRUPT_BASE + 39)
0100
0101 #define AU1X00_IRQ_IC1_BASE           (MIPS_INTERRUPT_BASE + 40)
0102 #define AU1X00_IRQ_GPIO0              (MIPS_INTERRUPT_BASE + 40)
0103 #define AU1X00_IRQ_GPIO1              (MIPS_INTERRUPT_BASE + 41)
0104 #define AU1X00_IRQ_GPIO2              (MIPS_INTERRUPT_BASE + 42)
0105 #define AU1X00_IRQ_GPIO3              (MIPS_INTERRUPT_BASE + 43)
0106 #define AU1X00_IRQ_GPIO4              (MIPS_INTERRUPT_BASE + 44)
0107 #define AU1X00_IRQ_GPIO5              (MIPS_INTERRUPT_BASE + 45)
0108 #define AU1X00_IRQ_GPIO6              (MIPS_INTERRUPT_BASE + 46)
0109 #define AU1X00_IRQ_GPIO7              (MIPS_INTERRUPT_BASE + 47)
0110 #define AU1X00_IRQ_GPIO8              (MIPS_INTERRUPT_BASE + 48)
0111 #define AU1X00_IRQ_GPIO9              (MIPS_INTERRUPT_BASE + 49)
0112 #define AU1X00_IRQ_GPIO10             (MIPS_INTERRUPT_BASE + 50)
0113 #define AU1X00_IRQ_GPIO11             (MIPS_INTERRUPT_BASE + 51)
0114 #define AU1X00_IRQ_GPIO12             (MIPS_INTERRUPT_BASE + 52)
0115 #define AU1X00_IRQ_GPIO13             (MIPS_INTERRUPT_BASE + 53)
0116 #define AU1X00_IRQ_GPIO14             (MIPS_INTERRUPT_BASE + 54)
0117 #define AU1X00_IRQ_GPIO15             (MIPS_INTERRUPT_BASE + 55)
0118 #define AU1X00_IRQ_GPIO200            (MIPS_INTERRUPT_BASE + 56)
0119 #define AU1X00_IRQ_GPIO201            (MIPS_INTERRUPT_BASE + 57)
0120 #define AU1X00_IRQ_GPIO202            (MIPS_INTERRUPT_BASE + 58)
0121 #define AU1X00_IRQ_GPIO203            (MIPS_INTERRUPT_BASE + 59)
0122 #define AU1X00_IRQ_GPIO20             (MIPS_INTERRUPT_BASE + 60)
0123 #define AU1X00_IRQ_GPIO204            (MIPS_INTERRUPT_BASE + 61)
0124 #define AU1X00_IRQ_GPIO205            (MIPS_INTERRUPT_BASE + 62)
0125 #define AU1X00_IRQ_GPIO23             (MIPS_INTERRUPT_BASE + 63)
0126 #define AU1X00_IRQ_GPIO24             (MIPS_INTERRUPT_BASE + 64)
0127 #define AU1X00_IRQ_GPIO25             (MIPS_INTERRUPT_BASE + 65)
0128 #define AU1X00_IRQ_GPIO26             (MIPS_INTERRUPT_BASE + 66)
0129 #define AU1X00_IRQ_GPIO27             (MIPS_INTERRUPT_BASE + 67)
0130 #define AU1X00_IRQ_GPIO28             (MIPS_INTERRUPT_BASE + 68)
0131 #define AU1X00_IRQ_GPIO206            (MIPS_INTERRUPT_BASE + 69)
0132 #define AU1X00_IRQ_GPIO207            (MIPS_INTERRUPT_BASE + 70)
0133 #define AU1X00_IRQ_GPIO208_215        (MIPS_INTERRUPT_BASE + 71)
0134
0135 #define AU1X00_MAXIMUM_VECTORS        (MIPS_INTERRUPT_BASE + 72)
0136
0137 #define BSP_INTERRUPT_VECTOR_COUNT    (AU1X00_MAXIMUM_VECTORS + 1)
0138
0139 /** @} */
0140
0141 #endif /* LIBBSP_MIPS_AU1X00_IRQ_H */