microblaze_fpga/start/microblaze_invalidate_icache.S

0001 /******************************************************************************
0002 * Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005
0006 #include <bspopts.h>
0007
0008     .text
0009     .globl  microblaze_invalidate_icache
0010     .ent    microblaze_invalidate_icache
0011     .align  2
0012
0013 microblaze_invalidate_icache:
0014     addik   r5, r0, BSP_MICROBLAZE_FPGA_ICACHE_BASE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN))  /* Align to cache line */
0015     addik   r6, r5, BSP_MICROBLAZE_FPGA_ICACHE_SIZE & (-(4 * BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN))  /* Compute end */
0016
0017 L_start:
0018     wic r5, r0                                          /* Invalidate the Cache */
0019
0020     cmpu    r18, r5, r6                                     /* Are we at the end? */
0021     blei    r18, L_done
0022
0023     brid    L_start                                         /* Branch to the beginning of the loop */
0024     addik   r5, r5, (BSP_MICROBLAZE_FPGA_ICACHE_LINE_LEN * 4)   /* Increment the address by 4 (delay slot) */
0025 L_done:
0026     rtsd    r15, 8                                          /* Return */
0027     nop
0028     .end    microblaze_invalidate_icache