microblaze_fpga/start/microblaze_invalidate_dcache_range.S

0001 /******************************************************************************
0002 * Copyright (c) 2008 - 2020 Xilinx, Inc.  All rights reserved.
0003 * SPDX-License-Identifier: MIT
0004 ******************************************************************************/
0005 /******************************************************************************
0006 *
0007 *
0008 * microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
0009 *
0010 *    Invalidate a Dcache range
0011 *
0012 *    Parameters:
0013 *       'cacheaddr' - address in the Dcache where invalidation begins
0014 *   'len    '   - length (in bytes) worth of Dcache to be invalidated
0015 *
0016 *
0017 *******************************************************************************/
0018
0019 #include <bspopts.h>
0020
0021 #define MICROBLAZE_MSR_DCACHE_ENABLE        0x00000080
0022 #define MICROBLAZE_MSR_INTR_ENABLE          0x00000002
0023
0024 #ifndef XPAR_MICROBLAZE_USE_DCACHE
0025 #define XPAR_MICROBLAZE_USE_DCACHE     1
0026 #endif
0027
0028 #ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
0029 #define XPAR_MICROBLAZE_ALLOW_DCACHE_WR     1
0030 #endif
0031
0032 #ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
0033 #define MB_VERSION_LT_v720
0034 #define MB_HAS_WRITEBACK_SET 0
0035 #else
0036 #define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
0037 #endif
0038
0039     .text
0040     .globl  microblaze_invalidate_dcache_range
0041     .ent    microblaze_invalidate_dcache_range
0042     .align  2
0043
0044 microblaze_invalidate_dcache_range:
0045 #if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
0046
0047 #ifdef MB_VERSION_LT_v720                                       /* Disable Dcache and interrupts before invalidating */
0048     mfs r9, rmsr
0049     andi    r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
0050     mts rmsr, r10
0051 #endif
0052
0053         BEQI    r6, L_done                                      /* Skip loop if size is zero */
0054
0055         ADD r6, r5, r6                                      /* Compute end address */
0056         ADDIK   r6, r6, -1
0057
0058         ANDI    r6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align end down to cache line */
0059         ANDI    r5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)  /* Align start down to cache line */
0060
0061 #if MB_HAS_WRITEBACK_SET == 0                                   /* Use a different scheme for MB version < v7.20 or when caches are write-through */
0062
0063 L_start:
0064     CMPU    r18, r5, r6                                     /* Are we at the end? */
0065     BLTI    r18, L_done
0066
0067     wdc     r5, r0
0068
0069 #if defined (__arch64__ )
0070     addlik  r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)   /* Increment the address by 4 */
0071     breai   L_start                                         /* Branch to the beginning of the loop */
0072 #else
0073     brid    L_start                                         /* Branch to the beginning of the loop */
0074     addik   r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)   /* Increment the address by 4 (delay slot) */
0075 #endif
0076 #else
0077
0078         RSUBK   r6, r5, r6
0079                                                                 /* r6 will now contain (count of bytes - (4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) */
0080 L_start:
0081         wdc.clear r5, r6                                        /* Invalidate the cache line only if the address matches */
0082 #if defined (__arch64__ )
0083         addlik   r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)
0084         beagei r6, L_start
0085 #else
0086         bneid   r6, L_start
0087         addik   r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)
0088 #endif
0089
0090 #endif
0091
0092 L_done:
0093     rtsd    r15, 8
0094 #ifdef MB_VERSION_LT_v720                                       /* restore MSR only for MB version < v7.20 */
0095     mts rmsr, r9
0096 #else
0097         nop
0098 #endif
0099
0100 #else
0101     rtsd    r15, 8
0102     nop
0103 #endif
0104     .end    microblaze_invalidate_dcache_range