![]() |
|
|||
File indexing completed on 2025-05-11 08:23:49
0001 /****************************************************************************** 0002 * Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved. 0003 * SPDX-License-Identifier: MIT 0004 ******************************************************************************/ 0005 0006 .text 0007 .globl microblaze_enable_icache 0008 .ent microblaze_enable_icache 0009 .align 2 0010 microblaze_enable_icache: 0011 /* Read the MSR register */ 0012 mfs r8, rmsr 0013 /* Set the interrupt enable bit */ 0014 ori r8, r8, 0x20 0015 /* Save the MSR register */ 0016 mts rmsr, r8 0017 /* Return */ 0018 rtsd r15, 8 0019 nop 0020 .end microblaze_enable_icache
[ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
![]() ![]() |