microblaze_fpga/irq/irq.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsMicroblaze
0007  *
0008  * @brief MicroBlaze interrupt support
0009  */
0010
0011 /*
0012  * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp.h>
0037 #include <bsp/intc.h>
0038 #include <bsp/irq-generic.h>
0039
0040 #include <rtems/score/cpu.h>
0041
0042 static volatile Microblaze_INTC *mblaze_intc;
0043
0044 static void ack_interrupt( uint8_t source )
0045 {
0046   mblaze_intc->iar = 0x1 << source;
0047 }
0048
0049 rtems_status_code bsp_interrupt_get_attributes(
0050   rtems_vector_number         vector,
0051   rtems_interrupt_attributes *attributes
0052 )
0053 {
0054   attributes->is_maskable = true;
0055   attributes->maybe_enable = true;
0056   attributes->maybe_disable = true;
0057   attributes->can_clear = true;
0058   attributes->cleared_by_acknowledge = true;
0059
0060   return RTEMS_SUCCESSFUL;
0061 }
0062
0063 rtems_status_code bsp_interrupt_is_pending(
0064   rtems_vector_number vector,
0065   bool               *pending
0066 )
0067 {
0068   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0069   bsp_interrupt_assert( pending != NULL );
0070   *pending = false;
0071   return RTEMS_UNSATISFIED;
0072 }
0073
0074 rtems_status_code bsp_interrupt_raise( rtems_vector_number vector )
0075 {
0076   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0077   return RTEMS_UNSATISFIED;
0078 }
0079
0080 rtems_status_code bsp_interrupt_clear( rtems_vector_number vector )
0081 {
0082   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0083
0084   mblaze_intc->iar = 0x1 << vector;
0085
0086   return RTEMS_SUCCESSFUL;
0087 }
0088
0089 rtems_status_code bsp_interrupt_vector_is_enabled(
0090   rtems_vector_number vector,
0091   bool               *enabled
0092 )
0093 {
0094   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0095   bsp_interrupt_assert( enabled != NULL );
0096
0097   uint32_t mask = 1 << vector;
0098
0099   *enabled = (mblaze_intc->ier & mask) != 0;
0100   return RTEMS_SUCCESSFUL;
0101 }
0102
0103 rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector )
0104 {
0105   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0106
0107   uint32_t mask = 1 << vector;
0108
0109   mblaze_intc->ier |= mask;
0110
0111   return RTEMS_SUCCESSFUL;
0112 }
0113
0114 rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector )
0115 {
0116   bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) );
0117
0118   uint32_t mask = 1 << vector;
0119
0120   mblaze_intc->ier &= ~mask;
0121
0122   return RTEMS_SUCCESSFUL;
0123 }
0124
0125 rtems_status_code bsp_interrupt_set_priority(
0126   rtems_vector_number vector,
0127   uint32_t priority
0128 )
0129 {
0130   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0131   return RTEMS_UNSATISFIED;
0132 }
0133
0134 rtems_status_code bsp_interrupt_get_priority(
0135   rtems_vector_number vector,
0136   uint32_t *priority
0137 )
0138 {
0139   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0140   bsp_interrupt_assert(priority != NULL);
0141   return RTEMS_UNSATISFIED;
0142 }
0143
0144 void bsp_interrupt_facility_initialize( void )
0145 {
0146   /*
0147    * Enable HW interrupts on the interrupt controller. This happens before
0148    * interrupts are enabled on the processor.
0149    */
0150    mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree(
0151     "xlnx,xps-intc-1.00.a",
0152     "reg",
0153     BSP_MICROBLAZE_FPGA_INTC_BASE
0154    );
0155
0156   mblaze_intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE;
0157 }
0158
0159 void bsp_interrupt_dispatch( uint32_t source )
0160 {
0161   uint32_t vector_number = 0;
0162
0163   if ( source == 0xFF ) {
0164     /* Read interrupt controller to get the source */
0165     vector_number = mblaze_intc->isr & mblaze_intc->ier;
0166
0167     /* Handle and the first interrupt that is set */
0168     uint8_t interrupt_status = 0;
0169     for ( int i = 0; i < 32; i++ ) {
0170       interrupt_status = vector_number >> i & 0x1;
0171       if ( interrupt_status != 0 ) {
0172         /* save current ILR */
0173         uint32_t interrupt_levels = mblaze_intc->ilr;
0174         /* set ILR to block out every interrupt less than or equal to priority of i */
0175         mblaze_intc->ilr = 0xFFFFFFFF >> (32 - i);
0176         bsp_interrupt_handler_dispatch( i );
0177         ack_interrupt( i );
0178         /* restore ILR */
0179         mblaze_intc->ilr = interrupt_levels;
0180         break;
0181       }
0182     }
0183   } else {
0184     vector_number = source;
0185
0186     /* Fast interrupt mode. Handle interrupt. Ack happens automatically */
0187     bsp_interrupt_handler_dispatch( vector_number );
0188   }
0189 }