include/bsp/microblaze-gpio.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsMicroblaze
0007  *
0008  * @brief MicroBlaze AXI GPIO definitions
0009  */
0010
0011 /*
0012  * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H
0037 #define LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H
0038
0039 #include <bspopts.h>
0040 #include <bsp/utility.h>
0041 #include <rtems.h>
0042
0043 #ifdef __cplusplus
0044 extern "C" {
0045 #endif /* __cplusplus */
0046
0047 typedef struct {
0048   /* Channel 1 data values */
0049
0050   /*
0051    * Used to read general purpose input ports and write to general purpose
0052    * output ports from channel 1.
0053    */
0054   volatile uint32_t gpio_data;
0055
0056   /*
0057    * The 3-state control register for channel 1 is used for the dynamic
0058    * configuration of ports as input or output. When a bit is set to 1, the
0059    * corresponding I/O port is an input port. When a bit is set to 0, it is an
0060    * output port.
0061    */
0062   volatile uint32_t gpio_tri;
0063
0064   /* Channel 2 data values */
0065
0066   /*
0067    * Used to read general purpose input ports and write to general purpose
0068    * output ports from channel 2.
0069    */
0070   volatile uint32_t gpio2_data;
0071
0072   /*
0073    * The 3-state control register for channel 2 is used for the dynamic
0074    * configuration of ports as input or output. When a bit is set to 1, the
0075    * corresponding I/O port is an input port. When a bit is set to 0, it is an
0076    * output port.
0077    */
0078   volatile uint32_t gpio2_tri;
0079
0080   char _unused[272];
0081
0082   /* Only the 31st bit is used to enable interrupts globally */
0083 #define GLOBAL_INTERRUPT_REGISTER_ENABLE BSP_BIT32(31)
0084
0085   /*
0086    * Global Interrupt Enable Register
0087    *
0088    * Determines whether interrupts are enabled or disabled.
0089    *
0090    * 0 - Disabled
0091    * 1 - Enabled
0092    */
0093   volatile uint32_t gier;
0094
0095   char _unused2[12];
0096
0097   /* Used with ip_isr and ip_ier member variables */
0098 #define CHANNEL_1_INTERRUPT_REGISTER BSP_BIT32(0)
0099 #define CHANNEL_2_INTERRUPT_REGISTER BSP_BIT32(1)
0100
0101   /*
0102    * IP Status Registers
0103    *
0104    * Contains the status bit for each channel.
0105    *
0106    * 0 - Disabled
0107    * 1 - Enabled
0108    */
0109   volatile uint32_t ip_isr;
0110
0111   char _unused3[4];
0112
0113   /*
0114    * IP Interrupt Enable Register
0115    *
0116    * Provides the ability to independtly control whether interrupts for each
0117    * channel are enabled or disabled.
0118    *
0119    * 0 - No Channel input interrupt
0120    * 1 - Channel input interrupt
0121    */
0122   volatile uint32_t ip_ier;
0123 } Microblaze_GPIO_registers;
0124
0125 typedef struct {
0126   Microblaze_GPIO_registers *regs;
0127   bool                       is_dual;
0128   uint32_t                   irq;
0129   bool                       has_interrupts;
0130 } Microblaze_GPIO_context;
0131
0132 #ifdef BSP_MICROBLAZE_FPGA_USE_FDT
0133 /**
0134  * @brief Initialize GPIO context from FDT.
0135  *
0136  * @param[in] context the GPIO context to initialize
0137  * @param[in] index the zero-based GPIO index in the FDT
0138  *
0139  * @retval RTEMS_SUCCESSFUL on success
0140  * @retval RTEMS_INVALID_NUMBER if the index is invalid or the node is missing a
0141  *         required property
0142  * @retval RTEMS_INVALID_ADDRESS if the context is NULL
0143  */
0144 rtems_status_code microblaze_gpio_init_context_from_fdt(
0145   Microblaze_GPIO_context *context,
0146   int index
0147 );
0148 #endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
0149
0150 /**
0151  * @brief Set pin configuration for the specified GPIO channel.
0152  *
0153  * Changes the pin configuration for a channel. Bits set to 0 are output, and
0154  * bits set to 1 are input.
0155  *
0156  * @param[in] ctx the GPIO context
0157  * @param[in] channel the GPIO channel
0158  * @param[in] mask the mask to be applied to @ channel
0159  *
0160  * @retval None
0161  */
0162 void microblaze_gpio_set_data_direction(
0163   Microblaze_GPIO_context *ctx,
0164   uint32_t                 channel,
0165   uint32_t                 mask
0166 );
0167
0168 /**
0169  * @brief Get pin configuration for specified GPIO channel.
0170  *
0171  * Gets the current pin configuration for a specified GPIO channel. Bits set to
0172  * 0 are output, and bits set to 1 are input.
0173  *
0174  * @param[in] ctx the GPIO context
0175  * @param[in] channel the GPIO channel
0176  *
0177  * @retval bitmask specifiying which pins on a channel are input or output
0178  */
0179 uint32_t microblaze_gpio_get_data_direction(
0180   Microblaze_GPIO_context *ctx,
0181   uint32_t                 channel
0182 );
0183
0184 /**
0185  * @brief Reads data for specified GPIO channel.
0186  *
0187  * @param[in] channel the GPIO channel
0188  *
0189  * @retval Current values in discretes register.
0190  */
0191 uint32_t microblaze_gpio_discrete_read(
0192   Microblaze_GPIO_context *ctx,
0193   uint32_t                 channel
0194 );
0195
0196 /**
0197  * @brief Writes to data register for specified GPIO channel.
0198  *
0199  * @param[in] ctx the GPIO context
0200  * @param[in] channel the GPIO channel
0201  * @param[in] mask the mask to be applied to @ channel
0202  *
0203  * @retval None
0204  */
0205 void microblaze_gpio_discrete_write(
0206   Microblaze_GPIO_context *ctx,
0207   uint32_t                 channel,
0208   uint32_t                 mask
0209 );
0210
0211 /**
0212  * @brief Set bits to 1 on specified GPIO channel.
0213  *
0214  * @param[in] ctx the GPIO context
0215  * @param[in] channel the GPIO channel
0216  * @param[in] mask the mask to be applied to @ channel
0217  *
0218  * @retval None
0219  */
0220 void microblaze_gpio_discrete_set(
0221   Microblaze_GPIO_context *ctx,
0222   uint32_t                 channel,
0223   uint32_t                 mask
0224 );
0225
0226 /**
0227  * @brief Set bits to 0 on specified GPIO channel.
0228  *
0229  * @param[in] ctx the GPIO context
0230  * @param[in] channel the GPIO channel
0231  * @param[in] mask the mask to be applied to @ channel
0232  *
0233  * @retval None
0234  */
0235 void microblaze_gpio_discrete_clear(
0236   Microblaze_GPIO_context *ctx,
0237   uint32_t                 channel,
0238   uint32_t                 mask
0239 );
0240
0241 /**
0242  * @brief Returns the vector number of the interrupt handler.
0243  *
0244  * @param[in] ctx the GPIO context
0245  *
0246  * @retval the vector number
0247  */
0248 rtems_vector_number microblaze_gpio_get_irq( Microblaze_GPIO_context *ctx );
0249
0250 /**
0251  * @brief Turns on interrupts globally.
0252  *
0253  * @param[in] ctx the GPIO context
0254  *
0255  * @retval None
0256  */
0257 void microblaze_gpio_interrupt_global_enable( Microblaze_GPIO_context *ctx );
0258
0259 /**
0260  * @brief Turns off interrupts globally.
0261  *
0262  * @param[in] ctx the GPIO context
0263  *
0264  * @retval None
0265  */
0266 void microblaze_gpio_interrupt_global_disable( Microblaze_GPIO_context *ctx );
0267
0268 /**
0269  * @brief Enables interrupts on specified channel
0270  *
0271  * @param[in] ctx the GPIO context
0272  * @param[in] channel the channel to enable interrupts on
0273  *
0274  * @retval None
0275  */
0276 void microblaze_gpio_interrupt_enable(
0277   Microblaze_GPIO_context *ctx,
0278   uint32_t                 channel
0279 );
0280
0281 /**
0282  * @brief Disables interrupts on specified channel
0283  *
0284  * @param[in] ctx the GPIO context
0285  * @param[in] channel the channel to turn interrupts on for
0286  *
0287  * @retval None
0288  */
0289 void microblaze_gpio_interrupt_disable(
0290   Microblaze_GPIO_context *ctx,
0291   uint32_t                 channel
0292 );
0293
0294 /**
0295  * @brief Clear status of interrupt signals on a specific channel
0296  *
0297  * @param[in] ctx     the GPIO context
0298  * @param[in] channel the channel to clear the interrupt pending status from
0299  *
0300  * @retval None
0301  */
0302 void microblaze_gpio_interrupt_clear(
0303   Microblaze_GPIO_context *ctx,
0304   uint32_t                 channel
0305 );
0306
0307 /**
0308  * @brief Return a bitmask of the interrupts that are enabled
0309  *
0310  * @param[in] ctx the GPIO context
0311  *
0312  * @retval the bitmask of enabled interrupts
0313  */
0314 uint32_t microblaze_gpio_interrupt_get_enabled( Microblaze_GPIO_context *ctx );
0315
0316 /**
0317  * @brief Return a bitmask of the status of the interrupt signals
0318  *
0319  * @param[in] ctx the GPIO context
0320  *
0321  * @retval bitmask containing statuses of interrupt signals
0322  */
0323 uint32_t microblaze_gpio_interrupt_get_status( Microblaze_GPIO_context *ctx );
0324
0325 #ifdef __cplusplus
0326 }
0327 #endif /* __cplusplus */
0328
0329 #endif /* LIBBSP_MICROBLAZE_FPGA_MICROBLAZE_GPIO_H */