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0001 ColdFire 5282
0002 =============
0003
0004 Arcturus Networks uC DIMM ColdFire 5282
0005
0006 ```
0007 CPU: MCF5282, 64MHz
0008 RAM: 16M
0009 SRAM: 64k (BSP places FEC buffer descriptors here)
0010 ROM: 4M
0011 ```
0012
0013 This is a credit-card sized board in a DIMM format. It is part of a family
0014 which includes Dragonball and Coldfire CPUs, with a standardized DIMM-based bus.
0015
0016 ACKNOWLEDGEMENTS
0017 ----------------
0018 This BSP is based on the work of:
0019 D. Peter Siddons
0020 Till Straumann
0021 Brett Swimley
0022 Jay Monkman
0023
0024
0025 TODO
0026 ----
0027 The bsp relies on the Arcturus monitor to set up DRAM and all chip selects.
0028 This seems OK to me, but others may find it lame.....
0029
0030 I/O pin restrictions make simultaneous operation of I2C, CAN and UART2
0031 impossible. The BSP configures UART2 to use the CAN pins and leaves
0032 the I2C pins available for use.
0033
0034 ```
0035 BSP NAME: uC5282
0036 BOARD: Arcturus Netrworks uCdimm 5282
0037 BUS: Arcturus DIMM bus, A24/D16, plus peripherals.
0038 CPU FAMILY: ColdFire 5282
0039 CPU: MCF5282
0040 COPROCESSORS: N/A
0041
0042 DEBUG MONITOR: Arcturus bootloader
0043 ```
0044
0045 PERIPHERALS
0046 -----------
0047 ```
0048 TIMERS: Four PIT (RTEMS clock is PIT3), Four Timers
0049 RESOLUTION: 1 microsecond
0050 SERIAL PORTS: Internal UART 0, 1 and 2
0051 REAL-TIME CLOCK: none
0052 DMA: none
0053 VIDEO: none
0054 SCSI: none
0055 NETWORKING: Internal 10/100Mbs FEC, 100 Mb/s, full/half-duplex
0056 ```
0057
0058 DRIVER INFORMATION
0059 ------------------
0060 ```
0061 CLOCK DRIVER: PIT3
0062 IOSUPP DRIVER: none
0063 SHMSUPP: none
0064 TIMER DRIVER: TIMER3
0065 TTY DRIVER: UART0, 1 and 2
0066 ```
0067
0068 STDIO
0069 -----
0070 ```
0071 PORT: UART0 Terminal
0072 ELECTRICAL: RS-232
0073 BAUD: 9600
0074 BITS PER CHARACTER: 8
0075 PARITY: None
0076 STOP BITS: 1
0077 ```
0078
0079 Downloading the image to the board.
0080 -----------------------------------
0081 The bootable image is generated by the make-exe target in the bsp makefile. It
0082 generates a simple stripped binary file which is downloaded over the ethernet
0083 port into RAM then executed or programmed into flash memory.
0084
0085 1) Power up the uC5282 board. A dump of some memory maps is produced
0086 followed by a prompt.
0087
0088 2) (first time only)
0089 Set the uC5282 board Internet configuration:
0090 setenv IPADDR0 www.xxx.yyy.zzz (Your board's address)
0091 setenv NETMASK ppp.qqq.rrr.sss (Your local network address mask)
0092 setenv HOSTNAME somename (Your board's name)
0093
0094 3) Type 'tftp<CR>'
0095 This forces the network link to half-duplex. If your network link is
0096 locked at full duplex you'll have to find another port!
0097 The RTEMS network driver can be forced to 100 Mbs/full-duplex by setting
0098 the bootstrap environment variable IPADDR0_100FULL to Y. The driver can
0099 be forced to 10 Mbs/half-duplex by setting the bootstrap environment
0100 variable IPADDR0_10HALF to Y.
0101
0102 4) Run 'tftp' on your host machine:
0103 tftp> binary
0104 tftp> connect www.xxx.yyy.zzz (Your ucDIMM's address)
0105 tftp> put someFile.exe (someFile.boot for the EPICS build system)
0106
0107 5) When the file has downloaded press the <ESC> key to terminate
0108 the uCDIMM tftp command.
0109
0110 6) Type 'goram<CR>' to start the downloaded program, or type 'program<CR>'
0111 to burn the code onto the uCDIMM flash.
0112
0113
0114 Clock Speed Determination Algorithm
0115 -----------------------------------
0116 Till Straumann submitted a patch to provide more dynamic clock speed
0117 selection.
0118
0119 Currently, the uC5282 BSP requires relinking the application with a
0120 special linker flag in order to make it work with 80MHz boards (breaking
0121 run-time compatibility with 64MHz variants).
0122
0123 The change aims adds support for run-time guessing/setting of
0124 the system-clock frequency:
0125
0126 1) If uCbootloader environment variable SYS_CLOCK_SPEED is set to a
0127 non-zero number then the BSP assumes this number to specify the clock
0128 frequency in Hz.
0129
0130 2) If 1) yields no non-zero frequency then the linker-provided symbol
0131 _CPUClockSpeed is assumed to specify the clock frequency (in Hz). This
0132 is the traditional behavior but the default value of _CPUClockSpeed
0133 was changed from 64000000 to 0 (in order to let step 3) do it's work
0134 by default).
0135
0136 3) If neither 1) nor 2) yield a non-zero frequency then assume a PLL
0137 reference frequency (in Hz) as defined by the linker-provided symbol
0138 '_PLLRefClockSpeed' (which defaults to 8000000) and compute the system
0139 clock frequency from the divisor/multiplier settings in the SYNCR
0140 register.
0141
0142 We have both, 64MHz and 80MHz variants and both use a PLL reference of
0143 8MHz so that run-time heuristics + detection 3) work fine.
0144
0145
0146 EPICS Bootstrap Information
0147 ---------------------------
0148 The EPICS startup code uses the following environment variables. If an
0149 optional environment variable is missing the value in parentheses will be used.
0150 All Internet addresses must be given in 'dotted-decimal' format.
0151 HWADDR0 - Ethernet hardware address.
0152 IPADDR0 - Internet address (192.168.0.2).
0153 NETMASK - Local network address mask (255.255.252.0).
0154 HOSTNAME - Internet host name (iocNobody).
0155 GATEWAY - Internet address of gateway machine (NULL).
0156 SERVER - Internet address of NFS server (192.168.0.1).
0157 NAMESERVER - Internet address of DNS server (SERVER).
0158 DOMAIN - DNS domain name (precompiled value from CONFIG_SITE).
0159 NTPSERVER - Internet address of NTP server (SERVER).
0160 BOOTFILE - Path to executable (epics/iocNobody/bin/RTEMS-uC5282/myApp.boot).
0161 CMDLINE - Path to startup script (epics/iocBoot/iocNobody/st.cmd).
0162 NFSMOUNT - NFS information: www.xxx.yyy.zzz:/remote/path /localpath
0163 A : can also be used to separate the remote and local paths.
0164 If NFSMOUNT is not set, SERVER will be used as the NFS server,
0165 and the remote and local paths will be taken from the first
0166 component of CMDLINE. If CMDLINE does not begin with a /
0167 then '/tftpboot' is prepended to the remote path. This allows
0168 a remote TFTP and NFS server to be handled transaparently.
0169
0170
0171
0172 Memory map
0173 ----------
0174 ```
0175 Memory map as set up by dBUG bootstrap and BSP initialization
0176
0177 +--------------------------------------------------+
0178 0000 0000 | 16 MByte SDRAM | 00FF FFFF
0179 0100 0000 | --------------------------------------------- |
0180 | Address space for future SDRAM expansion |
0181 . .
0182 . .
0183 . .
0184 | | 0FFF FFFF
0185 +--------------------------------------------------+
0186 1000 0000 | External 4 MByte flash memory |
0187 . .
0188 . .
0189 . .
0190 | | 1FFF FFFF
0191 +--------------------------------------------------+
0192 2000 0000 | 64 kByte on-chip SRAM (RAMBAR) |
0193 . .
0194 . .
0195 . .
0196 | | 2FFF FFFF
0197 +--------------------------------------------------+
0198 3000 0000 | CS1* (devLib 'VME' A24 space) | 30FF FFFF
0199 3100 0000 | CS2* (devLib 'VME' A32 and A16 space) x| 31FF FFFF
0200 . .
0201 . .
0202 . .
0203 | | 3FFF FFFF
0204 +--------------------------------------------------+
0205 4000 0000 | Internal peripheral system (IPSBAR) |
0206 . .
0207 4400 0000 | Backdoor access to on-chip flash |
0208 . .
0209 . .
0210 . .
0211 | | 4FFF FFFF
0212 +--------------------------------------------------+
0213 . .
0214 . .
0215 . .
0216 +--------------------------------------------------+
0217 f000 0000 | 512 kByte on-chip flash (FLASHBAR) |
0218 . .
0219 . .
0220 . .
0221 | | fFFF FFFF
0222 +--------------------------------------------------+
0223
0224 x - Final 16-bit location of CS2* space is reserved for FPGA interrupt status.
0225 ```
0226
0227
0228
0229 Interrupt map
0230 -------------
0231 ```
0232 External interrupt lines (priority is fixed between 3 and 4):
0233 IRQ7* - Ethernet Transceiver interrupts
0234 IRQ1* - FPGA ('VME') interrupts.
0235 +-----+-----------------------------------------------------------------------+
0236 | | PRIORITY |
0237 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0238 |LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0239 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0240 | 7 | | | | | | | | |
0241 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0242 | 6 | | | | | | | | |
0243 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0244 | 5 | | | | | | | | |
0245 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0246 | 4 | FEC RX | FEC TX | | | | | | PIT |
0247 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0248 | 3 | UART 0 | UART 1 | UART 2 | | | | | |
0249 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0250 | 2 | | | | | | | | |
0251 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0252 | 1 | | | | | | | | |
0253 +-----+--------+--------+--------+--------+--------+--------+--------+--------+
0254 ```
0255
