File indexing completed on 2025-05-11 08:23:49
0001 #include "fpsp-namespace.h"
0002 //
0003 //
0004 // x_operr.sa 3.5 7/1/91
0005 //
0006 // fpsp_operr --- FPSP handler for operand error exception
0007 //
0008 // See 68040 User's Manual pp. 9-44f
0009 //
0010 // Note 1: For trap disabled 040 does the following:
0011 // If the dest is a fp reg, then an extended precision non_signaling
0012 // NAN is stored in the dest reg. If the dest format is b, w, or l and
0013 // the source op is a NAN, then garbage is stored as the result (actually
0014 // the upper 32 bits of the mantissa are sent to the integer unit). If
0015 // the dest format is integer (b, w, l) and the operr is caused by
0016 // integer overflow, or the source op is inf, then the result stored is
0017 // garbage.
0018 // There are three cases in which operr is incorrectly signaled on the
0019 // 040. This occurs for move_out of format b, w, or l for the largest
0020 // negative integer (-2^7 for b, -2^15 for w, -2^31 for l).
0021 //
0022 // On opclass = 011 fmove.(b,w,l) that causes a conversion
0023 // overflow -> OPERR, the exponent in wbte (and fpte) is:
0024 // byte 56 - (62 - exp)
0025 // word 48 - (62 - exp)
0026 // long 32 - (62 - exp)
0027 //
0028 // where exp = (true exp) - 1
0029 //
0030 // So, wbtemp and fptemp will contain the following on erroneously
0031 // signalled operr:
0032 // fpts = 1
0033 // fpte = $4000 (15 bit externally)
0034 // byte fptm = $ffffffff ffffff80
0035 // word fptm = $ffffffff ffff8000
0036 // long fptm = $ffffffff 80000000
0037 //
0038 // Note 2: For trap enabled 040 does the following:
0039 // If the inst is move_out, then same as Note 1.
0040 // If the inst is not move_out, the dest is not modified.
0041 // The exceptional operand is not defined for integer overflow
0042 // during a move_out.
0043 //
0044
0045 // Copyright (C) Motorola, Inc. 1990
0046 // All Rights Reserved
0047 //
0048 // THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
0049 // The copyright notice above does not evidence any
0050 // actual or intended publication of such source code.
0051
0052 X_OPERR: //idnt 2,1 | Motorola 040 Floating Point Software Package
0053
0054 |section 8
0055
0056 #include "fpsp.defs"
0057
0058 |xref mem_write
0059 |xref real_operr
0060 |xref real_inex
0061 |xref get_fline
0062 |xref fpsp_done
0063 |xref reg_dest
0064
0065 .global fpsp_operr
0066 fpsp_operr:
0067 //
0068 link %a6,#-LOCAL_SIZE
0069 fsave -(%a7)
0070 moveml %d0-%d1/%a0-%a1,USER_DA(%a6)
0071 fmovemx %fp0-%fp3,USER_FP0(%a6)
0072 fmoveml %fpcr/%fpsr/%fpiar,USER_FPCR(%a6)
0073
0074 //
0075 // Check if this is an opclass 3 instruction.
0076 // If so, fall through, else branch to operr_end
0077 //
0078 btstb #TFLAG,T_BYTE(%a6)
0079 beqs operr_end
0080
0081 //
0082 // If the destination size is B,W,or L, the operr must be
0083 // handled here.
0084 //
0085 movel CMDREG1B(%a6),%d0
0086 bfextu %d0{#3:#3},%d0 //0=long, 4=word, 6=byte
0087 cmpib #0,%d0 //determine size; check long
0088 beq operr_long
0089 cmpib #4,%d0 //check word
0090 beq operr_word
0091 cmpib #6,%d0 //check byte
0092 beq operr_byte
0093
0094 //
0095 // The size is not B,W,or L, so the operr is handled by the
0096 // kernel handler. Set the operr bits and clean up, leaving
0097 // only the integer exception frame on the stack, and the
0098 // fpu in the original exceptional state.
0099 //
0100 operr_end:
0101 bsetb #operr_bit,FPSR_EXCEPT(%a6)
0102 bsetb #aiop_bit,FPSR_AEXCEPT(%a6)
0103
0104 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
0105 fmovemx USER_FP0(%a6),%fp0-%fp3
0106 fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
0107 frestore (%a7)+
0108 unlk %a6
0109 bral real_operr
0110
0111 operr_long:
0112 moveql #4,%d1 //write size to d1
0113 moveb STAG(%a6),%d0 //test stag for nan
0114 andib #0xe0,%d0 //clr all but tag
0115 cmpib #0x60,%d0 //check for nan
0116 beq operr_nan
0117 cmpil #0x80000000,FPTEMP_LO(%a6) //test if ls lword is special
0118 bnes chklerr //if not equal, check for incorrect operr
0119 bsr check_upper //check if exp and ms mant are special
0120 tstl %d0
0121 bnes chklerr //if d0 is true, check for incorrect operr
0122 movel #0x80000000,%d0 //store special case result
0123 bsr operr_store
0124 bra not_enabled //clean and exit
0125 //
0126 // CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
0127 //
0128 chklerr:
0129 movew FPTEMP_EX(%a6),%d0
0130 andw #0x7FFF,%d0 //ignore sign bit
0131 cmpw #0x3FFE,%d0 //this is the only possible exponent value
0132 bnes chklerr2
0133 fixlong:
0134 movel FPTEMP_LO(%a6),%d0
0135 bsr operr_store
0136 bra not_enabled
0137 chklerr2:
0138 movew FPTEMP_EX(%a6),%d0
0139 andw #0x7FFF,%d0 //ignore sign bit
0140 cmpw #0x4000,%d0
0141 bcc store_max //exponent out of range
0142
0143 movel FPTEMP_LO(%a6),%d0
0144 andl #0x7FFF0000,%d0 //look for all 1's on bits 30-16
0145 cmpl #0x7FFF0000,%d0
0146 beqs fixlong
0147
0148 tstl FPTEMP_LO(%a6)
0149 bpls chklepos
0150 cmpl #0xFFFFFFFF,FPTEMP_HI(%a6)
0151 beqs fixlong
0152 bra store_max
0153 chklepos:
0154 tstl FPTEMP_HI(%a6)
0155 beqs fixlong
0156 bra store_max
0157
0158 operr_word:
0159 moveql #2,%d1 //write size to d1
0160 moveb STAG(%a6),%d0 //test stag for nan
0161 andib #0xe0,%d0 //clr all but tag
0162 cmpib #0x60,%d0 //check for nan
0163 beq operr_nan
0164 cmpil #0xffff8000,FPTEMP_LO(%a6) //test if ls lword is special
0165 bnes chkwerr //if not equal, check for incorrect operr
0166 bsr check_upper //check if exp and ms mant are special
0167 tstl %d0
0168 bnes chkwerr //if d0 is true, check for incorrect operr
0169 movel #0x80000000,%d0 //store special case result
0170 bsr operr_store
0171 bra not_enabled //clean and exit
0172 //
0173 // CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
0174 //
0175 chkwerr:
0176 movew FPTEMP_EX(%a6),%d0
0177 andw #0x7FFF,%d0 //ignore sign bit
0178 cmpw #0x3FFE,%d0 //this is the only possible exponent value
0179 bnes store_max
0180 movel FPTEMP_LO(%a6),%d0
0181 swap %d0
0182 bsr operr_store
0183 bra not_enabled
0184
0185 operr_byte:
0186 moveql #1,%d1 //write size to d1
0187 moveb STAG(%a6),%d0 //test stag for nan
0188 andib #0xe0,%d0 //clr all but tag
0189 cmpib #0x60,%d0 //check for nan
0190 beqs operr_nan
0191 cmpil #0xffffff80,FPTEMP_LO(%a6) //test if ls lword is special
0192 bnes chkberr //if not equal, check for incorrect operr
0193 bsr check_upper //check if exp and ms mant are special
0194 tstl %d0
0195 bnes chkberr //if d0 is true, check for incorrect operr
0196 movel #0x80000000,%d0 //store special case result
0197 bsr operr_store
0198 bra not_enabled //clean and exit
0199 //
0200 // CHECK FOR INCORRECTLY GENERATED OPERR EXCEPTION HERE
0201 //
0202 chkberr:
0203 movew FPTEMP_EX(%a6),%d0
0204 andw #0x7FFF,%d0 //ignore sign bit
0205 cmpw #0x3FFE,%d0 //this is the only possible exponent value
0206 bnes store_max
0207 movel FPTEMP_LO(%a6),%d0
0208 asll #8,%d0
0209 swap %d0
0210 bsr operr_store
0211 bra not_enabled
0212
0213 //
0214 // This operr condition is not of the special case. Set operr
0215 // and aiop and write the portion of the nan to memory for the
0216 // given size.
0217 //
0218 operr_nan:
0219 orl #opaop_mask,USER_FPSR(%a6) //set operr & aiop
0220
0221 movel ETEMP_HI(%a6),%d0 //output will be from upper 32 bits
0222 bsr operr_store
0223 bra end_operr
0224 //
0225 // Store_max loads the max pos or negative for the size, sets
0226 // the operr and aiop bits, and clears inex and ainex, incorrectly
0227 // set by the 040.
0228 //
0229 store_max:
0230 orl #opaop_mask,USER_FPSR(%a6) //set operr & aiop
0231 bclrb #inex2_bit,FPSR_EXCEPT(%a6)
0232 bclrb #ainex_bit,FPSR_AEXCEPT(%a6)
0233 fmovel #0,%FPSR
0234
0235 tstw FPTEMP_EX(%a6) //check sign
0236 blts load_neg
0237 movel #0x7fffffff,%d0
0238 bsr operr_store
0239 bra end_operr
0240 load_neg:
0241 movel #0x80000000,%d0
0242 bsr operr_store
0243 bra end_operr
0244
0245 //
0246 // This routine stores the data in d0, for the given size in d1,
0247 // to memory or data register as required. A read of the fline
0248 // is required to determine the destination.
0249 //
0250 operr_store:
0251 movel %d0,L_SCR1(%a6) //move write data to L_SCR1
0252 movel %d1,-(%a7) //save register size
0253 bsrl get_fline //fline returned in d0
0254 movel (%a7)+,%d1
0255 bftst %d0{#26:#3} //if mode is zero, dest is Dn
0256 bnes dest_mem
0257 //
0258 // Destination is Dn. Get register number from d0. Data is on
0259 // the stack at (a7). D1 has size: 1=byte,2=word,4=long/single
0260 //
0261 andil #7,%d0 //isolate register number
0262 cmpil #4,%d1
0263 beqs op_long //the most frequent case
0264 cmpil #2,%d1
0265 bnes op_con
0266 orl #8,%d0
0267 bras op_con
0268 op_long:
0269 orl #0x10,%d0
0270 op_con:
0271 movel %d0,%d1 //format size:reg for reg_dest
0272 bral reg_dest //call to reg_dest returns to caller
0273 // ;of operr_store
0274 //
0275 // Destination is memory. Get <ea> from integer exception frame
0276 // and call mem_write.
0277 //
0278 dest_mem:
0279 leal L_SCR1(%a6),%a0 //put ptr to write data in a0
0280 movel EXC_EA(%a6),%a1 //put user destination address in a1
0281 movel %d1,%d0 //put size in d0
0282 bsrl mem_write
0283 rts
0284 //
0285 // Check the exponent for $c000 and the upper 32 bits of the
0286 // mantissa for $ffffffff. If both are true, return d0 clr
0287 // and store the lower n bits of the least lword of FPTEMP
0288 // to d0 for write out. If not, it is a real operr, and set d0.
0289 //
0290 check_upper:
0291 cmpil #0xffffffff,FPTEMP_HI(%a6) //check if first byte is all 1's
0292 bnes true_operr //if not all 1's then was true operr
0293 cmpiw #0xc000,FPTEMP_EX(%a6) //check if incorrectly signalled
0294 beqs not_true_operr //branch if not true operr
0295 cmpiw #0xbfff,FPTEMP_EX(%a6) //check if incorrectly signalled
0296 beqs not_true_operr //branch if not true operr
0297 true_operr:
0298 movel #1,%d0 //signal real operr
0299 rts
0300 not_true_operr:
0301 clrl %d0 //signal no real operr
0302 rts
0303
0304 //
0305 // End_operr tests for operr enabled. If not, it cleans up the stack
0306 // and does an rte. If enabled, it cleans up the stack and branches
0307 // to the kernel operr handler with only the integer exception
0308 // frame on the stack and the fpu in the original exceptional state
0309 // with correct data written to the destination.
0310 //
0311 end_operr:
0312 btstb #operr_bit,FPCR_ENABLE(%a6)
0313 beqs not_enabled
0314 enabled:
0315 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
0316 fmovemx USER_FP0(%a6),%fp0-%fp3
0317 fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
0318 frestore (%a7)+
0319 unlk %a6
0320 bral real_operr
0321
0322 not_enabled:
0323 //
0324 // It is possible to have either inex2 or inex1 exceptions with the
0325 // operr. If the inex enable bit is set in the FPCR, and either
0326 // inex2 or inex1 occurred, we must clean up and branch to the
0327 // real inex handler.
0328 //
0329 ck_inex:
0330 moveb FPCR_ENABLE(%a6),%d0
0331 andb FPSR_EXCEPT(%a6),%d0
0332 andib #0x3,%d0
0333 beq operr_exit
0334 //
0335 // Inexact enabled and reported, and we must take an inexact exception.
0336 //
0337 take_inex:
0338 moveb #INEX_VEC,EXC_VEC+1(%a6)
0339 movel USER_FPSR(%a6),FPSR_SHADOW(%a6)
0340 orl #sx_mask,E_BYTE(%a6)
0341 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
0342 fmovemx USER_FP0(%a6),%fp0-%fp3
0343 fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
0344 frestore (%a7)+
0345 unlk %a6
0346 bral real_inex
0347 //
0348 // Since operr is only an E1 exception, there is no need to frestore
0349 // any state back to the fpu.
0350 //
0351 operr_exit:
0352 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
0353 fmovemx USER_FP0(%a6),%fp0-%fp3
0354 fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
0355 unlk %a6
0356 bral fpsp_done
0357
0358 |end
