shared/cache/cache-mcf532x.c

0001 /**
0002  *  @file
0003  *
0004  *  Cache Management Support Routines for the MCF532x
0005  */
0006
0007 #include <rtems.h>
0008 #include <mcf532x/mcf532x.h>
0009 #include "cache.h"
0010
0011 #define m68k_set_cacr(_cacr) \
0012   __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
0013
0014 /*
0015  * Read/write copy of common cache
0016  *  Default cache mode is *disabled* (cache only ACRx areas)
0017  *  Allow CPUSHL to invalidate a cache line
0018  *  Enable store buffer
0019  */
0020 static uint32_t cacr_mode = MCF_CACR_ESB |
0021                               MCF_CACR_DCM(3);
0022
0023 /*
0024  * Cannot be frozen
0025  */
0026 static void _CPU_cache_freeze_data(void)
0027 {
0028 }
0029
0030 static void _CPU_cache_unfreeze_data(void)
0031 {
0032 }
0033
0034 static void _CPU_cache_freeze_instruction(void)
0035 {
0036 }
0037
0038 static void _CPU_cache_unfreeze_instruction(void)
0039 {
0040 }
0041
0042 static void _CPU_cache_flush_1_data_line(const void *d_addr)
0043 {
0044   register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
0045
0046   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0047   adr += 1;
0048   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0049   adr += 1;
0050   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0051   adr += 1;
0052   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0053 }
0054
0055 static void _CPU_cache_flush_entire_data(void)
0056 {
0057   register unsigned long set, adr;
0058
0059   for(set = 0; set < 256; ++set) {
0060     adr = (set << 4);
0061     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0062     adr += 1;
0063     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0064     adr += 1;
0065     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0066     adr += 1;
0067     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0068   }
0069 }
0070
0071 static void _CPU_cache_enable_instruction(void)
0072 {
0073   rtems_interrupt_level level;
0074
0075   rtems_interrupt_disable(level);
0076   if(!(cacr_mode & MCF_CACR_CENB))
0077   {
0078     cacr_mode |= MCF_CACR_CENB;
0079     m68k_set_cacr(cacr_mode);
0080   }
0081   rtems_interrupt_enable(level);
0082 }
0083
0084 static void _CPU_cache_disable_instruction(void)
0085 {
0086   rtems_interrupt_level level;
0087
0088   rtems_interrupt_disable(level);
0089   if((cacr_mode & MCF_CACR_CENB))
0090   {
0091     cacr_mode &= ~MCF_CACR_CENB;
0092     m68k_set_cacr(cacr_mode);
0093   }
0094   rtems_interrupt_enable(level);
0095 }
0096
0097 static void _CPU_cache_invalidate_entire_instruction(void)
0098 {
0099   m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
0100 }
0101
0102 static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
0103 {
0104   register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
0105
0106   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0107   adr += 1;
0108   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0109   adr += 1;
0110   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0111   adr += 1;
0112   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
0113 }
0114
0115 static void _CPU_cache_enable_data(void)
0116 {
0117   /*
0118    * The 532x has a unified data and instruction cache, so we call through
0119    * to enable instruction.
0120    */
0121   _CPU_cache_enable_instruction();
0122 }
0123
0124 static void _CPU_cache_disable_data(void)
0125 {
0126   /*
0127    * The 532x has a unified data and instruction cache, so we call through
0128    * to disable instruction.
0129    */
0130   _CPU_cache_disable_instruction();
0131 }
0132
0133 static void _CPU_cache_invalidate_entire_data(void)
0134 {
0135   _CPU_cache_invalidate_entire_instruction();
0136 }
0137
0138 static void _CPU_cache_invalidate_1_data_line(const void *addr)
0139 {
0140   _CPU_cache_invalidate_1_instruction_line(addr);
0141 }
0142
0143 #include "../../../shared/cache/cacheimpl.h"