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File indexing completed on 2025-05-11 08:23:48

0001 /**
0002  *  @file
0003  *
0004  *  Cache Management Support Routines for the MCF5282
0005  */
0006 
0007 #include <rtems.h>
0008 #include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
0009 #include "cache.h"
0010 
0011 /*
0012  * CPU-space access
0013  */
0014 #define m68k_set_acr0(_acr0) \
0015   __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
0016 #define m68k_set_acr1(_acr1) \
0017   __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
0018 
0019 #define NOP __asm__ volatile ("nop");
0020 
0021 /*
0022  * DEFAULT WHEN mcf5xxx_initialize_cacr not called
0023  *   Read/write copy of common cache
0024  *   Split I/D cache
0025  *   Allow CPUSHL to invalidate a cache line
0026  *   Enable buffered writes
0027  *   No burst transfers on non-cacheable accesses
0028  *   Default cache mode is *disabled* (cache only ACRx areas)
0029  */
0030 static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
0031                             MCF5XXX_CACR_DBWE |
0032                             MCF5XXX_CACR_DCM;
0033 
0034 void mcf5xxx_initialize_cacr(uint32_t cacr)
0035 {
0036   cacr_mode = cacr;
0037   m68k_set_cacr( cacr_mode );
0038 }
0039 
0040 /*
0041  * Cannot be frozen
0042  */
0043 static void _CPU_cache_freeze_data(void) {}
0044 static void _CPU_cache_unfreeze_data(void) {}
0045 static void _CPU_cache_freeze_instruction(void) {}
0046 static void _CPU_cache_unfreeze_instruction(void) {}
0047 
0048 /*
0049  * Write-through data cache -- flushes are unnecessary
0050  */
0051 static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
0052 static void _CPU_cache_flush_entire_data(void) {}
0053 
0054 static void _CPU_cache_enable_instruction(void)
0055 {
0056   rtems_interrupt_level level;
0057 
0058   rtems_interrupt_disable(level);
0059     cacr_mode &= ~MCF5XXX_CACR_DIDI;
0060     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI );
0061     NOP;
0062   rtems_interrupt_enable(level);
0063 }
0064 
0065 static void _CPU_cache_disable_instruction(void)
0066 {
0067   rtems_interrupt_level level;
0068 
0069   rtems_interrupt_disable(level);
0070     cacr_mode |= MCF5XXX_CACR_DIDI;
0071     m68k_set_cacr(cacr_mode);
0072   rtems_interrupt_enable(level);
0073 }
0074 
0075 static void _CPU_cache_invalidate_entire_instruction(void)
0076 {
0077   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
0078   NOP;
0079 }
0080 
0081 static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
0082 {
0083   /*
0084    * Top half of cache is I-space
0085    */
0086   addr = (void *)((int)addr | 0x400);
0087   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
0088 }
0089 
0090 static void _CPU_cache_enable_data(void)
0091 {
0092   rtems_interrupt_level level;
0093 
0094   rtems_interrupt_disable(level);
0095     cacr_mode &= ~MCF5XXX_CACR_DISD;
0096     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
0097   rtems_interrupt_enable(level);
0098 }
0099 
0100 static void _CPU_cache_disable_data(void)
0101 {
0102   rtems_interrupt_level level;
0103 
0104   rtems_interrupt_disable(level);
0105     cacr_mode |= MCF5XXX_CACR_DISD;
0106     m68k_set_cacr(cacr_mode);
0107   rtems_interrupt_enable(level);
0108 }
0109 
0110 static void _CPU_cache_invalidate_entire_data(void)
0111 {
0112   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
0113 }
0114 
0115 static void _CPU_cache_invalidate_1_data_line(const void *addr)
0116 {
0117   /*
0118    * Bottom half of cache is D-space
0119    */
0120   addr = (void *)((int)addr & ~0x400);
0121   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
0122 }
0123 
0124 #include "../../../shared/cache/cacheimpl.h"