shared/cache/cache-mcf5235.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  COPYRIGHT (c) 1989-2008.
0005  *  On-Line Applications Research Corporation (OAR).
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions and the following disclaimer.
0012  * 2. Redistributions in binary form must reproduce the above copyright
0013  *    notice, this list of conditions and the following disclaimer in the
0014  *    documentation and/or other materials provided with the distribution.
0015  *
0016  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0019  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0020  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0021  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0022  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0023  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0024  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0025  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0026  * POSSIBILITY OF SUCH DAMAGE.
0027  */
0028
0029 #include <rtems.h>
0030 #include <mcf5235/mcf5235.h>
0031 #include "cache.h"
0032
0033 /*
0034  *  Default value for the cacr is set by the BSP
0035  */
0036 extern uint32_t cacr_mode;
0037
0038 /*
0039  * Cannot be frozen
0040  */
0041 static void _CPU_cache_freeze_data(void) {}
0042 static void _CPU_cache_unfreeze_data(void) {}
0043 static void _CPU_cache_freeze_instruction(void) {}
0044 static void _CPU_cache_unfreeze_instruction(void) {}
0045
0046 /*
0047  * Write-through data cache -- flushes are unnecessary
0048  */
0049 static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
0050 static void _CPU_cache_flush_entire_data(void) {}
0051
0052 static void _CPU_cache_enable_instruction(void)
0053 {
0054     rtems_interrupt_level level;
0055
0056     rtems_interrupt_disable(level);
0057     cacr_mode &= ~MCF5XXX_CACR_DIDI;
0058     m68k_set_cacr(cacr_mode);
0059     rtems_interrupt_enable(level);
0060 }
0061
0062 static void _CPU_cache_disable_instruction(void)
0063 {
0064     rtems_interrupt_level level;
0065
0066     rtems_interrupt_disable(level);
0067     cacr_mode |= MCF5XXX_CACR_DIDI;
0068     m68k_set_cacr(cacr_mode);
0069     rtems_interrupt_enable(level);
0070 }
0071
0072 static void _CPU_cache_invalidate_entire_instruction(void)
0073 {
0074     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
0075 }
0076
0077 static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
0078 {
0079     /*
0080      * Top half of cache is I-space
0081      */
0082     addr = (void *)((int)addr | 0x400);
0083     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
0084 }
0085
0086 static void _CPU_cache_enable_data(void)
0087 {
0088     rtems_interrupt_level level;
0089
0090     rtems_interrupt_disable(level);
0091     cacr_mode &= ~MCF5XXX_CACR_DISD;
0092     m68k_set_cacr(cacr_mode);
0093     rtems_interrupt_enable(level);
0094 }
0095
0096 static void _CPU_cache_disable_data(void)
0097 {
0098     rtems_interrupt_level level;
0099
0100     rtems_interrupt_disable(level);
0101     cacr_mode |= MCF5XXX_CACR_DISD;
0102     m68k_set_cacr(cacr_mode);
0103     rtems_interrupt_enable(level);
0104 }
0105
0106 static void _CPU_cache_invalidate_entire_data(void)
0107 {
0108     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
0109 }
0110
0111 static void _CPU_cache_invalidate_1_data_line(const void *addr)
0112 {
0113     /*
0114      * Bottom half of cache is D-space
0115      */
0116     addr = (void *)((int)addr & ~0x400);
0117     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
0118 }
0119
0120 #include "../../../shared/cache/cacheimpl.h"