Back to home page

LXR
 
 

    

File indexing completed on 2025-05-11 08:23:48 

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsM68kMVME167
0005  *
0006  * @brief Global BSP definitions.
0007  */
0008 
0009 /*
0010  *  COPYRIGHT (c) 1989-2012.
0011  *  On-Line Applications Research Corporation (OAR).
0012  *
0013  *  The license and distribution terms for this file may be
0014  *  found in the file LICENSE in this distribution or at
0015  *  http://www.rtems.org/license/LICENSE.
0016  *
0017  *  Modifications of respective RTEMS file:
0018  *  Copyright (c) 1998, National Research Council of Canada
0019  */
0020 
0021 #ifndef LIBBSP_M68K_MVME167_BSP_H
0022 #define LIBBSP_M68K_MVME167_BSP_H
0023 
0024 /**
0025  * @defgroup RTEMSBSPsM68kMVME162 MVME167
0026  *
0027  * @ingroup RTEMSBSPsM68k
0028  *
0029  * @brief MVME167 Board Support Package.
0030  *
0031  * @{
0032  */
0033 
0034 #include <bspopts.h>
0035 #include <bsp/default-initial-extension.h>
0036 
0037 #include <rtems.h>
0038 #include <rtems/bspIo.h>
0039 
0040 #include <mvme16x_hw.h>
0041 
0042 #ifdef __cplusplus
0043 extern "C" {
0044 #endif
0045 
0046 /* GCSR is in mvme16x_hw.h */
0047 /* LCSR is in mvme16x_hw.h */
0048 /* i82596 is in mvme16x_hw.h */
0049 /* NVRAM is in mvme16x_hw.h */
0050 
0051 #if 0
0052 /*
0053  *  Representation of the PCCchip2
0054  */
0055 typedef volatile struct pccchip2_regs_ {
0056   unsigned char     chip_id;            /* 0xFFF42000 */
0057   unsigned char     chip_revision;      /* 0xFFF42001 */
0058   unsigned char     gen_control;        /* 0xFFF42002 */
0059   unsigned char     vector_base;        /* 0xFFF42003 */
0060   unsigned long     timer_cmp_1;        /* 0xFFF42004 */
0061   unsigned long     timer_cnt_1;        /* 0xFFF42008 */
0062   unsigned long     timer_cmp_2;        /* 0xFFF4200C */
0063   unsigned long     timer_cnt_2;        /* 0xFFF42010 */
0064   unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
0065   unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
0066   unsigned char     timer_ctl_2;        /* 0xFFF42016 */
0067   unsigned char     timer_ctl_1;        /* 0xFFF42017 */
0068   unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
0069   unsigned char     gpio_ctl;           /* 0xFFF42019 */
0070   unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
0071   unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
0072   unsigned char     SCC_error;          /* 0xFFF4201C */
0073   unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
0074   unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
0075   unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
0076   unsigned char     reserved1[3];
0077   unsigned char     modem_piack;        /* 0xFFF42023 */
0078   unsigned char     reserved2;
0079   unsigned char     tx_piack;           /* 0xFFF42025 */
0080   unsigned char     reserved3;
0081   unsigned char     rx_piack;           /* 0xFFF42027 */
0082   unsigned char     LANC_error;         /* 0xFFF42028 */
0083   unsigned char     reserved4;
0084   unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
0085   unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
0086   unsigned char     SCSI_error;         /* 0xFFF4202C */
0087   unsigned char     reserved5[2];
0088   unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
0089   unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
0090   unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
0091   unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
0092   unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
0093   unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
0094   unsigned char     reserved6;
0095   unsigned char     print_input_status; /* 0xFFF42036 */
0096   unsigned char     print_ctl;          /* 0xFFF42037 */
0097   unsigned char     chip_speed;         /* 0xFFF42038 */
0098   unsigned char     reserved7;
0099   unsigned char     print_data;         /* 0xFFF4203A */
0100   unsigned char     reserved8[3];
0101   unsigned char     int_level;          /* 0xFFF4203E */
0102   unsigned char     int_mask;           /* 0xFFF4203F */
0103 } pccchip2_regs;
0104 
0105 /*
0106  *  Base address of the PCCchip2.
0107  *  This is not configurable in the MVME167.
0108  */
0109 #define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
0110 
0111 #endif
0112 /*
0113  * The MVME167 is equiped with one or two MEMC040 memory controllers at
0114  * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
0115  * were initialized by 167Bug.
0116  */
0117 typedef volatile struct memc040_regs_ {
0118   unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
0119   unsigned char     reserved1[3];
0120   unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
0121   unsigned char     reserved2[3];
0122   unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
0123   unsigned char     reserved3[3];
0124   unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
0125   unsigned char     reserved4[3];
0126   unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
0127   unsigned char     reserved5[3];
0128   unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
0129   unsigned char     reserved6[3];
0130   unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
0131   unsigned char     reserved7[3];
0132   unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
0133 } memc040_regs;
0134 
0135 /*
0136  *  Base address of the MEMC040s.
0137  *  This is not configurable in the MVME167.
0138  */
0139 #define memc040_1   ((memc040_regs * const) 0xFFF43000)
0140 #define memc040_2   ((memc040_regs * const) 0xFFF43100)
0141 
0142 /*
0143  *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
0144  *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
0145  *  assumes that these controllers, if present, are initialized by 167Bug.
0146  *  They do not appear to hold information of interest at this time, so they
0147  *  are not described. However, each MCECC pair lives at the same address as
0148  *  the MEMC040 is replaces. The first eight registers of the MCECC are
0149  *  nearly identical to the ones of the MEMC040, and the memc040_X structures
0150  *  can be used to read those first eight registers.
0151  */
0152 
0153 /*
0154  *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
0155  */
0156 typedef volatile struct cd2401_regs_ {
0157   unsigned char     reserved1[7];
0158   unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
0159   unsigned char     reserved2;
0160   unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
0161   unsigned char     reserved3[6];
0162   unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
0163   unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
0164   unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
0165   unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
0166   unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
0167   unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
0168   unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
0169   unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
0170   unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
0171   unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
0172   unsigned char     csr;            /* 0xFFF4501A - Channel Status */
0173   unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
0174   union {
0175     struct {
0176       unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
0177       unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
0178       unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
0179       unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
0180     } async;
0181     struct {
0182       unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
0183       unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
0184       unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
0185       unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
0186     } sync;
0187   } u1;
0188   unsigned char     reserved4[2];
0189   unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
0190   unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
0191   union {
0192     struct {
0193       unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
0194     } w;
0195     struct {
0196       unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
0197       unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
0198     } b;
0199   } u2;
0200   unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
0201   unsigned char     reserved5[2];
0202   union {
0203     struct {
0204       unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
0205     } async;
0206     struct {
0207       unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
0208     } sync;
0209   } u3;
0210   union {
0211     struct {
0212       unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
0213     } w;
0214     struct {
0215       unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
0216       unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
0217     } b;
0218   } u4;
0219   unsigned char     reserved6[2];
0220   unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
0221   unsigned char     reserved7;
0222   unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
0223   unsigned char     reserved8[7];
0224   unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
0225   unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
0226   unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
0227   unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
0228   unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
0229   unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
0230   unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
0231   unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
0232   unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
0233   unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
0234   unsigned short    reserved9;
0235   unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
0236   unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
0237   unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
0238   unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
0239   unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
0240   unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
0241   unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
0242   unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
0243   unsigned short    reserved10;
0244   unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
0245   unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
0246   unsigned char     reserved11[32];
0247   unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
0248   unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
0249   unsigned char     reserved12[2];
0250   unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
0251   unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
0252   unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
0253   union {
0254     struct {
0255       unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
0256     } w;
0257     struct {
0258       unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
0259       unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
0260     } b;
0261   } u5;
0262   unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
0263   unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
0264   unsigned char     reserved13[2];
0265   unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
0266   unsigned char     reserved14[49];
0267   unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
0268   unsigned char     reserved15[2];
0269   unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
0270   unsigned char     reserved16[4];
0271   unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
0272   unsigned char     reserved17[2];
0273   unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
0274   unsigned char     reserved18[10];
0275   unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
0276   unsigned char     reserved19[3];
0277   unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
0278   unsigned char     reserved20[3];
0279   unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
0280   unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
0281   unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
0282   unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
0283   unsigned char     stk;            /* 0xFFF450E2 - Stack */
0284   unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
0285   unsigned char     reserved21[8];
0286   unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
0287   unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
0288   unsigned char     car;            /* 0xFFF450EE - Channel Access */
0289   unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
0290   unsigned char     reserved22[6];
0291   unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
0292   unsigned char     reserved23;
0293   unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
0294 } cd2401_regs;
0295 
0296 /*
0297  *  Base address of the CD2401.
0298  *  This is not configurable in the MVME167.
0299  */
0300 #define cd2401          ((cd2401_regs * const) 0xFFF45000)
0301 
0302 /* CD2401 is clocked at 20 MHz */
0303 #define CD2401_CLK_RATE 20000000
0304 
0305 /* BSP-wide functions */
0306 
0307 rtems_isr_entry set_vector(
0308   rtems_isr_entry     handler,
0309   rtems_vector_number vector,
0310   int                 type
0311 );
0312 
0313 #ifdef M167_INIT
0314 #undef EXTERN
0315 #define EXTERN
0316 #else
0317 #undef EXTERN
0318 #define EXTERN extern
0319 #endif
0320 
0321 extern void *M68Kvec[];   /* vector table address */
0322 
0323 #ifdef __cplusplus
0324 }
0325 #endif
0326 
0327 /** @} */
0328 
0329 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.3.7 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!