mvme147s/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This routine does the bulk of the system initialization.
0005  */
0006
0007 /*
0008  *  COPYRIGHT (c) 1989-1999.
0009  *  On-Line Applications Research Corporation (OAR).
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions
0013  * are met:
0014  * 1. Redistributions of source code must retain the above copyright
0015  *    notice, this list of conditions and the following disclaimer.
0016  * 2. Redistributions in binary form must reproduce the above copyright
0017  *    notice, this list of conditions and the following disclaimer in the
0018  *    documentation and/or other materials provided with the distribution.
0019  *
0020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0021  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0022  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0023  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0024  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0025  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0026  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0027  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0028  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0029  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0030  * POSSIBILITY OF SUCH DAMAGE.
0031  *
0032  *  MVME147 port for TNI - Telecom Bretagne
0033  *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
0034  *  May 1996
0035  */
0036
0037 #include <bsp.h>
0038 #include <bsp/bootcard.h>
0039
0040 void bsp_start( void )
0041 {
0042   rtems_isr_entry       *monitors_vector_table;
0043   int                   index;
0044   uint8_t               node_number;
0045
0046   monitors_vector_table = (rtems_isr_entry *)0;   /* 147Bug Vectors are at 0 */
0047   m68k_set_vbr( monitors_vector_table );
0048
0049   for ( index=2 ; index<=255 ; index++ )
0050     M68Kvec[ index ] = monitors_vector_table[ 32 ];
0051
0052   M68Kvec[  2 ] = monitors_vector_table[  2 ];   /* bus error vector */
0053   M68Kvec[  4 ] = monitors_vector_table[  4 ];   /* breakpoints vector */
0054   M68Kvec[  9 ] = monitors_vector_table[  9 ];   /* trace vector */
0055   M68Kvec[ 47 ] = monitors_vector_table[ 47 ];   /* system call vector */
0056
0057   m68k_set_vbr( &M68Kvec );
0058
0059   pcc->int_base_vector = PCC_BASE_VECTOR & 0xF0;
0060   /* Set the PCC int vectors base */
0061
0062   /* VME shared memory configuration */
0063   /* Only the first node shares its top 128k DRAM */
0064
0065   vme_lcsr->utility_interrupt_vector = VME_BASE_VECTOR & 0xF8;
0066   /* Set VMEchip base interrupt vector */
0067   vme_lcsr->utility_interrupt_mask |= 0x02;
0068   /* Enable SIGLP interruption (see shm support) */
0069   pcc->general_purpose_control &= 0x10;
0070   /* Enable VME master interruptions */
0071
0072   if (vme_lcsr->system_controller & 0x01) {
0073     /* the board is system controller */
0074     vme_lcsr->system_controller = 0x08;
0075     /* Make VME access round-robin */
0076   }
0077
0078 #if defined(RTEMS_MULTIPROCESSING)
0079   node_number = (uint8_t)
0080     (rtems_configuration_get_user_multiprocessing_table()->node - 1) & 0xF;
0081 #else
0082    node_number = 1;
0083 #endif
0084   /* Get and store node ID, first node_number = 0 */
0085   vme_gcsr->board_identification = node_number;
0086
0087   vme_lcsr->gcsr_base_address = node_number;
0088   /* Setup the base address of this board's gcsr */
0089   vme_lcsr->timer_configuration = 0x6a;
0090   /* Enable VME time outs, maximum periods */
0091
0092   if (node_number == 0) {
0093     pcc->slave_base_address = 0x01;
0094     /* Set local DRAM base address on the VME bus to the DRAM size */
0095
0096     vme_lcsr->vme_bus_requester = 0x80;
0097     while (! (vme_lcsr->vme_bus_requester & 0x40));
0098     /* Get VMEbus mastership */
0099     vme_lcsr->slave_address_modifier = 0xfb;
0100     /* Share everything */
0101     vme_lcsr->slave_configuration = 0x80;
0102     /* Share local DRAM */
0103     vme_lcsr->vme_bus_requester = 0x0;
0104     /* release bus */
0105   } else {
0106     pcc->slave_base_address = 0;
0107     /* Set local DRAM base address on the VME bus to 0 */
0108
0109     vme_lcsr->vme_bus_requester = 0x80;
0110     while (! (vme_lcsr->vme_bus_requester & 0x40));
0111     /* Get VMEbus mastership */
0112     vme_lcsr->slave_address_modifier = 0x08;
0113     /* Share only the short adress range */
0114     vme_lcsr->slave_configuration = 0;
0115     /* Don't share local DRAM */
0116     vme_lcsr->vme_bus_requester = 0x0;
0117     /* release bus */
0118   }
0119
0120   vme_lcsr->master_address_modifier = 0;
0121   /* Automatically set the address modifier */
0122   vme_lcsr->master_configuration = 1;
0123   /* Disable D32 transfers : they don't work on my VMEbus rack */
0124
0125   rtems_cache_enable_instruction();
0126   rtems_cache_enable_data();
0127 }