mvme147s/include/bsp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsM68kMVME147s
0007  *
0008  * @brief Global BSP definitions.
0009  */
0010
0011 /*  bsp.h
0012  *
0013  *  This include file contains all MVME147 board IO definitions.
0014  *
0015  *  COPYRIGHT (c) 1989-1999.
0016  *  On-Line Applications Research Corporation (OAR).
0017  *
0018  * Redistribution and use in source and binary forms, with or without
0019  * modification, are permitted provided that the following conditions
0020  * are met:
0021  * 1. Redistributions of source code must retain the above copyright
0022  *    notice, this list of conditions and the following disclaimer.
0023  * 2. Redistributions in binary form must reproduce the above copyright
0024  *    notice, this list of conditions and the following disclaimer in the
0025  *    documentation and/or other materials provided with the distribution.
0026  *
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0028  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0029  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0030  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0031  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0032  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0033  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0034  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0035  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0036  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGE.
0038  *
0039  *  MVME147 port for TNI - Telecom Bretagne
0040  *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
0041  *  May 1996
0042  */
0043
0044 #ifndef LIBBSP_M68K_MVME147S_BSP_H
0045 #define LIBBSP_M68K_MVME147S_BSP_H
0046
0047 /**
0048  * @defgroup RTEMSBSPsM68kMVME147s MVME147s
0049  *
0050  * @ingroup RTEMSBSPsM68k
0051  *
0052  * @brief MVME147s Board Support Package.
0053  *
0054  * @{
0055  */
0056
0057 #include <bspopts.h>
0058 #include <bsp/default-initial-extension.h>
0059
0060 #include <rtems.h>
0061
0062 #ifdef __cplusplus
0063 extern "C" {
0064 #endif
0065
0066 /* Constants */
0067
0068 #define RAM_START 0x00007000
0069 #define RAM_END   0x003e0000
0070 #define DRAM_END  0x00400000
0071   /* We leave 128k for the shared memory */
0072
0073   /* MVME 147 Peripheral controller chip
0074      see MVME147/D1, 3.4 */
0075
0076 struct pcc_map {
0077   /* 32 bit registers */
0078   uint32_t         dma_table_address;            /* 0xfffe1000 */
0079   uint32_t         dma_data_address;             /* 0xfffe1004 */
0080   uint32_t         dma_bytecount;                /* 0xfffe1008 */
0081   uint32_t         dma_data_holding;             /* 0xfffe100c */
0082
0083   /* 16 bit registers */
0084   uint16_t         timer1_preload;               /* 0xfffe1010 */
0085   uint16_t         timer1_count;                 /* 0xfffe1012 */
0086   uint16_t         timer2_preload;               /* 0xfffe1014 */
0087   uint16_t         timer2_count;                 /* 0xfffe1016 */
0088
0089   /* 8 bit registers */
0090   uint8_t         timer1_int_control;            /* 0xfffe1018 */
0091   uint8_t         timer1_control;                /* 0xfffe1019 */
0092   uint8_t         timer2_int_control;            /* 0xfffe101a */
0093   uint8_t         timer2_control;                /* 0xfffe101b */
0094
0095   uint8_t         acfail_int_control;            /* 0xfffe101c */
0096   uint8_t         watchdog_control;              /* 0xfffe101d */
0097
0098   uint8_t         printer_int_control;           /* 0xfffe101e */
0099   uint8_t         printer_control;               /* 0xfffe102f */
0100
0101   uint8_t         dma_int_control;               /* 0xfffe1020 */
0102   uint8_t         dma_control;                   /* 0xfffe1021 */
0103   uint8_t         bus_error_int_control;         /* 0xfffe1022 */
0104   uint8_t         dma_status;                    /* 0xfffe1023 */
0105   uint8_t         abort_int_control;             /* 0xfffe1024 */
0106   uint8_t         table_address_function_code;   /* 0xfffe1025 */
0107   uint8_t         serial_port_int_control;       /* 0xfffe1026 */
0108   uint8_t         general_purpose_control;       /* 0xfffe1027 */
0109   uint8_t         lan_int_control;               /* 0xfffe1028 */
0110   uint8_t         general_purpose_status;        /* 0xfffe1029 */
0111   uint8_t         scsi_port_int_control;         /* 0xfffe102a */
0112   uint8_t         slave_base_address;            /* 0xfffe102b */
0113   uint8_t         software_int_1_control;        /* 0xfffe102c */
0114   uint8_t         int_base_vector;               /* 0xfffe102d */
0115   uint8_t         software_int_2_control;        /* 0xfffe102e */
0116   uint8_t         revision_level;                /* 0xfffe102f */
0117 };
0118
0119 #define pcc      ((volatile struct pcc_map * const) 0xfffe1000)
0120
0121 /* VME chip configuration registers */
0122
0123 struct vme_lcsr_map {
0124   uint8_t         unused_1;
0125   uint8_t         system_controller;             /* 0xfffe2001 */
0126   uint8_t         unused_2;
0127   uint8_t         vme_bus_requester;             /* 0xfffe2003 */
0128   uint8_t         unused_3;
0129   uint8_t         master_configuration;          /* 0xfffe2005 */
0130   uint8_t         unused_4;
0131   uint8_t         slave_configuration;           /* 0xfffe2007 */
0132   uint8_t         unused_5;
0133   uint8_t         timer_configuration;           /* 0xfffe2009 */
0134   uint8_t         unused_6;
0135   uint8_t         slave_address_modifier;        /* 0xfffe200b */
0136   uint8_t         unused_7;
0137   uint8_t         master_address_modifier;       /* 0xfffe200d */
0138   uint8_t         unused_8;
0139   uint8_t         interrupt_handler_mask;        /* 0xfffe200f */
0140   uint8_t         unused_9;
0141   uint8_t         utility_interrupt_mask;        /* 0xfffe2011 */
0142   uint8_t         unused_10;
0143   uint8_t         utility_interrupt_vector;      /* 0xfffe2013 */
0144   uint8_t         unused_11;
0145   uint8_t         interrupt_request;             /* 0xfffe2015 */
0146   uint8_t         unused_12;
0147   uint8_t         vme_bus_status_id;             /* 0xfffe2017 */
0148   uint8_t         unused_13;
0149   uint8_t         bus_error_status;              /* 0xfffe2019 */
0150   uint8_t         unused_14;
0151   uint8_t         gcsr_base_address;             /* 0xfffe201b */
0152 };
0153
0154 #define vme_lcsr      ((volatile struct vme_lcsr_map * const) 0xfffe2000)
0155
0156 struct vme_gcsr_map {
0157   uint8_t         unused_1;
0158   uint8_t         global_0;                      /* 0xfffe2021 */
0159   uint8_t         unused_2;
0160   uint8_t         global_1;                      /* 0xfffe2023 */
0161   uint8_t         unused_3;
0162   uint8_t         board_identification;          /* 0xfffe2025 */
0163   uint8_t         unused_4;
0164   uint8_t         general_purpose_0;             /* 0xfffe2027 */
0165   uint8_t         unused_5;
0166   uint8_t         general_purpose_1;             /* 0xfffe2029 */
0167   uint8_t         unused_6;
0168   uint8_t         general_purpose_2;             /* 0xfffe202b */
0169   uint8_t         unused_7;
0170   uint8_t         general_purpose_3;             /* 0xfffe202d */
0171   uint8_t         unused_8;
0172   uint8_t         general_purpose_4;             /* 0xfffe202f */
0173 };
0174
0175 #define vme_gcsr      ((volatile struct vme_gcsr_map * const) 0xfffe2020)
0176
0177 #define z8530 0xfffe3001
0178
0179 /* interrupt vectors - see MVME147/D1 4.14 */
0180 #define PCC_BASE_VECTOR        0x40 /* First user int */
0181 #define SCC_VECTOR             PCC_BASE_VECTOR+3
0182 #define TIMER_1_VECTOR         PCC_BASE_VECTOR+8
0183 #define TIMER_2_VECTOR         PCC_BASE_VECTOR+9
0184 #define SOFT_1_VECTOR          PCC_BASE_VECTOR+10
0185 #define SOFT_2_VECTOR          PCC_BASE_VECTOR+11
0186
0187 #define VME_BASE_VECTOR        0x50
0188 #define VME_SIGLP_VECTOR       VME_BASE_VECTOR+1
0189
0190 #define USE_CHANNEL_A   1                /* 1 = use channel A for console */
0191 #define USE_CHANNEL_B   0                /* 1 = use channel B for console */
0192
0193 #if (USE_CHANNEL_A == 1)
0194 #define CONSOLE_CONTROL  0xfffe3002
0195 #define CONSOLE_DATA     0xfffe3003
0196 #elif (USE_CHANNEL_B == 1)
0197 #define CONSOLE_CONTROL  0xfffe3000
0198 #define CONSOLE_DATA     0xfffe3001
0199 #endif
0200
0201 #define FOREVER       1                  /* infinite loop */
0202
0203 #ifdef M147_INIT
0204 #undef EXTERN
0205 #define EXTERN
0206 #else
0207 #undef EXTERN
0208 #define EXTERN extern
0209 #endif
0210
0211 extern rtems_isr_entry M68Kvec[];   /* vector table address */
0212
0213 /*
0214  * NOTE: Use the standard Clock driver entry
0215  */
0216
0217 /* functions */
0218
0219 rtems_isr_entry set_vector(
0220   rtems_isr_entry     handler,
0221   rtems_vector_number vector,
0222   int                 type
0223 );
0224
0225 #ifdef __cplusplus
0226 }
0227 #endif
0228
0229 /** @} */
0230
0231 #endif