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File indexing completed on 2025-05-11 08:23:48
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @ingroup RTEMSBSPsM68kMVME147 0007 * 0008 * @brief Global BSP definitions. 0009 */ 0010 0011 /* bsp.h 0012 * 0013 * This include file contains all MVME147 board IO definitions. 0014 * 0015 * COPYRIGHT (c) 1989-1999. 0016 * On-Line Applications Research Corporation (OAR). 0017 * 0018 * Redistribution and use in source and binary forms, with or without 0019 * modification, are permitted provided that the following conditions 0020 * are met: 0021 * 1. Redistributions of source code must retain the above copyright 0022 * notice, this list of conditions and the following disclaimer. 0023 * 2. Redistributions in binary form must reproduce the above copyright 0024 * notice, this list of conditions and the following disclaimer in the 0025 * documentation and/or other materials provided with the distribution. 0026 * 0027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 0028 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 0029 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 0030 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 0031 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 0032 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 0033 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 0034 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 0035 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 0036 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 0037 * POSSIBILITY OF SUCH DAMAGE. 0038 * 0039 * MVME147 port for TNI - Telecom Bretagne 0040 * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) 0041 * May 1996 0042 */ 0043 0044 #ifndef LIBBSP_M68K_MVME147_BSP_H 0045 #define LIBBSP_M68K_MVME147_BSP_H 0046 0047 /** 0048 * @defgroup RTEMSBSPsM68kMVME147 MVME147 0049 * 0050 * @ingroup RTEMSBSPsM68k 0051 * 0052 * @brief MVME147 Board Support Package. 0053 * 0054 * @{ 0055 */ 0056 0057 #include <bspopts.h> 0058 #include <bsp/default-initial-extension.h> 0059 0060 #include <rtems.h> 0061 0062 #ifdef __cplusplus 0063 extern "C" { 0064 #endif 0065 0066 /* Constants */ 0067 0068 #define RAM_START 0x00005000 0069 #define RAM_END 0x00400000 0070 0071 /* MVME 147 Peripheral controller chip 0072 see MVME147/D1, 3.4 */ 0073 0074 struct pcc_map { 0075 /* 32 bit registers */ 0076 uint32_t dma_table_address; /* 0xfffe1000 */ 0077 uint32_t dma_data_address; /* 0xfffe1004 */ 0078 uint32_t dma_bytecount; /* 0xfffe1008 */ 0079 uint32_t dma_data_holding; /* 0xfffe100c */ 0080 0081 /* 16 bit registers */ 0082 uint16_t timer1_preload; /* 0xfffe1010 */ 0083 uint16_t timer1_count; /* 0xfffe1012 */ 0084 uint16_t timer2_preload; /* 0xfffe1014 */ 0085 uint16_t timer2_count; /* 0xfffe1016 */ 0086 0087 /* 8 bit registers */ 0088 uint8_t timer1_int_control; /* 0xfffe1018 */ 0089 uint8_t timer1_control; /* 0xfffe1019 */ 0090 uint8_t timer2_int_control; /* 0xfffe101a */ 0091 uint8_t timer2_control; /* 0xfffe101b */ 0092 0093 uint8_t acfail_int_control; /* 0xfffe101c */ 0094 uint8_t watchdog_control; /* 0xfffe101d */ 0095 0096 uint8_t printer_int_control; /* 0xfffe101e */ 0097 uint8_t printer_control; /* 0xfffe102f */ 0098 0099 uint8_t dma_int_control; /* 0xfffe1020 */ 0100 uint8_t dma_control; /* 0xfffe1021 */ 0101 uint8_t bus_error_int_control; /* 0xfffe1022 */ 0102 uint8_t dma_status; /* 0xfffe1023 */ 0103 uint8_t abort_int_control; /* 0xfffe1024 */ 0104 uint8_t table_address_function_code; /* 0xfffe1025 */ 0105 uint8_t serial_port_int_control; /* 0xfffe1026 */ 0106 uint8_t general_purpose_control; /* 0xfffe1027 */ 0107 uint8_t lan_int_control; /* 0xfffe1028 */ 0108 uint8_t general_purpose_status; /* 0xfffe1029 */ 0109 uint8_t scsi_port_int_control; /* 0xfffe102a */ 0110 uint8_t slave_base_address; /* 0xfffe102b */ 0111 uint8_t software_int_1_control; /* 0xfffe102c */ 0112 uint8_t int_base_vector; /* 0xfffe102d */ 0113 uint8_t software_int_2_control; /* 0xfffe102e */ 0114 uint8_t revision_level; /* 0xfffe102f */ 0115 }; 0116 0117 #define pcc ((volatile struct pcc_map * const) 0xfffe1000) 0118 0119 #define z8530 0xfffe3001 0120 0121 /* interrupt vectors - see MVME146/D1 4.14 */ 0122 #define PCC_BASE_VECTOR 0x40 /* First user int */ 0123 #define SCC_VECTOR PCC_BASE_VECTOR+3 0124 #define TIMER_1_VECTOR PCC_BASE_VECTOR+8 0125 #define TIMER_2_VECTOR PCC_BASE_VECTOR+9 0126 #define SOFT_1_VECTOR PCC_BASE_VECTOR+10 0127 #define SOFT_2_VECTOR PCC_BASE_VECTOR+11 0128 0129 #define USE_CHANNEL_A 1 /* 1 = use channel A for console */ 0130 #define USE_CHANNEL_B 0 /* 1 = use channel B for console */ 0131 0132 #if (USE_CHANNEL_A == 1) 0133 #define CONSOLE_CONTROL 0xfffe3002 0134 #define CONSOLE_DATA 0xfffe3003 0135 #elif (USE_CHANNEL_B == 1) 0136 #define CONSOLE_CONTROL 0xfffe3000 0137 #define CONSOLE_DATA 0xfffe3001 0138 #endif 0139 0140 extern rtems_isr_entry M68Kvec[]; /* vector table address */ 0141 0142 /* functions */ 0143 0144 rtems_isr_entry set_vector( 0145 rtems_isr_entry handler, 0146 rtems_vector_number vector, 0147 int type 0148 ); 0149 0150 #ifdef __cplusplus 0151 } 0152 #endif 0153 0154 /** @} */ 0155 0156 #endif
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