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File indexing completed on 2025-05-11 08:23:48
0001 /* timer_isr() 0002 * 0003 * This routine provides the ISR for the PCC timer on the MVME147 0004 * board. The timer is set up to generate an interrupt at maximum 0005 * intervals. 0006 * 0007 * MVME147 port for TNI - Telecom Bretagne 0008 * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) 0009 * May 1996 0010 */ 0011 0012 #include <rtems/asm.h> 0013 0014 BEGIN_CODE 0015 0016 .set T1_CONTROL_REGISTER, 0xfffe1018 | timer 1 control register 0017 0018 PUBLIC (timerisr) 0019 SYM (timerisr): 0020 orb #0x80, T1_CONTROL_REGISTER | clear T1 int status bit 0021 addql #1, SYM (Ttimer_val) | increment timer value 0022 end_timerisr: 0023 rte 0024 0025 END_CODE 0026 END
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