mcf5329/start/cfinit.c

0001 /*********************************************************************
0002 * Initialisation Code for ColdFire MCF5329 Processor                 *
0003 **********************************************************************
0004  Generated by ColdFire Initialisation Utility 2.10.8
0005  Wed Jul 02 14:26:25 2008
0006
0007  MicroAPL Ltd makes no warranties in respect of the suitability
0008  of this code for any particular purpose, and accepts
0009  no liability for any loss arising out of its use. The person or
0010  persons making use of this file must make the final evaluation
0011  as to its suitability and correctness for a particular application.
0012
0013 */
0014
0015 /* External reference frequency is 16.0000 MHz
0016  Internal bus clock frequency = 80.00 MHz
0017  Processor core frequency = 240.00 MHz
0018 */
0019
0020 #include <bsp.h>
0021
0022 /* eDMA Transfer Control Descriptor definitions */
0023 #define  MCF_EDMA_TCD_W0(channel)            (*(vuint32 *)(0xFC045000+((channel)*0x20)))        /* Transfer Control Descriptor Word 0 */
0024 #define  MCF_EDMA_TCD_W1(channel)            (*(vuint32 *)(0xFC045004+((channel)*0x20)))        /* Transfer Control Descriptor Word 1 */
0025 #define  MCF_EDMA_TCD_W2(channel)            (*(vuint32 *)(0xFC045008+((channel)*0x20)))        /* Transfer Control Descriptor Word 2 */
0026 #define  MCF_EDMA_TCD_W3(channel)            (*(vuint32 *)(0xFC04500C+((channel)*0x20)))        /* Transfer Control Descriptor Word 3 */
0027 #define  MCF_EDMA_TCD_W4(channel)            (*(vuint32 *)(0xFC045010+((channel)*0x20)))        /* Transfer Control Descriptor Word 4 */
0028 #define  MCF_EDMA_TCD_W5(channel)            (*(vuint32 *)(0xFC045014+((channel)*0x20)))        /* Transfer Control Descriptor Word 5 */
0029 #define  MCF_EDMA_TCD_W6(channel)            (*(vuint32 *)(0xFC045018+((channel)*0x20)))        /* Transfer Control Descriptor Word 6 */
0030 #define  MCF_EDMA_TCD_W7(channel)            (*(vuint32 *)(0xFC04501C+((channel)*0x20)))        /* Transfer Control Descriptor Word 7 */
0031
0032 /* Function prototypes */
0033 void init_main(void);
0034 static void disable_interrupts(void);
0035 static void disable_watchdog_timer(void);
0036 static void disable_cache(void);
0037 extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
0038 static void init_cache(void);
0039 static void init_crossbar(void);
0040 extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
0041 static void init_eport(void);
0042 static void init_flexcan(void);
0043 static void init_dma_timers(void);
0044 static void init_interrupt_timers(void);
0045 static void init_real_time_clock(void);
0046 static void init_watchdog_timers(void);
0047 static void init_edma(void);
0048 static void init_pin_assignments(void);
0049 extern void init_sdram_controller(void)
0050   __attribute__ ((section(".ram_code")));
0051 static void init_interrupt_controller(void);
0052
0053 /*********************************************************************
0054 * init_main - Main entry point for initialisation code               *
0055 **********************************************************************/
0056 void init_main(void)
0057 {
0058   init_clock_config();
0059
0060   /* Disable interrupts, watchdog timer, cache */
0061   disable_interrupts();
0062   disable_watchdog_timer();
0063   disable_cache();
0064
0065   /* Initialise individual modules */
0066   init_cache();
0067   init_crossbar();
0068   init_chip_selects();
0069   init_eport();
0070   init_flexcan();
0071   init_dma_timers();
0072   init_interrupt_timers();
0073   init_real_time_clock();
0074   init_watchdog_timers();
0075   init_edma();
0076   init_pin_assignments();
0077
0078   /* Initialise SDRAM controller (must be done after pin assignments) */
0079   init_sdram_controller();
0080
0081   /* Initialise interrupt controller */
0082   init_interrupt_controller();
0083 }
0084
0085 /*********************************************************************
0086 * disable_interrupts - Disable all interrupt sources                 *
0087 **********************************************************************/
0088 static void disable_interrupts(void)
0089 {
0090   vuint8 *p;
0091   int i;
0092
0093   /* Set ICR001-ICR063 to 0x0 */
0094   p = (vuint8 *) & MCF_INTC0_ICR1;
0095   for (i = 1; i <= 63; i++)
0096     *p++ = 0x0;
0097
0098   /* Set ICR100-ICR163 to 0x0 */
0099   p = (vuint8 *) & MCF_INTC1_ICR0;
0100   for (i = 100; i <= 163; i++)
0101     *p++ = 0x0;
0102 }
0103
0104 /*********************************************************************
0105 * disable_watchdog_timer - Disable system watchdog timer             *
0106 **********************************************************************/
0107 static void disable_watchdog_timer(void)
0108 {
0109   /* Disable Core Watchdog Timer */
0110   MCF_SCM_CWCR = 0;
0111 }
0112
0113 /*********************************************************************
0114 * disable_cache - Disable and invalidate cache                       *
0115 **********************************************************************/
0116 static void disable_cache(void)
0117 {
0118   __asm__ ("move.l   #0x01000000,%d0");
0119   __asm__ ("movec    %d0,%CACR");
0120 }
0121
0122 /*********************************************************************
0123 * init_clock_config - Clock Module                                   *
0124 **********************************************************************/
0125 void init_clock_config(void)
0126 {
0127   /* Clock module uses normal PLL mode with 16.0000 MHz external reference
0128      Bus clock frequency = 80.00 MHz
0129      Processor clock frequency = 3 x bus clock = 240.00 MHz
0130      Dithering disabled
0131    */
0132
0133   /* Check to see if the SDRAM has already been initialized
0134      by a run control tool. If it has, put SDRAM into self-refresh mode before
0135      initializing the PLL
0136    */
0137   if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
0138     MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
0139
0140   /* Temporarily switch to LIMP mode
0141      NOTE: Ensure that this code is not executing from SDRAM, since the
0142      SDRAM Controller is disabled in LIMP mode
0143    */
0144   MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
0145   MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
0146
0147   /* Configure the PLL settings */
0148   MCF_PLL_PODR = MCF_PLL_PODR_CPUDIV(0x2) | MCF_PLL_PODR_BUSDIV(0x6);
0149   MCF_PLL_PFDR = MCF_PLL_PFDR_MFD(0x78);
0150   MCF_PLL_PLLCR = 0;
0151   MCF_PLL_PMDR = 0;
0152
0153   /* Enable PLL and wait for lock */
0154   MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
0155   while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
0156
0157   /* From the Device Errata:
0158
0159      "After exiting LIMP mode, the value of 0x40000000 should be written
0160      to address 0xFC0B8080 before attempting to initialize the SDRAMC
0161      or exit the SDRAM from self-refresh mode."
0162    */
0163   *(vuint32 *) 0xfc0b8080 = 0x40000000;
0164
0165   /* If we put the SDRAM into self-refresh mode earlier, restore mode now */
0166   if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
0167     MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
0168 }
0169
0170 /*********************************************************************
0171 * init_cache - Unified (Instruction and Data) Cache                  *
0172 **********************************************************************/
0173 static void init_cache(void)
0174 {
0175   /* ACR0: Cache accesses to 32 MB memory region at address $40000000
0176      CACR: Don't cache accesses to the rest of memory
0177    */
0178   /*
0179    * Cache is enabled in bspstart.c
0180    */
0181 #if 0
0182   __asm__ ("move.l   #0xa0000600,%d0");
0183   __asm__ ("movec    %d0,%CACR");
0184 #endif
0185   __asm__ ("move.l   #0x4001c020,%d0");
0186   __asm__ ("movec    %d0,%ACR0");
0187   __asm__ ("move.l   #0x00000000,%d0");
0188   __asm__ ("movec    %d0,%ACR1");
0189 }
0190
0191 /*********************************************************************
0192 * init_crossbar - Cross-Bar Switch (XBS) Module                      *
0193 **********************************************************************/
0194 static void init_crossbar(void)
0195 {
0196   /* XBS settings for FlexBus/SDRAM Controller slave:
0197      Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
0198    */
0199   MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
0200     MCF_XBS_PRS_M5(0x4) |
0201     MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
0202   MCF_XBS_CRS1 = 0;
0203
0204   /* XBS settings for SRAM Backdoor slave:
0205      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
0206    */
0207   MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
0208     MCF_XBS_PRS_M5(0x4) |
0209     MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
0210   MCF_XBS_CRS4 = 0;
0211
0212   /* XBS settings for Cryptography Modules slave:
0213      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
0214    */
0215   MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
0216     MCF_XBS_PRS_M5(0x4) |
0217     MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
0218   MCF_XBS_CRS6 = 0;
0219
0220   /* XBS settings for On-chip Peripherals slave:
0221      Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
0222    */
0223   MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
0224     MCF_XBS_PRS_M5(0x4) |
0225     MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
0226   MCF_XBS_CRS7 = 0;
0227 }
0228
0229 /*********************************************************************
0230 * init_chip_selects - Chip Select Module (FlexBus)                   *
0231 **********************************************************************/
0232 void init_chip_selects(void)
0233 {
0234   /* Chip Select 1 disabled (CSMR1[V] = 0) */
0235   MCF_FBCS1_CSMR = 0;
0236
0237   /* Chip Select 2 disabled (CSMR2[V] = 0) */
0238   MCF_FBCS2_CSMR = 0;
0239
0240   /* Chip Select 3 disabled (CSMR3[V] = 0) */
0241   MCF_FBCS3_CSMR = 0;
0242
0243   /* Chip Select 4 disabled (CSMR4[V] = 0) */
0244   MCF_FBCS4_CSMR = 0;
0245
0246   /* Chip Select 5 disabled (CSMR5[V] = 0) */
0247   MCF_FBCS5_CSMR = 0;
0248
0249   /* Chip Select 0: 2 MB of Flash at base address $00000000
0250      Port size = 16 bits
0251      Assert chip select on first rising clock edge after address is asserted
0252      Generate internal transfer acknowledge after 7 wait states
0253      Address is held for 1 clock at end of read and write cycles
0254    */
0255   MCF_FBCS0_CSAR = 0;
0256   MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
0257     (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
0258   MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
0259 }
0260
0261 /*********************************************************************
0262 * init_eport - Edge Port Module (EPORT)                              *
0263 **********************************************************************/
0264 static void init_eport(void)
0265 {
0266   /* Pins 1-7 configured as GPIO inputs */
0267   MCF_EPORT_EPPAR = 0;
0268   MCF_EPORT_EPDDR = 0;
0269   MCF_EPORT_EPIER = 0;
0270 }
0271
0272 /*********************************************************************
0273 * init_flexcan - FlexCAN Module                                      *
0274 **********************************************************************/
0275 static void init_flexcan(void)
0276 {
0277   /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
0278   MCF_CAN_IMASK = 0;
0279   MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
0280   MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
0281   MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
0282   MCF_CAN_CANCTRL = 0;
0283   MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
0284     MCF_CAN_CANMCR_FRZ |
0285     MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
0286 }
0287
0288 /*********************************************************************
0289 * init_sdram_controller - SDRAM Controller                           *
0290 **********************************************************************/
0291 void init_sdram_controller(void)
0292 {
0293   /* Check to see if the SDRAM has already been initialized
0294      by a run control tool and skip if so
0295    */
0296   if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
0297     return;
0298
0299   /* Ensure that there is a delay from processor reset of the time recommended in
0300      the SDRAM data sheet (typically 100-200 microseconds) until the following
0301      code so that the SDRAM is ready for commands...
0302    */
0303
0304   /* SDRAM controller configured for Double-data rate (DDR) SDRAM
0305      Bus width = 16 bits
0306      SDRAM specification:
0307      SDRAM clock frequency = 80.00 MHz
0308      CASL = 2.5
0309      ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
0310      Write recovery time, tWR = 15.0 nanoseconds
0311      Precharge comand to ACTV command, tRP = 20.0 nanoseconds
0312      Auto refresh command period, tRFC = 75.0 nanoseconds
0313      Average periodic refresh interval, tREFI = 7.8 microseconds
0314    */
0315
0316   /* Memory block 0 enabled - 32 MBytes at address $40000000
0317      Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
0318    */
0319   MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
0320
0321   /* Memory block 1 disabled */
0322   MCF_SDRAMC_SDCS1 = 0;
0323
0324   /* Initialise SDCFG1 register with delay and timing values
0325      SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
0326      PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
0327    */
0328   MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
0329     MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
0330     MCF_SDRAMC_SDCFG1_RDLAT(0x7) |
0331     MCF_SDRAMC_SDCFG1_ACT2RW(0x2) |
0332     MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
0333     MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
0334
0335   /* Initialise SDCFG2 register with delay and timing values
0336      BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
0337    */
0338   MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
0339     MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
0340     MCF_SDRAMC_SDCFG2_BRD2WT(0x6) | MCF_SDRAMC_SDCFG2_BL(0x7);
0341
0342   /* Issue a Precharge All command */
0343   MCF_SDRAMC_SDCR = MCF_SDRAMC_SDCR_MODE_EN |
0344     MCF_SDRAMC_SDCR_CKE |
0345     MCF_SDRAMC_SDCR_DDR |
0346     MCF_SDRAMC_SDCR_MUX(0x1) |
0347     MCF_SDRAMC_SDCR_RCNT(0x8) | MCF_SDRAMC_SDCR_PS_16 | MCF_SDRAMC_SDCR_IPALL;
0348
0349   /* Write Extended Mode Register */
0350   MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_CMD;
0351
0352   /* Write Mode Register and Reset DLL */
0353   MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
0354     MCF_SDRAMC_SDMR_AD(0x163) | MCF_SDRAMC_SDMR_CMD;
0355
0356   /* Insert code here to pause for DLL lock time specified by memory... */
0357
0358   /* Issue a second Precharge All command */
0359   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
0360
0361   /* Refresh sequence...
0362      (check the number of refreshes required by the SDRAM manufacturer)
0363    */
0364   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
0365   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
0366
0367   /* Write Mode Register and clear the Reset DLL bit */
0368   MCF_SDRAMC_SDMR = MCF_SDRAMC_SDMR_BNKAD_LMR |
0369     MCF_SDRAMC_SDMR_AD(0x63) | MCF_SDRAMC_SDMR_CMD;
0370
0371   /* Enable automatic refresh and lock SDMR */
0372   MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
0373   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_REF |
0374     MCF_SDRAMC_SDCR_DQS_OE(0x8) | MCF_SDRAMC_SDCR_DQS_OE(0x4);
0375
0376 }
0377
0378 /*********************************************************************
0379 * init_dma_timers - DMA Timers                                       *
0380 **********************************************************************/
0381 static void init_dma_timers(void)
0382 {
0383   /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
0384   MCF_DTIM0_DTMR = 0;
0385   MCF_DTIM0_DTXMR = 0;
0386   MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0387
0388   /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
0389   MCF_DTIM1_DTMR = 0;
0390   MCF_DTIM1_DTXMR = 0;
0391   MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0392
0393   /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
0394   MCF_DTIM2_DTMR = 0;
0395   MCF_DTIM2_DTXMR = 0;
0396   MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0397
0398   /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
0399   MCF_DTIM3_DTMR = 0;
0400   MCF_DTIM3_DTXMR = 0;
0401   MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0402 }
0403
0404 /*********************************************************************
0405 * init_interrupt_timers - Programmable Interrupt Timers (PIT)        *
0406 **********************************************************************/
0407 static void init_interrupt_timers(void)
0408 {
0409   /* PIT0 disabled (PCSR0[EN]=0) */
0410   MCF_PIT0_PCSR = 0;
0411
0412   /* PIT1 disabled (PCSR1[EN]=0) */
0413   MCF_PIT1_PCSR = 0;
0414
0415   /* PIT2 disabled (PCSR2[EN]=0) */
0416   MCF_PIT2_PCSR = 0;
0417
0418   /* PIT3 disabled (PCSR3[EN]=0) */
0419   MCF_PIT3_PCSR = 0;
0420 }
0421
0422 /*********************************************************************
0423 * init_real_time_clock - Real-Time Clock (RTC)                       *
0424 **********************************************************************/
0425 static void init_real_time_clock(void)
0426 {
0427   /* Disable the RTC */
0428   MCF_RTC_CR = 0;
0429 }
0430
0431 /*********************************************************************
0432 * init_watchdog_timers - Watchdog Timers                             *
0433 **********************************************************************/
0434 static void init_watchdog_timers(void)
0435 {
0436   /* Watchdog Timer disabled (WCR[EN]=0)
0437      NOTE: WCR and WMR cannot be written again until after the
0438      processor is reset.
0439    */
0440   MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
0441   MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
0442
0443   /* Core watchdog timer disabled */
0444   MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
0445 }
0446
0447 /*********************************************************************
0448 * init_edma - eDMA Controller                                        *
0449 **********************************************************************/
0450 static void init_edma(void)
0451 {
0452   /* Associate eDMA channels 9-12 with SSI signals */
0453   MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
0454
0455   /* Configured for round-robin arbitration mode */
0456   MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
0457
0458   /* All error interrupts are disabled */
0459   MCF_EDMA_EEI = 0;
0460
0461   /* All DMA requests from peripherals are masked */
0462   MCF_EDMA_ERQ = 0;
0463 }
0464
0465 /*********************************************************************
0466 * init_interrupt_controller - Interrupt Controller                   *
0467 **********************************************************************/
0468 static void init_interrupt_controller(void)
0469 {
0470   /* No interrupt sources configured */
0471   MCF_INTC1_ICR0 = 0;
0472   MCF_INTC1_ICR1 = 0;
0473   MCF_INTC1_ICR3 = 0;
0474   MCF_INTC1_ICR4 = 0;
0475   MCF_INTC1_ICR5 = 0;
0476   MCF_INTC1_ICR6 = 0;
0477   MCF_INTC1_ICR7 = 0;
0478   MCF_INTC1_ICR8 = 0;
0479   MCF_INTC1_ICR9 = 0;
0480   MCF_INTC1_ICR10 = 0;
0481   MCF_INTC1_ICR11 = 0;
0482   MCF_INTC1_ICR12 = 0;
0483   MCF_INTC1_ICR13 = 0;
0484   MCF_INTC1_ICR14 = 0;
0485   MCF_INTC1_ICR15 = 0;
0486   MCF_INTC1_ICR16 = 0;
0487   MCF_INTC1_ICR17 = 0;
0488   MCF_INTC1_ICR18 = 0;
0489   MCF_INTC1_ICR19 = 0;
0490   MCF_INTC1_ICR40 = 0;
0491   MCF_INTC1_ICR41 = 0;
0492   MCF_INTC1_ICR42 = 0;
0493   MCF_INTC1_ICR43 = 0;
0494   MCF_INTC1_ICR44 = 0;
0495   MCF_INTC1_ICR45 = 0;
0496   MCF_INTC1_ICR46 = 0;
0497   MCF_INTC1_ICR47 = 0;
0498   MCF_INTC1_ICR48 = 0;
0499   MCF_INTC1_ICR49 = 0;
0500   MCF_INTC1_ICR50 = 0;
0501   MCF_INTC1_ICR51 = 0;
0502   MCF_INTC1_ICR52 = 0;
0503   MCF_INTC1_ICR53 = 0;
0504   MCF_INTC0_ICR1 = 0;
0505   MCF_INTC0_ICR2 = 0;
0506   MCF_INTC0_ICR3 = 0;
0507   MCF_INTC0_ICR4 = 0;
0508   MCF_INTC0_ICR5 = 0;
0509   MCF_INTC0_ICR6 = 0;
0510   MCF_INTC0_ICR7 = 0;
0511   MCF_INTC0_ICR8 = 0;
0512   MCF_INTC0_ICR9 = 0;
0513   MCF_INTC0_ICR10 = 0;
0514   MCF_INTC0_ICR11 = 0;
0515   MCF_INTC0_ICR12 = 0;
0516   MCF_INTC0_ICR13 = 0;
0517   MCF_INTC0_ICR14 = 0;
0518   MCF_INTC0_ICR15 = 0;
0519   MCF_INTC0_ICR16 = 0;
0520   MCF_INTC0_ICR17 = 0;
0521   MCF_INTC0_ICR18 = 0;
0522   MCF_INTC0_ICR19 = 0;
0523   MCF_INTC0_ICR20 = 0;
0524   MCF_INTC0_ICR21 = 0;
0525   MCF_INTC0_ICR22 = 0;
0526   MCF_INTC0_ICR23 = 0;
0527   MCF_INTC0_ICR24 = 0;
0528   MCF_INTC0_ICR25 = 0;
0529   MCF_INTC0_ICR26 = 0;
0530   MCF_INTC0_ICR27 = 0;
0531   MCF_INTC0_ICR28 = 0;
0532   MCF_INTC0_ICR30 = 0;
0533   MCF_INTC0_ICR31 = 0;
0534   MCF_INTC0_ICR32 = 0;
0535   MCF_INTC0_ICR33 = 0;
0536   MCF_INTC0_ICR34 = 0;
0537   MCF_INTC0_ICR35 = 0;
0538   MCF_INTC0_ICR36 = 0;
0539   MCF_INTC0_ICR37 = 0;
0540   MCF_INTC0_ICR38 = 0;
0541   MCF_INTC0_ICR39 = 0;
0542   MCF_INTC0_ICR40 = 0;
0543   MCF_INTC0_ICR41 = 0;
0544   MCF_INTC0_ICR42 = 0;
0545   MCF_INTC0_ICR43 = 0;
0546   MCF_INTC0_ICR44 = 0;
0547   MCF_INTC0_ICR45 = 0;
0548   MCF_INTC0_ICR46 = 0;
0549   MCF_INTC0_ICR47 = 0;
0550   MCF_INTC0_ICR48 = 0;
0551   MCF_INTC0_ICR62 = 0;
0552   MCF_INTC0_IMRH = 0xffffffff;
0553   MCF_INTC0_IMRL = 0xffffffff;
0554   MCF_INTC1_IMRH = 0xffffffff;
0555   MCF_INTC1_IMRL = 0xffffffff;
0556 }
0557
0558 /*********************************************************************
0559 * init_pin_assignments - Pin Assignment and General Purpose I/O      *
0560 **********************************************************************/
0561 static void init_pin_assignments(void)
0562 {
0563   /* Pin assignments for port BUSCTL
0564      Pin BUSCTL3 : External bus output enable, /OE
0565      Pin BUSCTL2 : External bus transfer acknowledge, /TA
0566      Pin BUSCTL1 : External bus read/write, R/W
0567      Pin BUSCTL0 : External bus transfer start, /TS
0568    */
0569   MCF_GPIO_PDDR_BUSCTL = 0;
0570   MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
0571     MCF_GPIO_PAR_BUSCTL_PAR_TA |
0572     MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
0573
0574   /* Pin assignments for port BE
0575      Pin BE3 : External bus byte enable BW/BWE3
0576      Pin BE2 : External bus byte enable BW/BWE2
0577      Pin BE1 : External bus byte enable BW/BWE1
0578      Pin BE0 : External bus byte enable BW/BWE0
0579    */
0580   MCF_GPIO_PDDR_BE = 0;
0581   MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 |
0582     MCF_GPIO_PAR_BE_PAR_BE2 |
0583     MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
0584
0585   /* Pin assignments for port CS
0586      Pin CS5 : Flex bus chip select /FB_CS5
0587      Pin CS4 : Flex bus chip select /FB_CS4
0588      Pin CS3 : Flex bus chip select /FB_CS3
0589      Pin CS2 : Flex bus chip select /FB_CS2
0590      Pin CS1 : Flex bus chip select /FB_CS1
0591    */
0592   MCF_GPIO_PDDR_CS = 0;
0593   MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 |
0594     MCF_GPIO_PAR_CS_PAR_CS4 |
0595     MCF_GPIO_PAR_CS_PAR_CS3 |
0596     MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
0597
0598   /* Pin assignments for port FECI2C
0599      Pin FECI2C3 : FEC management data clock, FEC_MDC
0600      Pin FECI2C2 : FEC management data, FEC_MDIO
0601      Pin FECI2C1 : GPIO input
0602      Pin FECI2C0 : GPIO input
0603    */
0604   MCF_GPIO_PDDR_FECI2C = 0;
0605   MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) |
0606     MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
0607
0608   /* Pin assignments for ports FECH and FECL
0609      Pin FECH7 : FEC transmit clock, FEC_TXCLK
0610      Pin FECH6 : FEC transmit enable, FEC_TXEN
0611      Pin FECH5 : FEC transmit data 0, FEC_TXD0
0612      Pin FECH4 : FEC collision, FEC_COL
0613      Pin FECH3 : FEC receive clock, FEC_RXCLK
0614      Pin FECH2 : FEC receive data valid, FEC_RXDV
0615      Pin FECH1 : FEC receive data 0, FEC_RXD0
0616      Pin FECH0 : FEC carrier receive sense, FEC_CRS
0617      Pin FECL7 : FEC transmit data 3, FEC_TXD3
0618      Pin FECL6 : FEC transmit data 2, FEC_TXD2
0619      Pin FECL5 : FEC transmit data 1, FEC_TXD1
0620      Pin FECL4 : FEC transmit error, FEC_TXER
0621      Pin FECL3 : FEC receive data 3, FEX_RXD3
0622      Pin FECL2 : FEC receive data 2, FEX_RXD2
0623      Pin FECL1 : FEC receive data 1, FEX_RXD1
0624      Pin FECL0 : FEC receive error, FEC_RXER
0625    */
0626   MCF_GPIO_PDDR_FECH = 0;
0627   MCF_GPIO_PDDR_FECL = 0;
0628   MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) |
0629     MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
0630
0631   /* Pin assignments for port IRQ
0632      Pins are all used for EdgePort GPIO/IRQ
0633    */
0634   MCF_GPIO_PAR_IRQ = 0;
0635
0636   /* Pin assignments for port LCDDATAH
0637      Pins are all GPIO inputs
0638    */
0639   MCF_GPIO_PDDR_LCDDATAH = 0;
0640   MCF_GPIO_PAR_LCDDATA = 0;
0641
0642   /* Pin assignments for port LCDDATAM
0643      Port LCDDATAM pins are all GPIO inputs
0644    */
0645   MCF_GPIO_PDDR_LCDDATAM = 0;
0646
0647   /* Pin assignments for port LCDDATAL
0648      Port LCDDATAL pins are all GPIO inputs
0649    */
0650   MCF_GPIO_PDDR_LCDDATAL = 0;
0651
0652   /* Pin assignments for port LCDCTLH
0653      Pins are all GPIO inputs
0654    */
0655   MCF_GPIO_PDDR_LCDCTLH = 0;
0656   MCF_GPIO_PAR_LCDCTL = 0;
0657
0658   /* Pin assignments for port LCDCTLL
0659      Pins are all GPIO inputs
0660    */
0661   MCF_GPIO_PDDR_LCDCTLL = 0;
0662
0663   /* Pin assignments for port PWM
0664      Pins are all GPIO inputs
0665    */
0666   MCF_GPIO_PDDR_PWM = 0;
0667   MCF_GPIO_PAR_PWM = 0;
0668
0669   /* Pin assignments for port QSPI
0670      Pins are all GPIO inputs
0671    */
0672   MCF_GPIO_PDDR_QSPI = 0;
0673   MCF_GPIO_PAR_QSPI = 0;
0674
0675   /* Pin assignments for port SSI
0676      Pins are all GPIO inputs
0677    */
0678   MCF_GPIO_PDDR_SSI = 0;
0679   MCF_GPIO_PAR_SSI = 0;
0680
0681   /* Pin assignments for port TIMER
0682      Pins are all GPIO outputs
0683    */
0684   MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
0685     MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 |
0686     MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
0687   MCF_GPIO_PAR_TIMER = 0;
0688
0689   /* Pin assignments for port UART
0690      Pin UART7 : UART 1 clear-to-send, /U1CTS
0691      Pin UART6 : UART 1 request-to-send, /U1RTS
0692      Pin UART5 : UART 1 transmit data, U1TXD
0693      Pin UART4 : UART 1 receive data, U1RXD
0694      Pin UART3 : UART 0 clear-to-send, /U0CTS
0695      Pin UART2 : UART 0 request-to-send, /U0RTS
0696      Pin UART1 : UART 0 transmit data, U0TXD
0697      Pin UART0 : UART 0 receive data, U0RXD
0698    */
0699   MCF_GPIO_PDDR_UART = 0;
0700   MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) |
0701     MCF_GPIO_PAR_UART_PAR_URTS1(0x3) |
0702     MCF_GPIO_PAR_UART_PAR_URXD1(0x3) |
0703     MCF_GPIO_PAR_UART_PAR_UTXD1(0x3) |
0704     MCF_GPIO_PAR_UART_PAR_UCTS0 |
0705     MCF_GPIO_PAR_UART_PAR_URTS0 |
0706     MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0;
0707 }