mcf5329/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This routine does the bulk of the system initialisation.
0005  */
0006
0007 /*
0008  *  Author:
0009  *    David Fiddes, D.J@fiddes.surfaid.org
0010  *    http://www.calm.hw.ac.uk/davidf/coldfire/
0011  *
0012  *  COPYRIGHT (c) 1989-1998.
0013  *  On-Line Applications Research Corporation (OAR).
0014  *
0015  * Redistribution and use in source and binary forms, with or without
0016  * modification, are permitted provided that the following conditions
0017  * are met:
0018  * 1. Redistributions of source code must retain the above copyright
0019  *    notice, this list of conditions and the following disclaimer.
0020  * 2. Redistributions in binary form must reproduce the above copyright
0021  *    notice, this list of conditions and the following disclaimer in the
0022  *    documentation and/or other materials provided with the distribution.
0023  *
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0025  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0026  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0027  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0028  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0029  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0030  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0031  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0032  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0033  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0034  * POSSIBILITY OF SUCH DAMAGE.
0035  */
0036
0037 #include <bsp.h>
0038 #include <bsp/bootcard.h>
0039 #include <rtems/rtems/cache.h>
0040
0041 void bsp_start(void)
0042 {
0043   /* cfinit invalidates cache and sets acr registers */
0044
0045   /*
0046    * Enable the cache, we only need to enable the instruction cache as the
0047    * 532x has a unified data and instruction cache.
0048    */
0049   rtems_cache_enable_instruction();
0050 }
0051
0052 uint32_t bsp_get_CPU_clock_speed(void)
0053 {
0054   return 240000000;
0055 }
0056
0057 uint32_t bsp_get_BUS_clock_speed(void)
0058 {
0059   return 80000000;
0060 }