Warning, /bsps/m68k/mcf5329/gdb-init is written in an unsupported language. File is not indexed.
0001 #target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 -v -d
0002 target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0
0003
0004 #monitor set remote-debug 1
0005 #monitor set debug 1
0006 monitor bdm-reset
0007
0008 #
0009 # Show the exception stack frame.
0010 #
0011 define show-exception-sframe
0012 set $frsr = *(unsigned short *)((unsigned long)$sp + 2)
0013 set $frpc = *(unsigned long *)((unsigned long)$sp + 4)
0014 set $frfvo = *(unsigned short *)((unsigned long)$sp + 0)
0015 set $frcode = $frfvo >> 12
0016 set $frvect = ($frfvo & 0xFFF) >> 2
0017 set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3)
0018 printf "EXCEPTION -- SR:0x%X PC:0x%X FRAME:0x%x VECTOR:%d STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus
0019 if $frstatus == 4
0020 printf " Fault Type: Error on instruction fetch"
0021 end
0022 if $frstatus == 8
0023 printf " Fault Type: Error on operand write"
0024 end
0025 if $frstatus == 12
0026 printf " Fault Type: Error on operand read"
0027 end
0028 if $frstatus == 9
0029 printf " Fault Type: Attempted write to write-protected space"
0030 end
0031 end
0032
0033 # I have to do this as there seems to be a problem with me setting up the
0034 # chip selects. As far as I can tell, gdb is probing whats at the program
0035 # counter. It issues a 2 byte read (smallest instruction) followed by a
0036 # 4 byte read (depending on the result of the 2 byte read). gdb issues these
0037 # reads after each and every write that the .gdbinit script issues. This means
0038 # that as I'm initializing the chip selects the gdb reads can happen in an
0039 # invalid memory address and this causes a target bus error. For now I'm just
0040 # setting pc to 0, which seems to stop gdb from probing around to read
0041 # assembler. This lets me setup chip selects without error.
0042
0043 set $pc = 0x00000000
0044
0045 # Turn on RAMBAR1 at address 80000000
0046 monitor bdm-ctl-set 0x0C05 0x80000221
0047
0048 # Set VBR to the beginning of what will be SDRAM
0049 # VBR is an absolute CPU register
0050 monitor bdm-ctl-set 0x0801 0x40000000
0051
0052 # Disable watchdog timer
0053 set *((short*) 0xFC098000) = 0x0000
0054
0055 #Init CS0
0056 set *((long*) 0xFC008000) = 0x00000000
0057 set *((long*) 0xFC008008) = 0x00001FA0
0058 set *((long*) 0xFC008004) = 0x001F0001
0059
0060 # SDRAM Initialization
0061
0062 monitor delay-ms 100
0063
0064 # SDCS0
0065 set *((long*) 0xFC0B8110) = 0x40000018
0066 # SDCFG1
0067 set *((long*) 0xFC0B8008) = 0x53722730
0068 # SDCFG2
0069 set *((long*) 0xFC0B800C) = 0x56670000
0070
0071 # Issue PALL
0072 # SDCR
0073 set *((long*) 0xFC0B8004) = 0xE1092002
0074
0075 # Issue LEMR
0076 # SDMR
0077 set *((long*) 0xFC0B8000) = 0x40010000
0078
0079 # Write mode register
0080 # SDMR
0081 set *((long*) 0xFC0B8000) = 0x058D0000
0082
0083 # Wait a bit
0084 monitor delay-ms 600
0085
0086 # Issue PALL
0087 # SDCR
0088 set *((long*) 0xFC0B8004) = 0xE1092002
0089
0090 # Perform two refresh cycles
0091 # SDCR
0092 set *((long*) 0xFC0B8004) = 0xE1092004
0093 # SDCR
0094 set *((long*) 0xFC0B8004) = 0xE1092004
0095
0096 # SDMR
0097 set *((long*) 0xFC0B8000) = 0x018D0000
0098 # SDCR
0099 set *((long*) 0xFC0B8004) = 0x71092C00
0100
0101 # Wait a bit
0102 monitor delay-ms 100
0103
0104 load
