mcf5235/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  *  This routine does the bulk of the system initialization.
0005  */
0006
0007 /*
0008  *  COPYRIGHT (c) 1989-2008.
0009  *  On-Line Applications Research Corporation (OAR).
0010  *
0011  * Redistribution and use in source and binary forms, with or without
0012  * modification, are permitted provided that the following conditions
0013  * are met:
0014  * 1. Redistributions of source code must retain the above copyright
0015  *    notice, this list of conditions and the following disclaimer.
0016  * 2. Redistributions in binary form must reproduce the above copyright
0017  *    notice, this list of conditions and the following disclaimer in the
0018  *    documentation and/or other materials provided with the distribution.
0019  *
0020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0021  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0022  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0023  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0024  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0025  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0026  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0027  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0028  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0029  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0030  * POSSIBILITY OF SUCH DAMAGE.
0031  */
0032
0033 #include <bsp.h>
0034 #include <bsp/bootcard.h>
0035
0036 /*
0037  * Read/write copy of common cache
0038  *   Split I/D cache
0039  *   Allow CPUSHL to invalidate a cache line
0040  *   Enable buffered writes
0041  *   No burst transfers on non-cacheable accesses
0042  *   Default cache mode is *disabled* (cache only ACRx areas)
0043  */
0044 uint32_t cacr_mode = MCF5XXX_CACR_CENB | MCF5XXX_CACR_DBWE | MCF5XXX_CACR_DCM;
0045
0046 /*
0047  * Cacheable areas
0048  */
0049 extern char RamBase[];
0050 extern char RamSize[];
0051
0052 /*
0053  *  bsp_start
0054  *
0055  *  This routine does the bulk of the system initialisation.
0056  */
0057 void bsp_start( void )
0058 {
0059   /*
0060    * Invalidate the cache and disable it
0061    */
0062   m68k_set_acr0(0);
0063   m68k_set_acr1(0);
0064   m68k_set_cacr(MCF5XXX_CACR_CINV);
0065
0066   /*
0067    * Cache SDRAM
0068    */
0069   m68k_set_acr0(MCF5XXX_ACR_AB((uintptr_t)RamBase)   |
0070                 MCF5XXX_ACR_AM((uintptr_t)RamSize-1) |
0071                 MCF5XXX_ACR_EN                       |
0072                 MCF5XXX_ACR_BWE                      |
0073                 MCF5XXX_ACR_SM_IGNORE);
0074
0075   /*
0076    * Enable the cache
0077    */
0078   m68k_set_cacr(cacr_mode);
0079 }