mcf52235/start/cfinit.c

0001 /*********************************************************************
0002 * Initialisation Code for ColdFire MCF52235 Processor                *
0003 **********************************************************************
0004  Generated by ColdFire Initialisation Utility 2.10.8
0005  Fri May 23 14:39:00 2008
0006
0007  MicroAPL Ltd makes no warranties in respect of the suitability
0008  of this code for any particular purpose, and accepts
0009  no liability for any loss arising out of its use. The person or
0010  persons making use of this file must make the final evaluation
0011  as to its suitability and correctness for a particular application.
0012
0013 */
0014
0015 /* Processor/internal bus clocked at 60.00 MHz */
0016
0017 #include <bsp.h>
0018
0019 /* Additional register read/write macros (missing in headers) */
0020 #define MCF_CIM_CCON                   (*(vuint16*)(void*)(&__IPSBAR[0x00110004]))
0021
0022 /* Bit definitions and macros for MCF_CIM_CCON */
0023 #define MCF_CIM_CCON_SZEN              (0x00000040)
0024 #define MCF_CIM_CCON_PSTEN             (0x00000020)
0025 #define MCF_CIM_CCON_BME               (0x00000008)
0026 #define MCF_CIM_CCON_BMT(x)            (((x)&0x00000007)<<0)
0027
0028 /* Function prototypes */
0029 void init_main(void);
0030 static void disable_interrupts(void);
0031 static void disable_watchdog_timer(void);
0032 static void init_ipsbar(void);
0033 static void init_clock_config(void);
0034 static void init_sram(void);
0035 static void init_flash_controller(void);
0036 static void init_eport(void);
0037 static void init_flexcan(void);
0038 static void init_bus_config(void);
0039 static void init_power_management(void);
0040 static void init_dma_timers(void);
0041 static void init_gp_timer(void);
0042 static void init_interrupt_timers(void);
0043 static void init_real_time_clock(void);
0044 static void init_watchdog_timer(void);
0045 static void init_pin_assignments(void);
0046 static void init_interrupt_controller(void);
0047
0048 /*********************************************************************
0049 * init_main - Main entry point for initialisation code               *
0050 **********************************************************************/
0051 void init_main(void)
0052 {
0053   /* Mask all interrupts */
0054   __asm__ ("move.w   #0x2700,%sr");
0055
0056   /* Initialise base address of peripherals, VBR, etc */
0057   init_ipsbar();
0058   init_clock_config();
0059
0060   /* Disable interrupts and watchdog timer */
0061   disable_interrupts();
0062   disable_watchdog_timer();
0063
0064   /* Initialise individual modules */
0065   init_sram();
0066   init_flash_controller();
0067   init_eport();
0068   init_flexcan();
0069   init_bus_config();
0070   init_power_management();
0071   init_dma_timers();
0072   init_gp_timer();
0073   init_interrupt_timers();
0074   init_real_time_clock();
0075   init_watchdog_timer();
0076   init_pin_assignments();
0077
0078   /* Initialise interrupt controller */
0079   init_interrupt_controller();
0080 }
0081
0082 /*********************************************************************
0083 * disable_interrupts - Disable all interrupt sources                 *
0084 **********************************************************************/
0085 static void disable_interrupts(void)
0086 {
0087   vuint8 *p;
0088   int i;
0089
0090   /* Set ICR008-ICR063 to 0x0 */
0091   p = (vuint8 *) & MCF_INTC0_ICR8;
0092   for (i = 8; i <= 63; i++)
0093     *p++ = 0x0;
0094
0095   /* Set ICR108-ICR139 to 0x0 */
0096   p = (vuint8 *) & MCF_INTC1_ICR8;
0097   for (i = 108; i <= 139; i++)
0098     *p++ = 0x0;
0099 }
0100
0101 /*********************************************************************
0102 * disable_watchdog_timer - Disable system watchdog timer             *
0103 **********************************************************************/
0104 static void disable_watchdog_timer(void)
0105 {
0106   /* Disable Core Watchdog Timer */
0107   MCF_SCM_CWCR = 0;
0108 }
0109
0110 /*********************************************************************
0111 * init_clock_config - Clock Module                                   *
0112 **********************************************************************/
0113 static void init_clock_config(void)
0114 {
0115   /* Clock source is 25.0000 MHz external crystal
0116      Clock mode: Normal PLL mode
0117      Processor/Bus clock frequency = 60.00 MHz
0118      Loss of clock detection disabled
0119      Reset on loss of lock disabled
0120    */
0121
0122   /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
0123   MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_PFD(0x4);
0124
0125   /* Set RFD+1 to avoid frequency overshoot and wait for PLL to lock */
0126   MCF_CLOCK_SYNCR = 0x4103;
0127   while ((MCF_CLOCK_SYNSR & 0x08) == 0) ;
0128
0129   /* Set desired RFD=0 and MFD=4 and wait for PLL to lock */
0130   MCF_CLOCK_SYNCR = 0x4003;
0131   while ((MCF_CLOCK_SYNSR & 0x08) == 0) ;
0132   MCF_CLOCK_SYNCR = 0x4007;                       /* Switch to using PLL */
0133 }
0134
0135 /*********************************************************************
0136 * init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
0137 **********************************************************************/
0138 static void init_ipsbar(void)
0139 {
0140   /* Base address of internal peripherals (IPSBAR) = 0x40000000
0141
0142      Note: Processor powers up with IPS base address = 0x40000000
0143      Write to IPS base + 0x00000000 to set new value
0144    */
0145   *(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1;     /* +1 for Enable */
0146 }
0147
0148 /*********************************************************************
0149 * init_flash_controller - Flash Module                               *
0150 **********************************************************************/
0151 static void init_flash_controller(void)
0152 {
0153   /* Internal Flash module enabled, address = $00000000
0154      Flash state machine clock = 197.37 kHz
0155      All access types except CPU space/interrupt acknowledge cycle allowed
0156      Flash is Write-Protected
0157      All interrupts disabled
0158    */
0159   MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12);
0160   MCF_CFM_CFMMCR = 0;
0161
0162   /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
0163      This is a workaround for a hardware problem whereby a speculative
0164      access to the Flash occuring at the same time as an SRAM access
0165      can return corrupt data.
0166
0167      This workaround can result in a 4% - 9% performance penalty. Other workarounds
0168      are possible for certain applications.
0169
0170      For example, if you know that you will not be using the top 32 KB of the Flash
0171      you can place the SRAM base address at 0x20038000
0172
0173      See Device Errata for further details
0174    */
0175   __asm__ ("move.l   #0x00000161,%d0");
0176   __asm__ ("movec    %d0,%FLASHBAR");
0177 }
0178
0179 /*********************************************************************
0180 * init_eport - Edge Port Module (EPORT)                              *
0181 **********************************************************************/
0182 static void init_eport(void)
0183 {
0184   /* Pins 1-15 configured as GPIO inputs */
0185   MCF_EPORT_EPDDR0 = 0;
0186   MCF_EPORT_EPDDR1 = 0;
0187   MCF_EPORT_EPPAR0 = 0;
0188   MCF_EPORT_EPPAR1 = 0;
0189   MCF_EPORT_EPIER0 = 0;
0190   MCF_EPORT_EPIER1 = 0;
0191 }
0192
0193 /*********************************************************************
0194 * init_flexcan - FlexCAN Module                                      *
0195 **********************************************************************/
0196 static void init_flexcan(void)
0197 {
0198   /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
0199   MCF_CAN_IMASK = 0;
0200   MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
0201   MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
0202   MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
0203   MCF_CAN_CANCTRL = 0;
0204   MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
0205     MCF_CAN_CANMCR_FRZ |
0206     MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
0207 }
0208
0209 /*********************************************************************
0210 * init_bus_config - Internal Bus Arbitration                         *
0211 **********************************************************************/
0212 static void init_bus_config(void)
0213 {
0214   /* Use round robin arbitration scheme
0215      Assigned priorities (highest first):
0216      Ethernet
0217      DMA Controller
0218      ColdFire Core
0219      DMA bandwidth control disabled
0220      Park on last active bus master
0221    */
0222   MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
0223     MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16);
0224 }
0225
0226 /*********************************************************************
0227 * init_sram - On-chip SRAM                                           *
0228 **********************************************************************/
0229 static void init_sram(void)
0230 {
0231   /* Internal SRAM module enabled, address = $20000000
0232      DMA access to SRAM block disabled
0233      All access types (supervisor and user) allowed
0234    */
0235   __asm__ ("move.l   #0x20000001,%d0");
0236   __asm__ ("movec    %d0,%RAMBAR");
0237 }
0238
0239 /*********************************************************************
0240 * init_power_management - Power Management                           *
0241 **********************************************************************/
0242 static void init_power_management(void)
0243 {
0244   /* On executing STOP instruction, processor enters RUN mode
0245      Mode is exited when an interrupt of level 1 or higher is received
0246    */
0247   MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
0248   MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
0249 }
0250
0251 /*********************************************************************
0252 * init_dma_timers - DMA Timer Modules                                *
0253 **********************************************************************/
0254 static void init_dma_timers(void)
0255 {
0256   /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
0257   MCF_DTIM0_DTMR = MCF_DTIM_DTMR_CLK(0x1);
0258   MCF_DTIM0_DTXMR = 0;
0259   MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0260
0261   /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
0262   MCF_DTIM1_DTMR = 0;
0263   MCF_DTIM1_DTXMR = 0;
0264   MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0265
0266   /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
0267   MCF_DTIM2_DTMR = 0;
0268   MCF_DTIM2_DTXMR = 0;
0269   MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0270
0271   /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
0272   MCF_DTIM3_DTMR = MCF_DTIM_DTMR_CLK(0x1);
0273   MCF_DTIM3_DTXMR = 0;
0274   MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
0275 }
0276
0277 /*********************************************************************
0278 * init_gp_timer - General Purpose Timer (GPT) Module                 *
0279 **********************************************************************/
0280 static void init_gp_timer(void)
0281 {
0282   /*
0283      GPT disabled (GPTASCR1[GPTEN] = 0)
0284      Channel 0 configured as GPIO input
0285      Channel 1 configured as GPIO input
0286      Channel 2 configured as GPIO input
0287      Channel 3 configured as GPIO input
0288    */
0289   MCF_GPT_GPTSCR1 = 0;
0290   MCF_GPT_GPTDDR = 0;
0291 }
0292
0293 /**********************************************************************
0294 * init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
0295 ***********************************************************************/
0296 static void init_interrupt_timers(void)
0297 {
0298   /* PIT0 disabled (PCSR0[EN]=0) */
0299   MCF_PIT0_PCSR = 0;
0300
0301   /* PIT1 disabled (PCSR1[EN]=0) */
0302   MCF_PIT1_PCSR = 0;
0303 }
0304
0305 /*********************************************************************
0306 * init_real_time_clock - Real-Time Clock (RTC)                       *
0307 **********************************************************************/
0308 static void init_real_time_clock(void)
0309 {
0310   /* Disable the RTC */
0311   MCF_RTC_CR = 0;
0312 }
0313
0314 /*********************************************************************
0315 * init_watchdog_timer - Watchdog Timer                               *
0316 **********************************************************************/
0317 static void init_watchdog_timer(void)
0318 {
0319   /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
0320   MCF_SCM_CWCR = 0;
0321 }
0322
0323 /*********************************************************************
0324 * init_interrupt_controller - Interrupt Controller                   *
0325 **********************************************************************/
0326 static void init_interrupt_controller(void)
0327 {
0328   /* Configured interrupt sources in order of priority...
0329      Level 7:  External interrupt /IRQ7, (initially masked)
0330      Level 6:  External interrupt /IRQ6, (initially masked)
0331      Level 5:  External interrupt /IRQ5, (initially masked)
0332      Level 4:  External interrupt /IRQ4, (initially masked)
0333      Level 3:  External interrupt /IRQ3, (initially masked)
0334      Level 2:  External interrupt /IRQ2, (initially masked)
0335      Level 1:  External interrupt /IRQ1, (initially masked)
0336    */
0337   MCF_INTC0_ICR1 = 0;
0338   MCF_INTC0_ICR2 = 0;
0339   MCF_INTC0_ICR3 = 0;
0340   MCF_INTC0_ICR4 = 0;
0341   MCF_INTC0_ICR5 = 0;
0342   MCF_INTC0_ICR6 = 0;
0343   MCF_INTC0_ICR7 = 0;
0344   MCF_INTC0_ICR8 = 0;
0345   MCF_INTC0_ICR9 = 0;
0346   MCF_INTC0_ICR10 = 0;
0347   MCF_INTC0_ICR11 = 0;
0348   MCF_INTC0_ICR12 = 0;
0349   MCF_INTC0_ICR13 = 0;
0350   MCF_INTC0_ICR14 = 0;
0351   MCF_INTC0_ICR15 = 0;
0352   MCF_INTC0_ICR17 = 0;
0353   MCF_INTC0_ICR18 = 0;
0354   MCF_INTC0_ICR19 = 0;
0355   MCF_INTC0_ICR20 = 0;
0356   MCF_INTC0_ICR21 = 0;
0357   MCF_INTC0_ICR22 = 0;
0358   MCF_INTC0_ICR23 = 0;
0359   MCF_INTC0_ICR24 = 0;
0360   MCF_INTC0_ICR25 = 0;
0361   MCF_INTC0_ICR26 = 0;
0362   MCF_INTC0_ICR27 = 0;
0363   MCF_INTC0_ICR28 = 0;
0364   MCF_INTC0_ICR29 = 0;
0365   MCF_INTC0_ICR30 = 0;
0366   MCF_INTC0_ICR31 = 0;
0367   MCF_INTC0_ICR32 = 0;
0368   MCF_INTC0_ICR33 = 0;
0369   MCF_INTC0_ICR34 = 0;
0370   MCF_INTC0_ICR35 = 0;
0371   MCF_INTC0_ICR36 = 0;
0372   MCF_INTC0_ICR41 = 0;
0373   MCF_INTC0_ICR42 = 0;
0374   MCF_INTC0_ICR43 = 0;
0375   MCF_INTC0_ICR44 = 0;
0376   MCF_INTC0_ICR45 = 0;
0377   MCF_INTC0_ICR46 = 0;
0378   MCF_INTC0_ICR47 = 0;
0379   MCF_INTC0_ICR48 = 0;
0380   MCF_INTC0_ICR49 = 0;
0381   MCF_INTC0_ICR50 = 0;
0382   MCF_INTC0_ICR51 = 0;
0383   MCF_INTC0_ICR52 = 0;
0384   MCF_INTC0_ICR53 = 0;
0385   MCF_INTC0_ICR55 = 0;
0386   MCF_INTC0_ICR56 = 0;
0387   MCF_INTC0_ICR59 = 0;
0388   MCF_INTC0_ICR60 = 0;
0389   MCF_INTC0_ICR61 = 0;
0390   MCF_INTC0_ICR62 = 0;
0391   MCF_INTC0_ICR63 = 0;
0392   MCF_INTC1_ICR8 = 0;
0393   MCF_INTC1_ICR9 = 0;
0394   MCF_INTC1_ICR10 = 0;
0395   MCF_INTC1_ICR11 = 0;
0396   MCF_INTC1_ICR12 = 0;
0397   MCF_INTC1_ICR13 = 0;
0398   MCF_INTC1_ICR14 = 0;
0399   MCF_INTC1_ICR15 = 0;
0400   MCF_INTC1_ICR16 = 0;
0401   MCF_INTC1_ICR17 = 0;
0402   MCF_INTC1_ICR18 = 0;
0403   MCF_INTC1_ICR19 = 0;
0404   MCF_INTC1_ICR20 = 0;
0405   MCF_INTC1_ICR21 = 0;
0406   MCF_INTC1_ICR22 = 0;
0407   MCF_INTC1_ICR23 = 0;
0408   MCF_INTC1_ICR24 = 0;
0409   MCF_INTC1_ICR25 = 0;
0410   MCF_INTC1_ICR32 = 0;
0411   MCF_INTC1_ICR33 = 0;
0412   MCF_INTC1_ICR34 = 0;
0413   MCF_INTC1_ICR35 = 0;
0414   MCF_INTC1_ICR36 = 0;
0415   MCF_INTC1_ICR37 = 0;
0416   MCF_INTC1_ICR38 = 0;
0417   MCF_INTC1_ICR39 = 0;
0418   MCF_INTC0_IMRH = 0xffffffff;
0419   MCF_INTC0_IMRL = 0xfffffffe;
0420   MCF_INTC1_IMRH = 0xffffffff;
0421   MCF_INTC1_IMRL = 0xfffffffe;
0422 }
0423
0424 /*********************************************************************
0425 * init_pin_assignments - Pin Assignment and General Purpose I/O      *
0426 **********************************************************************/
0427 static void init_pin_assignments(void)
0428 {
0429   /* Pin assignments for port NQ
0430      Pins NQ7-NQ1 : EdgePort GPIO/IRQ
0431    */
0432   MCF_GPIO_DDRNQ = 0;
0433   MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
0434     MCF_GPIO_PNQPAR_PNQPAR6(0x1) |
0435     MCF_GPIO_PNQPAR_PNQPAR5(0x1) |
0436     MCF_GPIO_PNQPAR_PNQPAR4(0x1) |
0437     MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
0438     MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1);
0439
0440   /* Pin assignments for port GP
0441      Pins PG7-PG0 : EdgePort GPIO/IRQ
0442    */
0443   MCF_GPIO_DDRGP = 0;
0444   MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
0445     MCF_GPIO_PGPPAR_PGPPAR6 |
0446     MCF_GPIO_PGPPAR_PGPPAR5 |
0447     MCF_GPIO_PGPPAR_PGPPAR4 |
0448     MCF_GPIO_PGPPAR_PGPPAR3 |
0449     MCF_GPIO_PGPPAR_PGPPAR2 |
0450     MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0;
0451
0452   /* Pin assignments for port DD
0453      Pin DD7 : DDATA[3]
0454      Pin DD6 : DDATA[2]
0455      Pin DD5 : DDATA[1]
0456      Pin DD4 : DDATA[0]
0457      Pin DD3 : PST[3]
0458      Pin DD2 : PST[2]
0459      Pin DD1 : PST[1]
0460      Pin DD0 : PST[0]
0461      CCON[PSTEN] = 1 to enable PST/DDATA function
0462    */
0463   MCF_GPIO_DDRDD = 0;
0464   MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
0465     MCF_GPIO_PDDPAR_PDDPAR6 |
0466     MCF_GPIO_PDDPAR_PDDPAR5 |
0467     MCF_GPIO_PDDPAR_PDDPAR4 |
0468     MCF_GPIO_PDDPAR_PDDPAR3 |
0469     MCF_GPIO_PDDPAR_PDDPAR2 |
0470     MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0;
0471   MCF_CIM_CCON = 0x0021;
0472
0473   /* Pin assignments for port AN
0474      Pins are all GPIO inputs
0475    */
0476   MCF_GPIO_DDRAN = 0;
0477   MCF_GPIO_PANPAR = 0;
0478
0479   /* Pin assignments for port AS
0480      Pins are all GPIO inputs
0481    */
0482   MCF_GPIO_DDRAS = 0;
0483   MCF_GPIO_PASPAR = 0;
0484
0485   /* Pin assignments for port LD
0486      Pins are all GPIO inputs
0487    */
0488   MCF_GPIO_DDRLD = 0;
0489   MCF_GPIO_PLDPAR = 0;
0490
0491   /* Pin assignments for port QS
0492      Pins are all GPIO inputs
0493    */
0494   MCF_GPIO_DDRQS = 0;
0495   MCF_GPIO_PQSPAR = 0;
0496
0497   /* Pin assignments for port TA
0498      Pins are all GPIO inputs
0499    */
0500   MCF_GPIO_DDRTA = 0;
0501   MCF_GPIO_PTAPAR = 0;
0502
0503   /* Pin assignments for port TC
0504      Pins are all GPIO inputs
0505    */
0506   MCF_GPIO_DDRTC = 0;
0507   MCF_GPIO_PTCPAR = 0;
0508
0509   /* Pin assignments for port TD
0510      Pins are all GPIO inputs
0511    */
0512   MCF_GPIO_DDRTD = 0;
0513   MCF_GPIO_PTDPAR = 0;
0514
0515   /* Pin assignments for port UA
0516      Pin UA3 : UART 0 clear-to-send, UCTS0
0517      Pin UA2 : UART 0 request-to-send, URTS0
0518      Pin UA1 : UART 0 receive data, URXD0
0519      Pin UA0 : UART 0 transmit data, UTXD0
0520    */
0521   MCF_GPIO_DDRUA = 0;
0522   MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
0523     MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
0524     MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1);
0525
0526   /* Pin assignments for port UB
0527      Pin UB3 : UART 1 clear-to-send, UCTS1
0528      Pin UB2 : UART 1 request-to-send, URTS1
0529      Pin UB1 : UART 1 receive data, URXD1
0530      Pin UB0 : UART 1 transmit data, UTXD1
0531    */
0532   MCF_GPIO_DDRUB = 0;
0533   MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
0534     MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
0535     MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1);
0536
0537   /* Pin assignments for port UC
0538      Pin UC3 : UART 2 clear-to-send, UCTS2
0539      Pin UC2 : UART 2 request-to-send, URTS2
0540      Pin UC1 : UART 2 receive data, URXD2
0541      Pin UC0 : UART 2 transmit data, UTXD2
0542    */
0543   MCF_GPIO_DDRUC = 0;
0544   MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |
0545     MCF_GPIO_PUCPAR_PUCPAR2 |
0546     MCF_GPIO_PUCPAR_PUCPAR1 | MCF_GPIO_PUCPAR_PUCPAR0;
0547
0548   /* Configure drive strengths */
0549   MCF_GPIO_PDSRH = 0;
0550   MCF_GPIO_PDSRL = 0;
0551
0552   /* Configure Wired-OR register */
0553   MCF_GPIO_PWOR = 0;
0554 }