mcf5206elite/start/init5206e.c

0001 /*
0002  *  MCF5206e hardware startup routines
0003  *
0004  *  This is where the real hardware setup is done. A minimal stack
0005  *  has been provided by the start.S code. No normal C or RTEMS
0006  *  functions can be called from here.
0007  *
0008  *  This initialization code based on hardware settings of dBUG
0009  *  monitor. This must be changed if you like to run it immediately
0010  *  after reset.
0011  */
0012
0013 /*
0014  *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
0015  *  Author: Victor V. Vengerov <vvv@oktet.ru>
0016  *
0017  *  Based on work:
0018  *  Author:
0019  *    David Fiddes, D.J@fiddes.surfaid.org
0020  *    http://www.calm.hw.ac.uk/davidf/coldfire/
0021  *
0022  *  COPYRIGHT (c) 1989-1998.
0023  *  On-Line Applications Research Corporation (OAR).
0024  *
0025  *  The license and distribution terms for this file may be
0026  *  found in the file LICENSE in this distribution or at
0027  *  http://www.rtems.org/license/LICENSE.
0028  */
0029
0030 #include <rtems.h>
0031 #include <bsp.h>
0032 #include "mcf5206/mcf5206e.h"
0033
0034 extern void CopyDataClearBSSAndStart(unsigned long ramsize);
0035 extern void INTERRUPT_VECTOR(void);
0036
0037 #define m68k_set_srambar( _rambar0 ) \
0038   __asm__ volatile (  "movec %0,%%rambar0\n\t" \
0039                   "nop\n\t" \
0040                   : : "d" (_rambar0) )
0041
0042 #define m68k_set_mbar( _mbar ) \
0043   __asm__ volatile (  "movec %0,%%mbar\n\t" \
0044                   "nop\n\t" \
0045                   : : "d" (_mbar) )
0046
0047 #define mcf5206e_enable_cache() \
0048   m68k_set_cacr( MCF5206E_CACR_CENB )
0049
0050 #define mcf5206e_disable_cache() \
0051   __asm__ volatile (  "nop\n\t"    \
0052                   "movec %0,%%cacr\n\t" \
0053                   "nop\n\t" \
0054                   "movec %0,%%cacr\n\t" \
0055                   "nop\n\t" \
0056                   : : "d" (MCF5206E_CACR_CINV) )
0057
0058 /*
0059  * Initialize MCF5206e on-chip modules
0060  */
0061 void Init5206e(void)
0062 {
0063   /* Set Module Base Address register */
0064   m68k_set_mbar((MBAR & MCF5206E_MBAR_BA) | MCF5206E_MBAR_V);
0065
0066   /* Set System Protection Control Register (SYPCR):
0067    * Bus Monitor Enable, Bus Monitor Timing = 1024 clocks,
0068    * Software watchdog disabled
0069    */
0070   *MCF5206E_SYPCR(MBAR) = MCF5206E_SYPCR_BME |
0071               MCF5206E_SYPCR_BMT_1024;
0072
0073   /* Set Pin Assignment Register (PAR):
0074    *     Output Timer 0 (not DREQ) on *TOUT[0] / *DREQ[1]
0075    *     Input Timer 0 (not DREQ) on *TIN[0] / *DREQ[0]
0076    *     IRQ, not IPL
0077    *     UART2 RTS signal (not \RSTO)
0078    *     PST/DDATA (not PPIO)
0079    *     *WE (not CS/A)
0080    */
0081   *MCF5206E_PAR(MBAR) = MCF5206E_PAR_PAR9_TOUT |
0082             MCF5206E_PAR_PAR8_TIN0 |
0083             MCF5206E_PAR_PAR7_UART2 |
0084             MCF5206E_PAR_PAR6_IRQ |
0085             MCF5206E_PAR_PAR5_PST |
0086             MCF5206E_PAR_PAR4_DDATA |
0087             MCF5206E_PAR_WE0_WE1_WE2_WE3;
0088
0089   /* Set SIM Configuration Register (SIMR):
0090    * Disable software watchdog timer and bus timeout monitor when
0091    * internal freeze signal is asserted.
0092    */
0093   *MCF5206E_SIMR(MBAR) = MCF5206E_SIMR_FRZ0 | MCF5206E_SIMR_FRZ1;
0094
0095   /* Set Interrupt Mask Register: Disable all interrupts */
0096   *MCF5206E_IMR(MBAR) = 0xFFFF;
0097
0098   /* Assign Interrupt Control Registers as it is defined in bsp.h */
0099   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL1) =
0100               (BSP_INTLVL_AVEC1 << MCF5206E_ICR_IL_S) |
0101               (BSP_INTPRIO_AVEC1 << MCF5206E_ICR_IP_S) |
0102               MCF5206E_ICR_AVEC;
0103   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL2) =
0104               (BSP_INTLVL_AVEC2 << MCF5206E_ICR_IL_S) |
0105               (BSP_INTPRIO_AVEC2 << MCF5206E_ICR_IP_S) |
0106               MCF5206E_ICR_AVEC;
0107   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL3) =
0108               (BSP_INTLVL_AVEC3 << MCF5206E_ICR_IL_S) |
0109               (BSP_INTPRIO_AVEC3 << MCF5206E_ICR_IP_S) |
0110               MCF5206E_ICR_AVEC;
0111   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL4) =
0112               (BSP_INTLVL_AVEC4 << MCF5206E_ICR_IL_S) |
0113               (BSP_INTPRIO_AVEC4 << MCF5206E_ICR_IP_S) |
0114               MCF5206E_ICR_AVEC;
0115   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL5) =
0116               (BSP_INTLVL_AVEC5 << MCF5206E_ICR_IL_S) |
0117               (BSP_INTPRIO_AVEC5 << MCF5206E_ICR_IP_S) |
0118               MCF5206E_ICR_AVEC;
0119   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL6) =
0120               (BSP_INTLVL_AVEC6 << MCF5206E_ICR_IL_S) |
0121               (BSP_INTPRIO_AVEC6 << MCF5206E_ICR_IP_S) |
0122               MCF5206E_ICR_AVEC;
0123   *MCF5206E_ICR(MBAR,MCF5206E_INTR_EXT_IPL7) =
0124               (BSP_INTLVL_AVEC7 << MCF5206E_ICR_IL_S) |
0125               (BSP_INTPRIO_AVEC7 << MCF5206E_ICR_IP_S) |
0126               MCF5206E_ICR_AVEC;
0127   *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_1) =
0128               (BSP_INTLVL_TIMER1 << MCF5206E_ICR_IL_S) |
0129               (BSP_INTPRIO_TIMER1 << MCF5206E_ICR_IP_S) |
0130               MCF5206E_ICR_AVEC;
0131   *MCF5206E_ICR(MBAR,MCF5206E_INTR_TIMER_2) =
0132               (BSP_INTLVL_TIMER2 << MCF5206E_ICR_IL_S) |
0133               (BSP_INTPRIO_TIMER2 << MCF5206E_ICR_IP_S) |
0134               MCF5206E_ICR_AVEC;
0135   *MCF5206E_ICR(MBAR,MCF5206E_INTR_MBUS) =
0136               (BSP_INTLVL_MBUS << MCF5206E_ICR_IL_S) |
0137               (BSP_INTPRIO_MBUS << MCF5206E_ICR_IP_S) |
0138               MCF5206E_ICR_AVEC;
0139   *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_1) =
0140               (BSP_INTLVL_UART1 << MCF5206E_ICR_IL_S) |
0141               (BSP_INTPRIO_UART1 << MCF5206E_ICR_IP_S);
0142   *MCF5206E_ICR(MBAR,MCF5206E_INTR_UART_2) =
0143               (BSP_INTLVL_UART2 << MCF5206E_ICR_IL_S) |
0144               (BSP_INTPRIO_UART2 << MCF5206E_ICR_IP_S);
0145   *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_0) =
0146               (BSP_INTLVL_DMA0 << MCF5206E_ICR_IL_S) |
0147               (BSP_INTPRIO_DMA0 << MCF5206E_ICR_IP_S) |
0148               MCF5206E_ICR_AVEC;
0149   *MCF5206E_ICR(MBAR,MCF5206E_INTR_DMA_1) =
0150               (BSP_INTLVL_DMA1 << MCF5206E_ICR_IL_S) |
0151               (BSP_INTPRIO_DMA1 << MCF5206E_ICR_IP_S) |
0152               MCF5206E_ICR_AVEC;
0153
0154   /* Software Watchdog timer (not used now) */
0155   *MCF5206E_SWIVR(MBAR) = 0x0F; /* Uninitialized interrupt */
0156   *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY1;
0157   *MCF5206E_SWSR(MBAR) = MCF5206E_SWSR_KEY2;
0158
0159   /* Configuring Chip Selects */
0160   /* CS2: SRAM memory */
0161   *MCF5206E_CSAR(MBAR,2) = BSP_MEM_ADDR_ESRAM >> 16;
0162   *MCF5206E_CSMR(MBAR,2) = BSP_MEM_MASK_ESRAM;
0163   *MCF5206E_CSCR(MBAR,2) = MCF5206E_CSCR_WS1 |
0164                MCF5206E_CSCR_PS_32 |
0165                MCF5206E_CSCR_AA |
0166                MCF5206E_CSCR_EMAA |
0167                MCF5206E_CSCR_WR |
0168                MCF5206E_CSCR_RD;
0169
0170   /* CS3: GPIO on eLITE board */
0171   *MCF5206E_CSAR(MBAR,3) = BSP_MEM_ADDR_GPIO >> 16;
0172   *MCF5206E_CSMR(MBAR,3) = BSP_MEM_MASK_GPIO;
0173   *MCF5206E_CSCR(MBAR,3) = MCF5206E_CSCR_WS15 |
0174                MCF5206E_CSCR_PS_16 |
0175                MCF5206E_CSCR_AA |
0176                MCF5206E_CSCR_EMAA |
0177                MCF5206E_CSCR_WR |
0178                MCF5206E_CSCR_RD;
0179
0180   {
0181     uint32_t         *inttab = (uint32_t*)&INTERRUPT_VECTOR;
0182     uint32_t         *intvec = (uint32_t*)BSP_MEM_ADDR_ESRAM;
0183     register int i;
0184
0185     for (i = 0; i < 256; i++) {
0186       *(intvec++) = *(inttab++);
0187     }
0188   }
0189   m68k_set_vbr(BSP_MEM_ADDR_ESRAM);
0190
0191   /* CS0: Flash EEPROM */
0192   *MCF5206E_CSAR(MBAR,0) = BSP_MEM_ADDR_FLASH >> 16;
0193   *MCF5206E_CSCR(MBAR,0) = MCF5206E_CSCR_WS3 |
0194                MCF5206E_CSCR_AA |
0195                MCF5206E_CSCR_PS_16 |
0196                MCF5206E_CSCR_EMAA |
0197                MCF5206E_CSCR_WR |
0198                MCF5206E_CSCR_RD;
0199   *MCF5206E_CSMR(MBAR,0) = BSP_MEM_MASK_FLASH;
0200
0201   /*
0202    * Invalidate the cache and disable it
0203    */
0204   mcf5206e_disable_cache();
0205
0206   /*
0207    * Setup ACRs so that if cache turned on, periphal accesses
0208    * are not messed up.  (Non-cacheable, serialized)
0209    */
0210   m68k_set_acr0 ( 0
0211       | MCF5206E_ACR_BASE(BSP_MEM_ADDR_ESRAM)
0212       | MCF5206E_ACR_MASK(BSP_MEM_MASK_ESRAM)
0213       | MCF5206E_ACR_EN
0214       | MCF5206E_ACR_SM_ANY
0215   );
0216   m68k_set_acr1 ( 0
0217       | MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH)
0218       | MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH)
0219       | MCF5206E_ACR_EN
0220       | MCF5206E_ACR_SM_ANY
0221   );
0222
0223   mcf5206e_enable_cache();
0224
0225   /*
0226    * Copy data, clear BSS, switch stacks and call boot_card()
0227    */
0228   CopyDataClearBSSAndStart (BSP_MEM_SIZE_ESRAM - 0x400);
0229 }