m68k/include/mvme16x_hw.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  @ingroup m68k_mvme
0007  *
0008  *  @brief MVME16x IO definitions
0009  */
0010
0011 /*  mvme16x_hw.h
0012  *
0013  *  This include file contains all MVME16x board IO definitions
0014  *  and was derived by combining the common items in the
0015  *  mvme162 and mvme167 BSPs.
0016  *
0017  *  COPYRIGHT (c) 1989-2000.
0018  *  On-Line Applications Research Corporation (OAR).
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #ifndef __MVME16xHW_h
0043 #define __MVME16xHW_h
0044
0045 #include <bsp.h>
0046
0047 #ifdef __cplusplus
0048 extern "C" {
0049 #endif
0050
0051 /**
0052  *  @defgroup m68k_mvme MVME16X IO Support
0053  *
0054  *  @ingroup RTEMSBSPsM68kShared
0055  *
0056  *  @brief IO Support Package
0057  */
0058
0059 struct rtems_bsdnet_ifconfig;
0060 int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
0061 #define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
0062 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
0063
0064 /*
0065  *  This is NOT the base address of local RAM!
0066  *  This is the base local address of the VMEbus short I/O space. A local
0067  *  access to this space results in a A16 VMEbus I/O cycle. This base address
0068  *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
0069  *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
0070  *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
0071  *  GCSRs of other boards are accessible only through the VMEbus short I/O
0072  *  space. See pages 2-45 and 2-7.
0073  */
0074 #define BOARD_BASE_ADDRESS 0xFFFF0000
0075
0076 /*
0077  *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
0078  *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
0079  *  VMEbus short I/O space. It also should represent the group address of this
0080  *  MVME167! The group address is configurable, and must match the address
0081  *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
0082  *  recommended by Motorola. It is arbitrary.
0083  *  See pages 2-42 and 2-97 to 2-104.
0084  */
0085 #define GROUP_BASE_ADDRESS 0x0000CC00
0086
0087 /*
0088  *  Representation of the VMEchip2 LCSR.
0089  *  Could be made more detailed.
0090  */
0091
0092 typedef volatile struct {
0093   unsigned long     slave_adr[2];
0094   unsigned long     slave_trn[2];
0095   unsigned long     slave_ctl;
0096   unsigned long     mastr_adr[4];
0097   unsigned long     mastr_trn;
0098   unsigned long     mastr_att;
0099   unsigned long     mastr_ctl;
0100   unsigned long     dma_ctl_1;
0101   unsigned long     dma_ctl_2;
0102   unsigned long     dma_loc_cnt;
0103   unsigned long     dma_vme_cnt;
0104   unsigned long     dma_byte_cnt;
0105   unsigned long     dma_adr_cnt;
0106   unsigned long     dma_status;
0107   unsigned long     to_ctl;
0108   unsigned long     timer_cmp_1;
0109   unsigned long     timer_cnt_1;
0110   unsigned long     timer_cmp_2;
0111   unsigned long     timer_cnt_2;
0112   unsigned long     board_ctl;
0113   unsigned long     prescaler_cnt;
0114   unsigned long     intr_stat;
0115   unsigned long     intr_ena;
0116   unsigned long     intr_soft_set;
0117   unsigned long     intr_clear;
0118   unsigned long     intr_level[4];
0119   unsigned long     vector_base;
0120 } lcsr_regs;
0121
0122 /*
0123  *  Base address of VMEchip2 LCSR
0124  *  Not configurable on the MVME167.
0125  *  XXX what about 162?
0126  */
0127 #define lcsr        ((lcsr_regs * const) 0xFFF40000)
0128
0129 /*
0130  *  Vector numbers for the interrupts from the VMEchip2. Use the values
0131  *  "recommended" by Motorola.
0132  *  See pages 2-70 to 2-92, and table 2-3.
0133  */
0134
0135 /* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
0136 #define MASK_INT    0x00800000
0137
0138 /* The content of VBR0 corresponds to "X" in table 2-3 */
0139 #define VBR0        0x6
0140
0141 /* The content of VBR1 corresponds to "Y" in table 2-3 */
0142 #define VBR1        0x7
0143
0144 /*
0145  *  Representation of the PCCchip2
0146  */
0147 typedef volatile struct pccchip2_regs_ {
0148   unsigned char     chip_id;            /* 0xFFF42000 */
0149   unsigned char     chip_revision;      /* 0xFFF42001 */
0150   unsigned char     gen_control;        /* 0xFFF42002 */
0151   unsigned char     vector_base;        /* 0xFFF42003 */
0152   unsigned long     timer_cmp_1;        /* 0xFFF42004 */
0153   unsigned long     timer_cnt_1;        /* 0xFFF42008 */
0154   unsigned long     timer_cmp_2;        /* 0xFFF4200C */
0155   unsigned long     timer_cnt_2;        /* 0xFFF42010 */
0156   unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
0157   unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
0158   unsigned char     timer_ctl_2;        /* 0xFFF42016 */
0159   unsigned char     timer_ctl_1;        /* 0xFFF42017 */
0160   unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
0161   unsigned char     gpio_ctl;           /* 0xFFF42019 */
0162   unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
0163   unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
0164   unsigned char     SCC_error;          /* 0xFFF4201C */
0165   unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
0166   unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
0167   unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
0168   unsigned char     reserved1[3];
0169   unsigned char     modem_piack;        /* 0xFFF42023 */
0170   unsigned char     reserved2;
0171   unsigned char     tx_piack;           /* 0xFFF42025 */
0172   unsigned char     reserved3;
0173   unsigned char     rx_piack;           /* 0xFFF42027 */
0174   unsigned char     LANC_error;         /* 0xFFF42028 */
0175   unsigned char     reserved4;
0176   unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
0177   unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
0178   unsigned char     SCSI_error;         /* 0xFFF4202C */
0179   unsigned char     reserved5[2];
0180   unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
0181   unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
0182   unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
0183   unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
0184   unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
0185   unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
0186   unsigned char     reserved6;
0187   unsigned char     print_input_status; /* 0xFFF42036 */
0188   unsigned char     print_ctl;          /* 0xFFF42037 */
0189   unsigned char     chip_speed;         /* 0xFFF42038 */
0190   unsigned char     reserved7;
0191   unsigned char     print_data;         /* 0xFFF4203A */
0192   unsigned char     reserved8[3];
0193   unsigned char     int_level;          /* 0xFFF4203E */
0194   unsigned char     int_mask;           /* 0xFFF4203F */
0195 } pccchip2_regs;
0196
0197 /*
0198  *  Base address of the PCCchip2.
0199  *  This is not configurable in the MVME167.
0200  */
0201 #define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
0202
0203 /*
0204  *  On the MVME162, we have the mcchip and the pccchip2 on
0205  *  the 167.  They are similar but different enough where
0206  *  we have to reconcile them later.
0207  */
0208
0209 /*
0210  * Vector numbers for the interrupts from the PCCchip2. Use the values
0211  * "recommended" by Motorola.
0212  * See page 3-15.
0213  */
0214 #define PCCCHIP2_VBR    0x5
0215
0216 /*
0217  * The following registers are located in the VMEbus short
0218  * IO space and respond to address modifier codes $29 and $2D.
0219  * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
0220  */
0221
0222 typedef volatile struct {
0223   unsigned char       chip_revision;
0224   unsigned char       chip_id;
0225   unsigned char       lmsig;
0226   unsigned char       board_scr;
0227   unsigned short      gpr[6];
0228 } gcsr_regs;
0229
0230 #define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
0231 #define gcsr     ((gcsr_regs * const) 0xFFF40100)
0232
0233 /*
0234  *  Representation of 82596CA LAN controller: Memory Map
0235  */
0236 typedef volatile struct i82596_regs_ {
0237   unsigned short  port_lower;             /* 0xFFF46000 */
0238   unsigned short  port_upper;             /* 0xFFF46002 */
0239   unsigned long   chan_attn;              /* 0xFFF46004 */
0240 } i82596_regs;
0241
0242 /*
0243  *  Base address of the 82596.
0244  */
0245
0246 #define i82596    ((i82596_regs * const) 0xFFF46000)
0247
0248 /*
0249  *  Representation of initialization data in NVRAM
0250  */
0251
0252 #if defined(mvme167)
0253 typedef volatile struct nvram_config_ {
0254   unsigned char   cache_mode;          /* 0xFFFC0000 */
0255   unsigned char   console_mode;        /* 0xFFFC0001 */
0256   unsigned char   console_printk_port; /* 0xFFFC0002 */
0257   unsigned char   pad1;                /* 0xFFFC0003 */
0258   unsigned long   ipaddr;              /* 0xFFFC0004 */
0259   unsigned long   netmask;             /* 0xFFFC0008 */
0260   unsigned char   enaddr[6];           /* 0xFFFC000C */
0261   unsigned short  processor_id;        /* 0xFFFC0012 */
0262   unsigned long   rma_start;           /* 0xFFFC0014 */
0263   unsigned long   vma_start;           /* 0xFFFC0018 */
0264   unsigned long   ramsize;             /* 0xFFFC001C */
0265 } nvram_config;
0266
0267 /*
0268  *  Pointer to the base of User Area NVRAM
0269  */
0270
0271 #define nvram      ((nvram_config * const) 0xFFFC0000)
0272
0273 #endif
0274
0275 /*
0276  *  Flag to indicate if J1-4 is on (and parameters should be
0277  *  sought in User Area NVRAM)
0278  *
0279  *  NOTE:  If NVRAM has bad settings, the you want to disable this
0280  *         on the MVME167.
0281  */
0282 #if defined(mvme167)
0283   #define NVRAM_CONFIGURE \
0284     ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
0285 #else
0286   #define NVRAM_CONFIGURE 0
0287 #endif
0288
0289 #ifdef __cplusplus
0290 }
0291 #endif
0292
0293 #endif