include/mcf5272/mcf5272.h

0001 /*
0002  *  Coldfire MCF5272 definitions.
0003  *  Contents of this file based on information provided in
0004  *  Motorola MCF5272 User's Manual.
0005  *
0006  *  Copyright (C) 2004 Jay Monkman <jtm@lopingdog.com>
0007  *
0008  *  The license and distribution terms for this file may be
0009  *  found in the file LICENSE in this distribution or at
0010  *  http://www.rtems.org/license/LICENSE.
0011  */
0012
0013 #ifndef __MCF5272_H__
0014 #define __MCF5272_H__
0015
0016 #ifndef ASM
0017 #include <rtems.h>
0018 #endif
0019
0020 #define bit(x) (1 << (x))
0021
0022 #define MCF5272_SIM_BASE(mbar)    ((mbar) + 0x0000)
0023 #define MCF5272_INT_BASE(mbar)    ((mbar) + 0x0020)
0024 #define MCF5272_CS_BASE(mbar)     ((mbar) + 0x0040)
0025 #define MCF5272_GPIO_BASE(mbar)   ((mbar) + 0x0080)
0026 #define MCF5272_QSPI_BASE(mbar)   ((mbar) + 0x00A0)
0027 #define MCF5272_PWM_BASE(mbar)    ((mbar) + 0x00C0)
0028 #define MCF5272_DMAC_BASE(mbar)   ((mbar) + 0x00E0)
0029 #define MCF5272_UART0_BASE(mbar)  ((mbar) + 0x0100)
0030 #define MCF5272_UART1_BASE(mbar)  ((mbar) + 0x0140)
0031 #define MCF5272_SDRAMC_BASE(mbar) ((mbar) + 0x0180)
0032 #define MCF5272_TIMER_BASE(mbar)  ((mbar) + 0x0200)
0033 #define MCF5272_PLIC_BASE(mbar)   ((mbar) + 0x0300)
0034 #define MCF5272_ENET_BASE(mbar)   ((mbar) + 0x0840)
0035 #define MCF5272_USB_BASE(mbar)    ((mbar) + 0x1000)
0036
0037
0038 /* RAMBAR - SRAM Base Address Register */
0039 #define MCF5272_RAMBAR_BA  (0xfffff000) /* SRAM Base Address */
0040 #define MCF5272_RAMBAR_WP  (0x00000100) /* Write Protect */
0041 #define MCF5272_RAMBAR_CI  (0x00000020) /* CPU Space mask */
0042 #define MCF5272_RAMBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
0043 #define MCF5272_RAMBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
0044 #define MCF5272_RAMBAR_UC  (0x00000004) /* User Code Space Mask */
0045 #define MCF5272_RAMBAR_UD  (0x00000002) /* User Data Space Mask */
0046 #define MCF5272_RAMBAR_V   (0x00000001) /* Contents of RAMBAR are valid */
0047
0048 /* MBAR - Module Base Address Register */
0049 #define MCF5272_MBAR_BA  (0xffff0000) /* Base Address */
0050 #define MCF5272_MBAR_SC  (0x00000010) /* Supervisor Code Space Mask */
0051 #define MCF5272_MBAR_SD  (0x00000008) /* Supervisor Data Space Mask */
0052 #define MCF5272_MBAR_UC  (0x00000004) /* User Code Space Mask */
0053 #define MCF5272_MBAR_UD  (0x00000002) /* User Data Space Mask */
0054 #define MCF5272_MBAR_V   (0x00000001) /* Contents of MBAR are valid */
0055
0056 /* CACR - Cache Control Register */
0057 #define MCF5272_CACR_CENB  (0x80000000) /* Cache Enable */
0058 #define MCF5272_CACR_CPDI  (0x10000000) /* Disable CPUSHL Invalidation */
0059 #define MCF5272_CACR_CFRZ  (0x08000000) /* Cache Freeze */
0060 #define MCF5272_CACR_CINV  (0x01000000) /* Cache Invalidate */
0061 #define MCF5272_CACR_CEIB  (0x00000400) /* Cache Enable Noncacheable
0062                                            instruction bursting */
0063 #define MCF5272_CACR_DCM   (0x00000200) /* Default cache mode - noncacheable*/
0064 #define MCF5272_CACR_DBWE  (0x00000100) /* Default Buffered Write Enable */
0065 #define MCF5272_CACR_DWP   (0x00000020) /* Default Write Protection */
0066 #define MCF5272_CACR_CLNF  (0x00000003) /* Cache Line Fill */
0067
0068 /* ACRx - Cache Access Control Registers */
0069 #define MCF5272_ACR_BA        (0xff000000) /* Address Base */
0070 #define MCF5272_ACR_BAM       (0x00ff0000) /* Address Mask */
0071 #define MCF5272_ACR_EN        (0x00008000) /* Enable */
0072 #define MCF5272_ACR_SM_USR    (0x00000000) /* Match if user mode */
0073 #define MCF5272_ACR_SM_SVR    (0x00002000) /* Match if supervisor mode */
0074 #define MCF5272_ACR_SM_ANY    (0x00004000) /* Match Always */
0075 #define MCF527_ACR_CM         (0x00000040) /* Cache Mode (1 - noncacheable) */
0076 #define MCF5272_ACR_BWE       (0x00000020) /* Buffered Write Enable */
0077 #define MCF5272_ACR_WP        (0x00000004) /* Write Protect */
0078 #define MCF5272_ACR_BASE(base) ((base) & MCF5272_ACR_BA)
0079 #define MCF5272_ACR_MASK(mask) (((mask) >> 8) & MCF5272_ACR_BAM)
0080
0081
0082 #define MCF5272_ICR1_INT1_PI     (bit(31))
0083 #define MCF5272_ICR1_INT1_IPL(x) ((x) << 28)
0084 #define MCF5272_ICR1_INT1_MASK   ((7) << 28)
0085 #define MCF5272_ICR1_INT2_PI     (bit(27))
0086 #define MCF5272_ICR1_INT2_IPL(x) ((x) << 24)
0087 #define MCF5272_ICR1_INT2_MASK   ((7) << 24)
0088 #define MCF5272_ICR1_INT3_PI     (bit(23))
0089 #define MCF5272_ICR1_INT3_IPL(x) ((x) << 20)
0090 #define MCF5272_ICR1_INT3_MASK   ((7) << 20)
0091 #define MCF5272_ICR1_INT4_PI     (bit(19))
0092 #define MCF5272_ICR1_INT4_IPL(x) ((x) << 16)
0093 #define MCF5272_ICR1_INT4_MASK   ((7) << 16)
0094 #define MCF5272_ICR1_TMR0_PI     (bit(15))
0095 #define MCF5272_ICR1_TMR0_IPL(x) ((x) << 12)
0096 #define MCF5272_ICR1_TMR0_MASK   ((7) << 12)
0097 #define MCF5272_ICR1_TMR1_PI     (bit(11))
0098 #define MCF5272_ICR1_TMR1_IPL(x) ((x) << 8)
0099 #define MCF5272_ICR1_TMR1_MASK   ((7) << 8)
0100 #define MCF5272_ICR1_TMR2_PI     (bit(7))
0101 #define MCF5272_ICR1_TMR2_IPL(x) ((x) << 4)
0102 #define MCF5272_ICR1_TMR2_MASK   ((7) << 4)
0103 #define MCF5272_ICR1_TMR3_PI     (bit(3))
0104 #define MCF5272_ICR1_TMR3_IPL(x) ((x) << 0)
0105 #define MCF5272_ICR1_TMR3_MASK   ((7) << 0)
0106
0107 #define MCF5272_ICR3_USB4_PI     (bit(31))
0108 #define MCF5272_ICR3_USB4_IPL(x) ((x) << 28)
0109 #define MCF5272_ICR3_USB4_MASK   ((7) << 28)
0110 #define MCF5272_ICR3_USB5_PI     (bit(27))
0111 #define MCF5272_ICR3_USB5_IPL(x) ((x) << 24)
0112 #define MCF5272_ICR3_USB5_MASK   ((7) << 24)
0113 #define MCF5272_ICR3_USB6_PI     (bit(23))
0114 #define MCF5272_ICR3_USB6_IPL(x) ((x) << 20)
0115 #define MCF5272_ICR3_USB6_MASK   ((7) << 20)
0116 #define MCF5272_ICR3_USB7_PI     (bit(19))
0117 #define MCF5272_ICR3_USB7_IPL(x) ((x) << 16)
0118 #define MCF5272_ICR3_USB7_MASK   ((7) << 16)
0119 #define MCF5272_ICR3_DMA_PI     (bit(15))
0120 #define MCF5272_ICR3_DMA_IPL(x) ((x) << 12)
0121 #define MCF5272_ICR3_DMA_MASK   ((7) << 12)
0122 #define MCF5272_ICR3_ERX_PI     (bit(11))
0123 #define MCF5272_ICR3_ERX_IPL(x) ((x) << 8)
0124 #define MCF5272_ICR3_ERX_MASK   ((7) << 8)
0125 #define MCF5272_ICR3_ETX_PI     (bit(7))
0126 #define MCF5272_ICR3_ETX_IPL(x) ((x) << 4)
0127 #define MCF5272_ICR3_ETX_MASK   ((7) << 4)
0128 #define MCF5272_ICR3_ENTC_PI     (bit(3))
0129 #define MCF5272_ICR3_ENTC_IPL(x) ((x) << 0)
0130 #define MCF5272_ICR3_ENTC_MASK   ((7) << 0)
0131
0132
0133 #define MCF5272_USR_RB        (bit(7))
0134 #define MCF5272_USR_FE        (bit(6))
0135 #define MCF5272_USR_PE        (bit(5))
0136 #define MCF5272_USR_OE        (bit(4))
0137 #define MCF5272_USR_TXEMP     (bit(3))
0138 #define MCF5272_USR_TXRDY     (bit(2))
0139 #define MCF5272_USR_FFULL     (bit(1))
0140 #define MCF5272_USR_RXRDY     (bit(0))
0141
0142 #define MCF5272_TMR_PS_MASK     0xff00
0143 #define MCF5272_TMR_PS_SHIFT    8
0144 #define MCF5272_TMR_CE_DISABLE  (0 << 6)
0145 #define MCF5272_TMR_CE_RISING   (1 << 6)
0146 #define MCF5272_TMR_CE_FALLING  (2 << 6)
0147 #define MCF5272_TMR_CE_ANY      (3 << 6)
0148 #define MCF5272_TMR_OM          (bit(5))
0149 #define MCF5272_TMR_ORI         (bit(4))
0150 #define MCF5272_TMR_FRR         (bit(3))
0151 #define MCF5272_TMR_CLK_STOP    (0 << 1)
0152 #define MCF5272_TMR_CLK_MSTR    (1 << 1)
0153 #define MCF5272_TMR_CLK_MSTR16  (2 << 1)
0154 #define MCF5272_TMR_CLK_TIN     (3 << 1)
0155 #define MCF5272_TMR_RST         (bit(0))
0156 #define MCF5272_TER_REF (bit(1))
0157 #define MCF5272_TER_CAP (bit(0))
0158
0159 #define MCF5272_SCR_PRI         (bit(8))
0160 #define MCF5272_SCR_AR          (bit(7))
0161 #define MCF5272_SCR_SRST        (bit(6))
0162 #define MCF5272_SCR_BUSLOCK     (bit(3))
0163 #define MCF5272_SCR_HWR_128     (0)
0164 #define MCF5272_SCR_HWR_256     (1)
0165 #define MCF5272_SCR_HWR_512     (2)
0166 #define MCF5272_SCR_HWR_1024    (3)
0167 #define MCF5272_SCR_HWR_2048    (4)
0168 #define MCF5272_SCR_HWR_4096    (5)
0169 #define MCF5272_SCR_HWR_8192    (6)
0170 #define MCF5272_SCR_HWR_16384   (7)
0171
0172 #define MCF5272_SPR_ADC         (bit(15))
0173 #define MCF5272_SPR_WPV         (bit(15))
0174 #define MCF5272_SPR_SMV         (bit(15))
0175 #define MCF5272_SPR_PE          (bit(15))
0176 #define MCF5272_SPR_HWT         (bit(15))
0177 #define MCF5272_SPR_RPV         (bit(15))
0178 #define MCF5272_SPR_EXT         (bit(15))
0179 #define MCF5272_SPR_SUV         (bit(15))
0180 #define MCF5272_SPR_ADCEN       (bit(15))
0181 #define MCF5272_SPR_WPVEN       (bit(15))
0182 #define MCF5272_SPR_SMVEN       (bit(15))
0183 #define MCF5272_SPR_PEEN        (bit(15))
0184 #define MCF5272_SPR_HWTEN       (bit(15))
0185 #define MCF5272_SPR_RPVEN       (bit(15))
0186 #define MCF5272_SPR_EXTEN       (bit(15))
0187 #define MCF5272_SPR_SUVEN       (bit(15))
0188
0189 #define MCF5272_ENET_TX_RT      (bit(25))
0190 #define MCF5272_ENET_ETHERN_EN  (bit(1))
0191 #define MCF5272_ENET_RESET      (bit(0))
0192
0193 #define MCF5272_ENET_EIR_HBERR  (bit(31))
0194 #define MCF5272_ENET_EIR_BABR   (bit(30))
0195 #define MCF5272_ENET_EIR_BABT   (bit(29))
0196 #define MCF5272_ENET_EIR_GRA    (bit(28))
0197 #define MCF5272_ENET_EIR_TXF    (bit(27))
0198 #define MCF5272_ENET_EIR_TXB    (bit(26))
0199 #define MCF5272_ENET_EIR_RXF    (bit(25))
0200 #define MCF5272_ENET_EIR_RXB    (bit(24))
0201 #define MCF5272_ENET_EIR_MII    (bit(23))
0202 #define MCF5272_ENET_EIR_EBERR  (bit(22))
0203 #define MCF5272_ENET_EIR_UMINT  (bit(21))
0204
0205 #define MCF5272_ENET_RCR_PROM   (bit(3))
0206 #define MCF5272_ENET_RCR_MII    (bit(2))
0207 #define MCF5272_ENET_RCR_DRT    (bit(1))
0208 #define MCF5272_ENET_RCR_LOOP   (bit(0))
0209
0210 #define MCF5272_ENET_TCR_FDEN   (bit(2))
0211 #define MCF5272_ENET_TCR_HBC    (bit(1))
0212 #define MCF5272_ENET_TCR_GTS    (bit(0))
0213
0214
0215 #ifndef ASM
0216 typedef struct {
0217     volatile uint32_t mbar;       /* READ ONLY!! */
0218
0219     volatile uint16_t scr;
0220     volatile uint16_t _res0;
0221
0222     volatile uint16_t _res1;
0223     volatile uint16_t spr;
0224
0225     volatile uint32_t pmr;
0226
0227     volatile uint16_t _res2;
0228     volatile uint16_t alpr;
0229
0230     volatile uint32_t dir;
0231 } sim_regs_t;
0232
0233 typedef struct {
0234     volatile uint32_t icr1;
0235     volatile uint32_t icr2;
0236     volatile uint32_t icr3;
0237     volatile uint32_t icr4;
0238     volatile uint32_t isr;
0239     volatile uint32_t pitr;
0240     volatile uint32_t piwr;
0241     volatile uint8_t  _res0[3];
0242     volatile uint8_t  pivr;
0243 } intctrl_regs_t;
0244
0245 typedef struct {
0246     volatile uint32_t csbr0;
0247     volatile uint32_t csor0;
0248     volatile uint32_t csbr1;
0249     volatile uint32_t csor1;
0250     volatile uint32_t csbr2;
0251     volatile uint32_t csor2;
0252     volatile uint32_t csbr3;
0253     volatile uint32_t csor3;
0254     volatile uint32_t csbr4;
0255     volatile uint32_t csor4;
0256     volatile uint32_t csbr5;
0257     volatile uint32_t csor5;
0258     volatile uint32_t csbr6;
0259     volatile uint32_t csor6;
0260     volatile uint32_t csbr7;
0261     volatile uint32_t csor7;
0262 } chipsel_regs_t;
0263
0264 typedef struct {
0265     volatile uint32_t pacnt;
0266
0267     volatile uint16_t paddr;
0268     volatile uint16_t _res0;
0269
0270     volatile uint16_t _res1;
0271     volatile uint16_t padat;
0272
0273     volatile uint32_t pbcnt;
0274
0275     volatile uint16_t pbddr;
0276     volatile uint16_t _res2;
0277
0278     volatile uint16_t _res3;
0279     volatile uint16_t pbdat;
0280
0281     volatile uint16_t pcddr;
0282     volatile uint16_t _res4;
0283
0284     volatile uint16_t _res5;
0285     volatile uint16_t pcdat;
0286
0287     volatile uint32_t pdcnt;
0288 } gpio_regs_t;
0289
0290 typedef struct {
0291     volatile uint32_t qmr;
0292     volatile uint32_t qdlyr;
0293     volatile uint32_t qwr;
0294     volatile uint32_t qir;
0295     volatile uint32_t qar;
0296     volatile uint32_t qdr;
0297 } qspi_regs_t;
0298
0299 typedef struct {
0300     volatile uint8_t pwcr1;
0301     volatile uint8_t _res0[3];
0302
0303     volatile uint8_t pwcr2;
0304     volatile uint8_t _res1[3];
0305
0306     volatile uint8_t pwcr3;
0307     volatile uint8_t _res2[3];
0308
0309     volatile uint8_t pwwd1;
0310     volatile uint8_t _res3[3];
0311
0312     volatile uint8_t pwwd2;
0313     volatile uint8_t _res4[3];
0314
0315     volatile uint8_t pwwd3;
0316     volatile uint8_t _res5[3];
0317 } pwm_regs_t;
0318
0319 typedef struct {
0320     volatile uint32_t dcmr;
0321
0322     volatile uint16_t _res0;
0323     volatile uint16_t dcir;
0324
0325     volatile uint32_t dbcr;
0326
0327     volatile uint32_t dsar;
0328
0329     volatile uint32_t ddar;
0330 } dma_regs_t;
0331
0332 typedef struct {
0333     volatile uint8_t umr;              /* 0x000 */
0334     volatile uint8_t _res0[3];
0335
0336     volatile uint8_t ucsr;             /* 0x004 */
0337     volatile uint8_t _res2[3];
0338
0339     volatile uint8_t ucr;              /* 0x008 */
0340     volatile uint8_t _res3[3];
0341
0342     volatile uint8_t udata;            /* 0x00c */
0343     volatile uint8_t _res4[3];
0344
0345     volatile uint8_t uccr;             /* 0x010 */
0346     volatile uint8_t _res6[3];
0347
0348     volatile uint8_t uisr;             /* 0x014 */
0349     volatile uint8_t _res8[3];
0350
0351     volatile uint8_t ubg1;             /* 0x018 */
0352     volatile uint8_t _res10[3];
0353
0354     volatile uint8_t ubg2;             /* 0x01c */
0355     volatile uint8_t _res11[3];
0356
0357     volatile uint8_t uabr1;            /* 0x020 */
0358     volatile uint8_t _res12[3];
0359
0360     volatile uint8_t uabr2;            /* 0x024 */
0361     volatile uint8_t _res13[3];
0362
0363     volatile uint8_t utxfcsr;          /* 0x028 */
0364     volatile uint8_t _res14[3];
0365
0366     volatile uint8_t urxfcsr;          /* 0x02c */
0367     volatile uint8_t _res15[3];
0368
0369     volatile uint8_t ufpdn;            /* 0x030 */
0370     volatile uint8_t _res16[3];
0371
0372     volatile uint8_t uip;              /* 0x034 */
0373     volatile uint8_t _res17[3];
0374
0375     volatile uint8_t uop1;             /* 0x038 */
0376     volatile uint8_t _res18[3];
0377
0378     volatile uint8_t uop0;             /* 0x03c */
0379     volatile uint8_t _res19[3];
0380 } uart_regs_t;
0381
0382 typedef struct {
0383     volatile uint16_t tmr0;
0384     volatile uint16_t _res0;
0385
0386     volatile uint16_t trr0;
0387     volatile uint16_t _res1;
0388
0389     volatile uint16_t tcap0;
0390     volatile uint16_t _res2;
0391
0392     volatile uint16_t tcn0;
0393     volatile uint16_t _res3;
0394
0395     volatile uint16_t ter0;
0396     volatile uint16_t _res4;
0397
0398     volatile uint8_t  _res40[12];
0399
0400     volatile uint16_t tmr1;
0401     volatile uint16_t _res5;
0402
0403     volatile uint16_t trr1;
0404     volatile uint16_t _res6;
0405
0406     volatile uint16_t tcap1;
0407     volatile uint16_t _res7;
0408
0409     volatile uint16_t tcn1;
0410     volatile uint16_t _res8;
0411
0412     volatile uint16_t ter1;
0413     volatile uint16_t _res9;
0414
0415     volatile uint8_t  _res91[12];
0416
0417     volatile uint16_t tmr2;
0418     volatile uint16_t _res10;
0419
0420     volatile uint16_t trr2;
0421     volatile uint16_t _res11;
0422
0423     volatile uint16_t tcap2;
0424     volatile uint16_t _res12;
0425
0426     volatile uint16_t tcn2;
0427     volatile uint16_t _res13;
0428
0429     volatile uint16_t ter2;
0430     volatile uint16_t _res14;
0431
0432     volatile uint8_t  _res140[12];
0433
0434     volatile uint16_t tmr3;
0435     volatile uint16_t _res15;
0436
0437     volatile uint16_t trr3;
0438     volatile uint16_t _res16;
0439
0440     volatile uint16_t tcap3;
0441     volatile uint16_t _res17;
0442
0443     volatile uint16_t tcn3;
0444     volatile uint16_t _res18;
0445
0446     volatile uint16_t ter3;
0447     volatile uint16_t _res19;
0448
0449     volatile uint8_t  _res190[12];
0450
0451     volatile uint16_t wrrr;
0452     volatile uint16_t _res20;
0453
0454     volatile uint16_t wirr;
0455     volatile uint16_t _res21;
0456
0457     volatile uint16_t wcr;
0458     volatile uint16_t _res22;
0459
0460     volatile uint16_t wer;
0461     volatile uint16_t _res23;
0462 } timer_regs_t;
0463
0464 typedef struct {
0465     volatile uint32_t p0b1rr;
0466     volatile uint32_t p1b1rr;
0467     volatile uint32_t p2b1rr;
0468     volatile uint32_t p3b1rr;
0469     volatile uint32_t p0b2rr;
0470     volatile uint32_t p1b2rr;
0471     volatile uint32_t p2b2rr;
0472     volatile uint32_t p3b2rr;
0473
0474     volatile uint8_t  p0drr;
0475     volatile uint8_t  p1drr;
0476     volatile uint8_t  p2drr;
0477     volatile uint8_t  p3drr;
0478
0479     volatile uint32_t p0b1tr;
0480     volatile uint32_t p1b1tr;
0481     volatile uint32_t p2b1tr;
0482     volatile uint32_t p3b1tr;
0483     volatile uint32_t p0b2tr;
0484     volatile uint32_t p1b2tr;
0485     volatile uint32_t p2b2tr;
0486     volatile uint32_t p3b2tr;
0487
0488     volatile uint8_t  p0dtr;
0489     volatile uint8_t  p1dtr;
0490     volatile uint8_t  p2dtr;
0491     volatile uint8_t  p3dtr;
0492
0493     volatile uint16_t p0cr;
0494     volatile uint16_t p1cr;
0495     volatile uint16_t p2cr;
0496     volatile uint16_t p3cr;
0497     volatile uint16_t p0icr;
0498     volatile uint16_t p1icr;
0499     volatile uint16_t p2icr;
0500     volatile uint16_t p3icr;
0501     volatile uint16_t p0gmr;
0502     volatile uint16_t p1gmr;
0503     volatile uint16_t p2gmr;
0504     volatile uint16_t p3gmr;
0505     volatile uint16_t p0gmt;
0506     volatile uint16_t p1gmt;
0507     volatile uint16_t p2gmt;
0508     volatile uint16_t p3gmt;
0509
0510     volatile uint8_t  _res0;
0511     volatile uint8_t  pgmts;
0512     volatile uint8_t  pgmta;
0513     volatile uint8_t  _res1;
0514     volatile uint8_t  p0gcir;
0515     volatile uint8_t  p1gcir;
0516     volatile uint8_t  p2gcir;
0517     volatile uint8_t  p3gcir;
0518     volatile uint8_t  p0gcit;
0519     volatile uint8_t  p1gcit;
0520     volatile uint8_t  p2gcit;
0521     volatile uint8_t  p3gcit;
0522     volatile uint8_t  _res3[3];
0523     volatile uint8_t  pgcitsr;
0524     volatile uint8_t  _res4[3];
0525     volatile uint8_t  pdcsr;
0526
0527     volatile uint16_t p0psr;
0528     volatile uint16_t p1psr;
0529     volatile uint16_t p2psr;
0530     volatile uint16_t p3psr;
0531     volatile uint16_t pasr;
0532     volatile uint8_t  _res5;
0533     volatile uint8_t  plcr;
0534     volatile uint16_t _res6;
0535     volatile uint16_t pdrqr;
0536     volatile uint16_t p0sdr;
0537     volatile uint16_t p1sdr;
0538     volatile uint16_t p2sdr;
0539     volatile uint16_t p3sdr;
0540     volatile uint16_t _res7;
0541     volatile uint16_t pcsr;
0542 } plic_regs_t;
0543
0544 typedef struct {
0545     volatile uint32_t ecr;
0546     volatile uint32_t eir;
0547     volatile uint32_t eimr;
0548     volatile uint32_t ivsr;
0549     volatile uint32_t rdar;
0550     volatile uint32_t tdar;
0551     volatile uint32_t _res0[10];
0552     volatile uint32_t mmfr;
0553     volatile uint32_t mscr;
0554     volatile uint32_t _res1[17];
0555     volatile uint32_t frbr;
0556     volatile uint32_t frsr;
0557     volatile uint32_t _res2[4];
0558     volatile uint32_t tfwr;
0559     volatile uint32_t _res3[1];
0560     volatile uint32_t tfsr;
0561     volatile uint32_t _res4[21];
0562     volatile uint32_t rcr;
0563     volatile uint32_t mflr;
0564     volatile uint32_t _res5[14];
0565     volatile uint32_t tcr;
0566     volatile uint32_t _res6[158];
0567     volatile uint32_t malr;
0568     volatile uint32_t maur;
0569     volatile uint32_t htur;
0570     volatile uint32_t htlr;
0571     volatile uint32_t erdsr;
0572     volatile uint32_t etdsr;
0573     volatile uint32_t emrbr;
0574 /*    volatile uint8_t  fifo[448]; */
0575 } enet_regs_t;
0576
0577 typedef struct {
0578     volatile uint16_t _res0;
0579     volatile uint16_t fnr;
0580     volatile uint16_t _res1;
0581     volatile uint16_t fnmr;
0582     volatile uint16_t _res2;
0583     volatile uint16_t rfmr;
0584     volatile uint16_t _res3;
0585     volatile uint16_t rfmmr;
0586     volatile uint8_t  _res4[3];
0587     volatile uint8_t  far;
0588     volatile uint32_t asr;
0589     volatile uint32_t drr1;
0590     volatile uint32_t drr2;
0591     volatile uint16_t _res5;
0592     volatile uint16_t specr;
0593     volatile uint16_t _res6;
0594     volatile uint16_t ep0sr;
0595
0596     volatile uint32_t iep0cfg;
0597     volatile uint32_t oep0cfg;
0598     volatile uint32_t ep1cfg;
0599     volatile uint32_t ep2cfg;
0600     volatile uint32_t ep3cfg;
0601     volatile uint32_t ep4cfg;
0602     volatile uint32_t ep5cfg;
0603     volatile uint32_t ep6cfg;
0604     volatile uint32_t ep7cfg;
0605     volatile uint32_t ep0ctl;
0606
0607     volatile uint16_t _res7;
0608     volatile uint16_t ep1ctl;
0609     volatile uint16_t _res8;
0610     volatile uint16_t ep2ctl;
0611     volatile uint16_t _res9;
0612     volatile uint16_t ep3ctl;
0613     volatile uint16_t _res10;
0614     volatile uint16_t ep4ctl;
0615     volatile uint16_t _res11;
0616     volatile uint16_t ep5ctl;
0617     volatile uint16_t _res12;
0618     volatile uint16_t ep6ctl;
0619     volatile uint16_t _res13;
0620     volatile uint16_t ep7ctl;
0621
0622     volatile uint32_t ep0isr;
0623
0624     volatile uint16_t _res14;
0625     volatile uint16_t ep1isr;
0626     volatile uint16_t _res15;
0627     volatile uint16_t ep2isr;
0628     volatile uint16_t _res16;
0629     volatile uint16_t ep3isr;
0630     volatile uint16_t _res17;
0631     volatile uint16_t ep4isr;
0632     volatile uint16_t _res18;
0633     volatile uint16_t ep5isr;
0634     volatile uint16_t _res19;
0635     volatile uint16_t ep6isr;
0636     volatile uint16_t _res20;
0637     volatile uint16_t ep7isr;
0638
0639     volatile uint32_t ep0imr;
0640
0641     volatile uint16_t _res21;
0642     volatile uint16_t ep1imr;
0643     volatile uint16_t _res22;
0644     volatile uint16_t ep2imr;
0645     volatile uint16_t _res23;
0646     volatile uint16_t ep3imr;
0647     volatile uint16_t _res24;
0648     volatile uint16_t ep4imr;
0649     volatile uint16_t _res25;
0650     volatile uint16_t ep5imr;
0651     volatile uint16_t _res26;
0652     volatile uint16_t ep6imr;
0653     volatile uint16_t _res27;
0654     volatile uint16_t ep7imr;
0655
0656     volatile uint32_t ep0dr;
0657     volatile uint32_t ep1dr;
0658     volatile uint32_t ep2dr;
0659     volatile uint32_t ep3dr;
0660     volatile uint32_t ep4dr;
0661     volatile uint32_t ep5dr;
0662     volatile uint32_t ep6dr;
0663     volatile uint32_t ep7dr;
0664
0665     volatile uint16_t _res28;
0666     volatile uint16_t ep0dpr;
0667     volatile uint16_t _res29;
0668     volatile uint16_t ep1dpr;
0669     volatile uint16_t _res30;
0670     volatile uint16_t ep2dpr;
0671     volatile uint16_t _res31;
0672     volatile uint16_t ep3dpr;
0673     volatile uint16_t _res32;
0674     volatile uint16_t ep4dpr;
0675     volatile uint16_t _res33;
0676     volatile uint16_t ep5dpr;
0677     volatile uint16_t _res34;
0678     volatile uint16_t ep6dpr;
0679     volatile uint16_t _res35;
0680     volatile uint16_t ep7dpr;
0681 /*    uint8_t  ram[1024]; */
0682 } usb_regs_t;
0683
0684 extern intctrl_regs_t *g_intctrl_regs;
0685 extern chipsel_regs_t *g_chipsel_regs;
0686 extern gpio_regs_t *g_gpio_regs;
0687 extern qspi_regs_t *g_qspi_regs;
0688 extern pwm_regs_t *g_pwm_regs;
0689 extern dma_regs_t *g_dma_regs;
0690 extern uart_regs_t *g_uart0_regs;
0691 extern uart_regs_t *g_uart1_regs;
0692 extern timer_regs_t *g_timer_regs;
0693 extern plic_regs_t *g_plic_regs;
0694 extern enet_regs_t *g_enet_regs;
0695 extern usb_regs_t *g_usb_regs;
0696
0697 #endif /* ASM */
0698
0699 #endif /* __MCF5272_H__ */