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File indexing completed on 2025-05-11 08:23:45 

0001 /*
0002  * File:    mcf5223x.h
0003  * Purpose: Register and bit definitions
0004  */
0005 
0006 #ifndef __MCF5223x_H__
0007 #define __MCF5223x_H__
0008 
0009 typedef volatile unsigned char vuint8;
0010 typedef volatile unsigned short vuint16;
0011 typedef volatile unsigned long vuint32;
0012 
0013 /*********************************************************************
0014 *
0015 * System Control Module (SCM)
0016 *
0017 *********************************************************************/
0018 
0019 /* Register read/write macros */
0020 #define MCF_SCM_IPSBAR               (*(vuint32*)(&__IPSBAR[0x000000]))
0021 #define MCF_SCM_RAMBAR               (*(vuint32*)(&__IPSBAR[0x000008]))
0022 #define MCF_SCM_PPMRH                (*(vuint32*)(&__IPSBAR[0x00000C]))
0023 #define MCF_SCM_CRSR                 (*(vuint8 *)(&__IPSBAR[0x000010]))
0024 #define MCF_SCM_CWCR                 (*(vuint8 *)(&__IPSBAR[0x000011]))
0025 #define MCF_SCM_LPICR                (*(vuint8 *)(&__IPSBAR[0x000012]))
0026 #define MCF_SCM_CWSR                 (*(vuint8 *)(&__IPSBAR[0x000013]))
0027 #define MCF_SCM_PPMRL                (*(vuint32*)(&__IPSBAR[0x000018]))
0028 #define MCF_SCM_MPARK                (*(vuint32*)(&__IPSBAR[0x00001C]))
0029 #define MCF_SCM_MPR                  (*(vuint32*)(&__IPSBAR[0x000020]))
0030 #define MCF_SCM_PPMRS                (*(vuint8 *)(&__IPSBAR[0x000021]))
0031 #define MCF_SCM_PPMRC                (*(vuint8 *)(&__IPSBAR[0x000022]))
0032 #define MCF_SCM_IPSBMT               (*(vuint8 *)(&__IPSBAR[0x000023]))
0033 #define MCF_SCM_PACR0                (*(vuint8 *)(&__IPSBAR[0x000024]))
0034 #define MCF_SCM_PACR1                (*(vuint8 *)(&__IPSBAR[0x000025]))
0035 #define MCF_SCM_PACR2                (*(vuint8 *)(&__IPSBAR[0x000026]))
0036 #define MCF_SCM_PACR3                (*(vuint8 *)(&__IPSBAR[0x000027]))
0037 #define MCF_SCM_PACR4                (*(vuint8 *)(&__IPSBAR[0x000028]))
0038 #define MCF_SCM_PACR5                (*(vuint8 *)(&__IPSBAR[0x000029]))
0039 #define MCF_SCM_PACR6                (*(vuint8 *)(&__IPSBAR[0x00002A]))
0040 #define MCF_SCM_PACR7                (*(vuint8 *)(&__IPSBAR[0x00002B]))
0041 #define MCF_SCM_PACR8                (*(vuint8 *)(&__IPSBAR[0x00002C]))
0042 #define MCF_SCM_GPACR0               (*(vuint8 *)(&__IPSBAR[0x000030]))
0043 #define MCF_SCM_GPACR1               (*(vuint8 *)(&__IPSBAR[0x000031]))
0044 
0045 /* Bit definitions and macros for MCF_SCM_IPSBAR */
0046 #define MCF_SCM_IPSBAR_V             (0x00000001)
0047 #define MCF_SCM_IPSBAR_BA(x)         ((x)&0xC0000000)
0048 
0049 /* Bit definitions and macros for MCF_SCM_RAMBAR */
0050 #define MCF_SCM_RAMBAR_BDE           (0x00000200)
0051 #define MCF_SCM_RAMBAR_BA(x)         ((x)&0xFFFF0000)
0052 
0053 /* Bit definitions and macros for MCF_SCM_CRSR */
0054 #define MCF_SCM_CRSR_CWDR            (0x20)
0055 #define MCF_SCM_CRSR_EXT             (0x80)
0056 
0057 /* Bit definitions and macros for MCF_SCM_CWCR */
0058 #define MCF_SCM_CWCR_CWTIC           (0x01)
0059 #define MCF_SCM_CWCR_CWTAVAL         (0x02)
0060 #define MCF_SCM_CWCR_CWTA            (0x04)
0061 #define MCF_SCM_CWCR_CWT(x)          (((x)&0x07)<<3)
0062 #define MCF_SCM_CWCR_CWRI            (0x40)
0063 #define MCF_SCM_CWCR_CWE             (0x80)
0064 
0065 /* Bit definitions and macros for MCF_SCM_LPICR */
0066 #define MCF_SCM_LPICR_XIPL(x)        (((x)&0x07)<<4)
0067 #define MCF_SCM_LPICR_ENBSTOP        (0x80)
0068 
0069 /* Bit definitions and macros for MCF_SCM_CWSR */
0070 #define MCF_SCM_CWSR_CWSR(x)         (((x)&0xFF)<<0)
0071 
0072 /* Bit definitions and macros for MCF_SCM_PPMRH */
0073 #define MCF_SCM_PPMRH_CDPORTS        (0x00000001)
0074 #define MCF_SCM_PPMRH_CDEPORT        (0x00000002)
0075 #define MCF_SCM_PPMRH_CDPIT0         (0x00000008)
0076 #define MCF_SCM_PPMRH_CDPIT1         (0x00000010)
0077 #define MCF_SCM_PPMRH_CDADC          (0x00000080)
0078 #define MCF_SCM_PPMRH_CDGPT          (0x00000100)
0079 #define MCF_SCM_PPMRH_CDPWN          (0x00000200)
0080 #define MCF_SCM_PPMRH_CDFCAN         (0x00000400)
0081 #define MCF_SCM_PPMRH_CDCFM          (0x00000800)
0082 
0083 /* Bit definitions and macros for MCF_SCM_PPMRL */
0084 #define MCF_SCM_PPMRL_CDG            (0x00000002)
0085 #define MCF_SCM_PPMRL_CDEIM          (0x00000008)
0086 #define MCF_SCM_PPMRL_CDDMA          (0x00000010)
0087 #define MCF_SCM_PPMRL_CDUART0        (0x00000020)
0088 #define MCF_SCM_PPMRL_CDUART1        (0x00000040)
0089 #define MCF_SCM_PPMRL_CDUART2        (0x00000080)
0090 #define MCF_SCM_PPMRL_CDI2C          (0x00000200)
0091 #define MCF_SCM_PPMRL_CDQSPI         (0x00000400)
0092 #define MCF_SCM_PPMRL_CDDTIM0        (0x00002000)
0093 #define MCF_SCM_PPMRL_CDDTIM1        (0x00004000)
0094 #define MCF_SCM_PPMRL_CDDTIM2        (0x00008000)
0095 #define MCF_SCM_PPMRL_CDDTIM3        (0x00010000)
0096 #define MCF_SCM_PPMRL_CDINTC0        (0x00020000)
0097 
0098 /* Bit definitions and macros for MCF_SCM_MPARK */
0099 #define MCF_SCM_MPARK_LCKOUT_TIME(x)  (((x)&0x0000000F)<<8)
0100 #define MCF_SCM_MPARK_PRKLAST         (0x00001000)
0101 #define MCF_SCM_MPARK_TIMEOUT         (0x00002000)
0102 #define MCF_SCM_MPARK_FIXED           (0x00004000)
0103 #define MCF_SCM_MPARK_M0PRTY(x)       (((x)&0x00000003)<<18)
0104 #define MCF_SCM_MPARK_M2PRTY(x)       (((x)&0x00000003)<<20)
0105 #define MCF_SCM_MPARK_M3PRTY(x)       (((x)&0x00000003)<<22)
0106 #define MCF_SCM_MPARK_BCR24BIT        (0x01000000)
0107 #define MCF_SCM_MPARK_M2_P_EN         (0x02000000)
0108 
0109 /* Bit definitions and macros for MCF_SCM_PPMRS */
0110 #define MCF_SCM_PPMRS_DISABLE_ALL    (64)
0111 #define MCF_SCM_PPMRS_DISABLE_CFM    (43)
0112 #define MCF_SCM_PPMRS_DISABLE_CAN    (42)
0113 #define MCF_SCM_PPMRS_DISABLE_PWM    (41)
0114 #define MCF_SCM_PPMRS_DISABLE_GPT    (40)
0115 #define MCF_SCM_PPMRS_DISABLE_ADC    (39)
0116 #define MCF_SCM_PPMRS_DISABLE_PIT1   (36)
0117 #define MCF_SCM_PPMRS_DISABLE_PIT0   (35)
0118 #define MCF_SCM_PPMRS_DISABLE_EPORT  (33)
0119 #define MCF_SCM_PPMRS_DISABLE_PORTS  (32)
0120 #define MCF_SCM_PPMRS_DISABLE_INTC   (17)
0121 #define MCF_SCM_PPMRS_DISABLE_DTIM3  (16)
0122 #define MCF_SCM_PPMRS_DISABLE_DTIM2  (15)
0123 #define MCF_SCM_PPMRS_DISABLE_DTIM1  (14)
0124 #define MCF_SCM_PPMRS_DISABLE_DTIM0  (13)
0125 #define MCF_SCM_PPMRS_DISABLE_QSPI   (10)
0126 #define MCF_SCM_PPMRS_DISABLE_I2C    (9)
0127 #define MCF_SCM_PPMRS_DISABLE_UART2  (7)
0128 #define MCF_SCM_PPMRS_DISABLE_UART1  (6)
0129 #define MCF_SCM_PPMRS_DISABLE_UART0  (5)
0130 #define MCF_SCM_PPMRS_DISABLE_DMA    (4)
0131 #define MCF_SCM_PPMRS_SET_CDG        (1)
0132 
0133 /* Bit definitions and macros for MCF_SCM_PPMRC */
0134 #define MCF_SCM_PPMRC_ENABLE_ALL     (64)
0135 #define MCF_SCM_PPMRC_ENABLE_CFM     (43)
0136 #define MCF_SCM_PPMRC_ENABLE_CAN     (42)
0137 #define MCF_SCM_PPMRC_ENABLE_PWM     (41)
0138 #define MCF_SCM_PPMRC_ENABLE_GPT     (40)
0139 #define MCF_SCM_PPMRC_ENABLE_ADC     (39)
0140 #define MCF_SCM_PPMRC_ENABLE_PIT1    (36)
0141 #define MCF_SCM_PPMRC_ENABLE_PIT0    (35)
0142 #define MCF_SCM_PPMRC_ENABLE_EPORT   (33)
0143 #define MCF_SCM_PPMRC_ENABLE_PORTS   (32)
0144 #define MCF_SCM_PPMRC_ENABLE_INTC    (17)
0145 #define MCF_SCM_PPMRC_ENABLE_DTIM3   (16)
0146 #define MCF_SCM_PPMRC_ENABLE_DTIM2   (15)
0147 #define MCF_SCM_PPMRC_ENABLE_DTIM1   (14)
0148 #define MCF_SCM_PPMRC_ENABLE_DTIM0   (13)
0149 #define MCF_SCM_PPMRC_ENABLE_QSPI    (10)
0150 #define MCF_SCM_PPMRC_ENABLE_I2C     (9)
0151 #define MCF_SCM_PPMRC_ENABLE_UART2   (7)
0152 #define MCF_SCM_PPMRC_ENABLE_UART1   (6)
0153 #define MCF_SCM_PPMRC_ENABLE_UART0   (5)
0154 #define MCF_SCM_PPMRC_ENABLE_DMA     (4)
0155 #define MCF_SCM_PPMRC_CLEAR_CDG      (1)
0156 
0157 
0158 /*********************************************************************
0159 *
0160 * Power Management Module (PMM)
0161 *
0162 *********************************************************************/
0163 
0164 /* Register read/write macros */
0165 #define MCF_PMM_PPMRH           (*(vuint32*)(&__IPSBAR[0x00000C]))
0166 #define MCF_PMM_PPMRL           (*(vuint32*)(&__IPSBAR[0x000018]))
0167 #define MCF_PMM_LPICR           (*(vuint8 *)(&__IPSBAR[0x000012]))
0168 #define MCF_PMM_LPCR            (*(vuint8 *)(&__IPSBAR[0x110007]))
0169 
0170 /* Bit definitions and macros for MCF_PMM_PPMRH */
0171 #define MCF_PMM_PPMRH_CDPORTS   (0x00000001)
0172 #define MCF_PMM_PPMRH_CDEPORT   (0x00000002)
0173 #define MCF_PMM_PPMRH_CDPIT0    (0x00000008)
0174 #define MCF_PMM_PPMRH_CDPIT1    (0x00000010)
0175 #define MCF_PMM_PPMRH_CDADC     (0x00000080)
0176 #define MCF_PMM_PPMRH_CDGPT     (0x00000100)
0177 #define MCF_PMM_PPMRH_CDPWM     (0x00000200)
0178 #define MCF_PMM_PPMRH_CDFCAN    (0x00000400)
0179 #define MCF_PMM_PPMRH_CDCFM     (0x00000800)
0180 
0181 /* Bit definitions and macros for MCF_PMM_PPMRL */
0182 #define MCF_PMM_PPMRL_CDG       (0x00000002)
0183 #define MCF_PMM_PPMRL_CDEIM     (0x00000008)
0184 #define MCF_PMM_PPMRL_CDDMA     (0x00000010)
0185 #define MCF_PMM_PPMRL_CDUART0   (0x00000020)
0186 #define MCF_PMM_PPMRL_CDUART1   (0x00000040)
0187 #define MCF_PMM_PPMRL_CDUART2   (0x00000080)
0188 #define MCF_PMM_PPMRL_CDI2C     (0x00000200)
0189 #define MCF_PMM_PPMRL_CDQSPI    (0x00000400)
0190 #define MCF_PMM_PPMRL_CDDTIM0   (0x00002000)
0191 #define MCF_PMM_PPMRL_CDDTIM1   (0x00004000)
0192 #define MCF_PMM_PPMRL_CDDTIM2   (0x00008000)
0193 #define MCF_PMM_PPMRL_CDDTIM3   (0x00010000)
0194 #define MCF_PMM_PPMRL_CDINTC0   (0x00020000)
0195 
0196 /* Bit definitions and macros for MCF_PMM_LPICR */
0197 #define MCF_PMM_LPICR_XIPL(x)   (((x)&0x07)<<4)
0198 #define MCF_PMM_LPICR_ENBSTOP   (0x80)
0199 
0200 /* Bit definitions and macros for MCF_PMM_LPCR */
0201 #define MCF_PMM_LPCR_LVDSE      (0x02)
0202 #define MCF_PMM_LPCR_STPMD(x)   (((x)&0x03)<<3)
0203 #define MCF_PMM_LPCR_LPMD(x)    (((x)&0x03)<<6)
0204 #define MCF_PMM_LPCR_LPMD_STOP  (0xC0)
0205 #define MCF_PMM_LPCR_LPMD_WAIT  (0x80)
0206 #define MCF_PMM_LPCR_LPMD_DOZE  (0x40)
0207 #define MCF_PMM_LPCR_LPMD_RUN   (0x00)
0208 
0209 
0210 /*********************************************************************
0211 *
0212 * DMA Controller Module (DMA)
0213 *
0214 *********************************************************************/
0215 
0216 /* Register read/write macros */
0217 #define MCF_DMA_DMAREQC                 (*(vuint32*)(&__IPSBAR[0x000014]))
0218 #define MCF_DMA_SAR0                    (*(vuint32*)(&__IPSBAR[0x000100]))
0219 #define MCF_DMA_SAR1                    (*(vuint32*)(&__IPSBAR[0x000110]))
0220 #define MCF_DMA_SAR2                    (*(vuint32*)(&__IPSBAR[0x000120]))
0221 #define MCF_DMA_SAR3                    (*(vuint32*)(&__IPSBAR[0x000130]))
0222 #define MCF_DMA_SAR(x)                  (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)]))
0223 #define MCF_DMA_DAR0                    (*(vuint32*)(&__IPSBAR[0x000104]))
0224 #define MCF_DMA_DAR1                    (*(vuint32*)(&__IPSBAR[0x000114]))
0225 #define MCF_DMA_DAR2                    (*(vuint32*)(&__IPSBAR[0x000124]))
0226 #define MCF_DMA_DAR3                    (*(vuint32*)(&__IPSBAR[0x000134]))
0227 #define MCF_DMA_DAR(x)                  (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)]))
0228 #define MCF_DMA_DSR0                    (*(vuint8 *)(&__IPSBAR[0x000108]))
0229 #define MCF_DMA_DSR1                    (*(vuint8 *)(&__IPSBAR[0x000118]))
0230 #define MCF_DMA_DSR2                    (*(vuint8 *)(&__IPSBAR[0x000128]))
0231 #define MCF_DMA_DSR3                    (*(vuint8 *)(&__IPSBAR[0x000138]))
0232 #define MCF_DMA_DSR(x)                  (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)]))
0233 #define MCF_DMA_BCR0                    (*(vuint32*)(&__IPSBAR[0x000108]))
0234 #define MCF_DMA_BCR1                    (*(vuint32*)(&__IPSBAR[0x000118]))
0235 #define MCF_DMA_BCR2                    (*(vuint32*)(&__IPSBAR[0x000128]))
0236 #define MCF_DMA_BCR3                    (*(vuint32*)(&__IPSBAR[0x000138]))
0237 #define MCF_DMA_BCR(x)                  (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)]))
0238 #define MCF_DMA_DCR0                    (*(vuint32*)(&__IPSBAR[0x00010C]))
0239 #define MCF_DMA_DCR1                    (*(vuint32*)(&__IPSBAR[0x00011C]))
0240 #define MCF_DMA_DCR2                    (*(vuint32*)(&__IPSBAR[0x00012C]))
0241 #define MCF_DMA_DCR3                    (*(vuint32*)(&__IPSBAR[0x00013C]))
0242 #define MCF_DMA_DCR(x)                  (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)]))
0243 
0244 /* Bit definitions and macros for MCF_DMA_DMAREQC */
0245 #define MCF_DMA_DMAREQC_DMAC0(x)        (((x)&0x0000000F)<<0)
0246 #define MCF_DMA_DMAREQC_DMAC1(x)        (((x)&0x0000000F)<<4)
0247 #define MCF_DMA_DMAREQC_DMAC2(x)        (((x)&0x0000000F)<<8)
0248 #define MCF_DMA_DMAREQC_DMAC3(x)        (((x)&0x0000000F)<<12)
0249 #define MCF_DMA_DMAREQC_DMAREQC_EXT(x)  (((x)&0x0000000F)<<16)
0250 
0251 /* Bit definitions and macros for MCF_DMA_SAR */
0252 #define MCF_DMA_SAR_SAR(x)              (((x)&0xFFFFFFFF)<<0)
0253 
0254 /* Bit definitions and macros for MCF_DMA_DAR */
0255 #define MCF_DMA_DAR_DAR(x)              (((x)&0xFFFFFFFF)<<0)
0256 
0257 /* Bit definitions and macros for MCF_DMA_DSR */
0258 #define MCF_DMA_DSR_DONE                (0x01)
0259 #define MCF_DMA_DSR_BSY                 (0x02)
0260 #define MCF_DMA_DSR_REQ                 (0x04)
0261 #define MCF_DMA_DSR_BED                 (0x10)
0262 #define MCF_DMA_DSR_BES                 (0x20)
0263 #define MCF_DMA_DSR_CE                  (0x40)
0264 
0265 /* Bit definitions and macros for MCF_DMA_BCR */
0266 #define MCF_DMA_BCR_BCR(x)              (((x)&0x00FFFFFF)<<0)
0267 #define MCF_DMA_BCR_DSR(x)              (((x)&0x000000FF)<<24)
0268 
0269 /* Bit definitions and macros for MCF_DMA_DCR */
0270 #define MCF_DMA_DCR_LCH2(x)             (((x)&0x00000003)<<0)
0271 #define MCF_DMA_DCR_LCH1(x)             (((x)&0x00000003)<<2)
0272 #define MCF_DMA_DCR_LINKCC(x)           (((x)&0x00000003)<<4)
0273 #define MCF_DMA_DCR_D_REQ               (0x00000080)
0274 #define MCF_DMA_DCR_DMOD(x)             (((x)&0x0000000F)<<8)
0275 #define MCF_DMA_DCR_SMOD(x)             (((x)&0x0000000F)<<12)
0276 #define MCF_DMA_DCR_START               (0x00010000)
0277 #define MCF_DMA_DCR_DSIZE(x)            (((x)&0x00000003)<<17)
0278 #define MCF_DMA_DCR_DINC                (0x00080000)
0279 #define MCF_DMA_DCR_SSIZE(x)            (((x)&0x00000003)<<20)
0280 #define MCF_DMA_DCR_SINC                (0x00400000)
0281 #define MCF_DMA_DCR_BWC(x)              (((x)&0x00000007)<<25)
0282 #define MCF_DMA_DCR_AA                  (0x10000000)
0283 #define MCF_DMA_DCR_CS                  (0x20000000)
0284 #define MCF_DMA_DCR_EEXT                (0x40000000)
0285 #define MCF_DMA_DCR_INT                 (0x80000000)
0286 #define MCF_DMA_DCR_BWC_16K             (0x1)
0287 #define MCF_DMA_DCR_BWC_32K             (0x2)
0288 #define MCF_DMA_DCR_BWC_64K             (0x3)
0289 #define MCF_DMA_DCR_BWC_128K            (0x4)
0290 #define MCF_DMA_DCR_BWC_256K            (0x5)
0291 #define MCF_DMA_DCR_BWC_512K            (0x6)
0292 #define MCF_DMA_DCR_BWC_1024K           (0x7)
0293 #define MCF_DMA_DCR_DMOD_DIS            (0x0)
0294 #define MCF_DMA_DCR_DMOD_16             (0x1)
0295 #define MCF_DMA_DCR_DMOD_32             (0x2)
0296 #define MCF_DMA_DCR_DMOD_64             (0x3)
0297 #define MCF_DMA_DCR_DMOD_128            (0x4)
0298 #define MCF_DMA_DCR_DMOD_256            (0x5)
0299 #define MCF_DMA_DCR_DMOD_512            (0x6)
0300 #define MCF_DMA_DCR_DMOD_1K             (0x7)
0301 #define MCF_DMA_DCR_DMOD_2K             (0x8)
0302 #define MCF_DMA_DCR_DMOD_4K             (0x9)
0303 #define MCF_DMA_DCR_DMOD_8K             (0xA)
0304 #define MCF_DMA_DCR_DMOD_16K            (0xB)
0305 #define MCF_DMA_DCR_DMOD_32K            (0xC)
0306 #define MCF_DMA_DCR_DMOD_64K            (0xD)
0307 #define MCF_DMA_DCR_DMOD_128K           (0xE)
0308 #define MCF_DMA_DCR_DMOD_256K           (0xF)
0309 #define MCF_DMA_DCR_SMOD_DIS            (0x0)
0310 #define MCF_DMA_DCR_SMOD_16             (0x1)
0311 #define MCF_DMA_DCR_SMOD_32             (0x2)
0312 #define MCF_DMA_DCR_SMOD_64             (0x3)
0313 #define MCF_DMA_DCR_SMOD_128            (0x4)
0314 #define MCF_DMA_DCR_SMOD_256            (0x5)
0315 #define MCF_DMA_DCR_SMOD_512            (0x6)
0316 #define MCF_DMA_DCR_SMOD_1K             (0x7)
0317 #define MCF_DMA_DCR_SMOD_2K             (0x8)
0318 #define MCF_DMA_DCR_SMOD_4K             (0x9)
0319 #define MCF_DMA_DCR_SMOD_8K             (0xA)
0320 #define MCF_DMA_DCR_SMOD_16K            (0xB)
0321 #define MCF_DMA_DCR_SMOD_32K            (0xC)
0322 #define MCF_DMA_DCR_SMOD_64K            (0xD)
0323 #define MCF_DMA_DCR_SMOD_128K           (0xE)
0324 #define MCF_DMA_DCR_SMOD_256K           (0xF)
0325 #define MCF_DMA_DCR_SSIZE_LONG          (0x0)
0326 #define MCF_DMA_DCR_SSIZE_BYTE          (0x1)
0327 #define MCF_DMA_DCR_SSIZE_WORD          (0x2)
0328 #define MCF_DMA_DCR_SSIZE_LINE          (0x3)
0329 #define MCF_DMA_DCR_DSIZE_LONG          (0x0)
0330 #define MCF_DMA_DCR_DSIZE_BYTE          (0x1)
0331 #define MCF_DMA_DCR_DSIZE_WORD          (0x2)
0332 #define MCF_DMA_DCR_DSIZE_LINE          (0x3)
0333 #define MCF_DMA_DCR_LCH1_CH0            (0x0)
0334 #define MCF_DMA_DCR_LCH1_CH1            (0x1)
0335 #define MCF_DMA_DCR_LCH1_CH2            (0x2)
0336 #define MCF_DMA_DCR_LCH1_CH3            (0x3)
0337 #define MCF_DMA_DCR_LCH2_CH0            (0x0)
0338 #define MCF_DMA_DCR_LCH2_CH1            (0x1)
0339 #define MCF_DMA_DCR_LCH2_CH2            (0x2)
0340 #define MCF_DMA_DCR_LCH2_CH3            (0x3)
0341 
0342 
0343 /*********************************************************************
0344 *
0345 * Universal Asynchronous Receiver Transmitter (UART)
0346 *
0347 *********************************************************************/
0348 
0349 /* Register read/write macros */
0350 #define MCF_UART0_UMR                 (*(vuint8 *)(&__IPSBAR[0x000200]))
0351 #define MCF_UART0_USR                 (*(vuint8 *)(&__IPSBAR[0x000204]))
0352 #define MCF_UART0_UCSR                (*(vuint8 *)(&__IPSBAR[0x000204]))
0353 #define MCF_UART0_UCR                 (*(vuint8 *)(&__IPSBAR[0x000208]))
0354 #define MCF_UART0_URB                 (*(vuint8 *)(&__IPSBAR[0x00020C]))
0355 #define MCF_UART0_UTB                 (*(vuint8 *)(&__IPSBAR[0x00020C]))
0356 #define MCF_UART0_UIPCR               (*(vuint8 *)(&__IPSBAR[0x000210]))
0357 #define MCF_UART0_UACR                (*(vuint8 *)(&__IPSBAR[0x000210]))
0358 #define MCF_UART0_UISR                (*(vuint8 *)(&__IPSBAR[0x000214]))
0359 #define MCF_UART0_UIMR                (*(vuint8 *)(&__IPSBAR[0x000214]))
0360 #define MCF_UART0_UBG1                (*(vuint8 *)(&__IPSBAR[0x000218]))
0361 #define MCF_UART0_UBG2                (*(vuint8 *)(&__IPSBAR[0x00021C]))
0362 #define MCF_UART0_UIP                 (*(vuint8 *)(&__IPSBAR[0x000234]))
0363 #define MCF_UART0_UOP1                (*(vuint8 *)(&__IPSBAR[0x000238]))
0364 #define MCF_UART0_UOP0                (*(vuint8 *)(&__IPSBAR[0x00023C]))
0365 #define MCF_UART1_UMR                 (*(vuint8 *)(&__IPSBAR[0x000240]))
0366 #define MCF_UART1_USR                 (*(vuint8 *)(&__IPSBAR[0x000244]))
0367 #define MCF_UART1_UCSR                (*(vuint8 *)(&__IPSBAR[0x000244]))
0368 #define MCF_UART1_UCR                 (*(vuint8 *)(&__IPSBAR[0x000248]))
0369 #define MCF_UART1_URB                 (*(vuint8 *)(&__IPSBAR[0x00024C]))
0370 #define MCF_UART1_UTB                 (*(vuint8 *)(&__IPSBAR[0x00024C]))
0371 #define MCF_UART1_UIPCR               (*(vuint8 *)(&__IPSBAR[0x000250]))
0372 #define MCF_UART1_UACR                (*(vuint8 *)(&__IPSBAR[0x000250]))
0373 #define MCF_UART1_UISR                (*(vuint8 *)(&__IPSBAR[0x000254]))
0374 #define MCF_UART1_UIMR                (*(vuint8 *)(&__IPSBAR[0x000254]))
0375 #define MCF_UART1_UBG1                (*(vuint8 *)(&__IPSBAR[0x000258]))
0376 #define MCF_UART1_UBG2                (*(vuint8 *)(&__IPSBAR[0x00025C]))
0377 #define MCF_UART1_UIP                 (*(vuint8 *)(&__IPSBAR[0x000274]))
0378 #define MCF_UART1_UOP1                (*(vuint8 *)(&__IPSBAR[0x000278]))
0379 #define MCF_UART1_UOP0                (*(vuint8 *)(&__IPSBAR[0x00027C]))
0380 #define MCF_UART2_UMR                 (*(vuint8 *)(&__IPSBAR[0x000280]))
0381 #define MCF_UART2_USR                 (*(vuint8 *)(&__IPSBAR[0x000284]))
0382 #define MCF_UART2_UCSR                (*(vuint8 *)(&__IPSBAR[0x000284]))
0383 #define MCF_UART2_UCR                 (*(vuint8 *)(&__IPSBAR[0x000288]))
0384 #define MCF_UART2_URB                 (*(vuint8 *)(&__IPSBAR[0x00028C]))
0385 #define MCF_UART2_UTB                 (*(vuint8 *)(&__IPSBAR[0x00028C]))
0386 #define MCF_UART2_UIPCR               (*(vuint8 *)(&__IPSBAR[0x000290]))
0387 #define MCF_UART2_UACR                (*(vuint8 *)(&__IPSBAR[0x000290]))
0388 #define MCF_UART2_UISR                (*(vuint8 *)(&__IPSBAR[0x000294]))
0389 #define MCF_UART2_UIMR                (*(vuint8 *)(&__IPSBAR[0x000294]))
0390 #define MCF_UART2_UBG1                (*(vuint8 *)(&__IPSBAR[0x000298]))
0391 #define MCF_UART2_UBG2                (*(vuint8 *)(&__IPSBAR[0x00029C]))
0392 #define MCF_UART2_UIP                 (*(vuint8 *)(&__IPSBAR[0x0002B4]))
0393 #define MCF_UART2_UOP1                (*(vuint8 *)(&__IPSBAR[0x0002B8]))
0394 #define MCF_UART2_UOP0                (*(vuint8 *)(&__IPSBAR[0x0002BC]))
0395 #define MCF_UART_UMR(x)               (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)]))
0396 #define MCF_UART_USR(x)               (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)]))
0397 #define MCF_UART_UCSR(x)              (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)]))
0398 #define MCF_UART_UCR(x)               (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)]))
0399 #define MCF_UART_URB(x)               (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)]))
0400 #define MCF_UART_UTB(x)               (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)]))
0401 #define MCF_UART_UIPCR(x)             (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)]))
0402 #define MCF_UART_UACR(x)              (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)]))
0403 #define MCF_UART_UISR(x)              (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)]))
0404 #define MCF_UART_UIMR(x)              (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)]))
0405 #define MCF_UART_UBG1(x)              (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)]))
0406 #define MCF_UART_UBG2(x)              (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)]))
0407 #define MCF_UART_UIP(x)               (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)]))
0408 #define MCF_UART_UOP1(x)              (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)]))
0409 #define MCF_UART_UOP0(x)              (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)]))
0410 
0411 /* Bit definitions and macros for MCF_UART_UMR */
0412 #define MCF_UART_UMR_BC(x)            (((x)&0x03)<<0)
0413 #define MCF_UART_UMR_PT               (0x04)
0414 #define MCF_UART_UMR_PM(x)            (((x)&0x03)<<3)
0415 #define MCF_UART_UMR_ERR              (0x20)
0416 #define MCF_UART_UMR_RXIRQ            (0x40)
0417 #define MCF_UART_UMR_RXRTS            (0x80)
0418 #define MCF_UART_UMR_SB(x)            (((x)&0x0F)<<0)
0419 #define MCF_UART_UMR_TXCTS            (0x10)
0420 #define MCF_UART_UMR_TXRTS            (0x20)
0421 #define MCF_UART_UMR_CM(x)            (((x)&0x03)<<6)
0422 #define MCF_UART_UMR_PM_MULTI_ADDR    (0x1C)
0423 #define MCF_UART_UMR_PM_MULTI_DATA    (0x18)
0424 #define MCF_UART_UMR_PM_NONE          (0x10)
0425 #define MCF_UART_UMR_PM_FORCE_HI      (0x0C)
0426 #define MCF_UART_UMR_PM_FORCE_LO      (0x08)
0427 #define MCF_UART_UMR_PM_ODD           (0x04)
0428 #define MCF_UART_UMR_PM_EVEN          (0x00)
0429 #define MCF_UART_UMR_BC_5             (0x00)
0430 #define MCF_UART_UMR_BC_6             (0x01)
0431 #define MCF_UART_UMR_BC_7             (0x02)
0432 #define MCF_UART_UMR_BC_8             (0x03)
0433 #define MCF_UART_UMR_CM_NORMAL        (0x00)
0434 #define MCF_UART_UMR_CM_ECHO          (0x40)
0435 #define MCF_UART_UMR_CM_LOCAL_LOOP    (0x80)
0436 #define MCF_UART_UMR_CM_REMOTE_LOOP   (0xC0)
0437 #define MCF_UART_UMR_SB_STOP_BITS_1   (0x07)
0438 #define MCF_UART_UMR_SB_STOP_BITS_15  (0x08)
0439 #define MCF_UART_UMR_SB_STOP_BITS_2   (0x0F)
0440 
0441 /* Bit definitions and macros for MCF_UART_USR */
0442 #define MCF_UART_USR_RXRDY            (0x01)
0443 #define MCF_UART_USR_FFULL            (0x02)
0444 #define MCF_UART_USR_TXRDY            (0x04)
0445 #define MCF_UART_USR_TXEMP            (0x08)
0446 #define MCF_UART_USR_OE               (0x10)
0447 #define MCF_UART_USR_PE               (0x20)
0448 #define MCF_UART_USR_FE               (0x40)
0449 #define MCF_UART_USR_RB               (0x80)
0450 
0451 /* Bit definitions and macros for MCF_UART_UCSR */
0452 #define MCF_UART_UCSR_TCS(x)          (((x)&0x0F)<<0)
0453 #define MCF_UART_UCSR_RCS(x)          (((x)&0x0F)<<4)
0454 #define MCF_UART_UCSR_RCS_SYS_CLK     (0xD0)
0455 #define MCF_UART_UCSR_RCS_CTM16       (0xE0)
0456 #define MCF_UART_UCSR_RCS_CTM         (0xF0)
0457 #define MCF_UART_UCSR_TCS_SYS_CLK     (0x0D)
0458 #define MCF_UART_UCSR_TCS_CTM16       (0x0E)
0459 #define MCF_UART_UCSR_TCS_CTM         (0x0F)
0460 
0461 /* Bit definitions and macros for MCF_UART_UCR */
0462 #define MCF_UART_UCR_RXC(x)           (((x)&0x03)<<0)
0463 #define MCF_UART_UCR_TXC(x)           (((x)&0x03)<<2)
0464 #define MCF_UART_UCR_MISC(x)          (((x)&0x07)<<4)
0465 #define MCF_UART_UCR_NONE             (0x00)
0466 #define MCF_UART_UCR_STOP_BREAK       (0x70)
0467 #define MCF_UART_UCR_START_BREAK      (0x60)
0468 #define MCF_UART_UCR_BKCHGINT         (0x50)
0469 #define MCF_UART_UCR_RESET_ERROR      (0x40)
0470 #define MCF_UART_UCR_RESET_TX         (0x30)
0471 #define MCF_UART_UCR_RESET_RX         (0x20)
0472 #define MCF_UART_UCR_RESET_MR         (0x10)
0473 #define MCF_UART_UCR_TX_DISABLED      (0x08)
0474 #define MCF_UART_UCR_TX_ENABLED       (0x04)
0475 #define MCF_UART_UCR_RX_DISABLED      (0x02)
0476 #define MCF_UART_UCR_RX_ENABLED       (0x01)
0477 
0478 /* Bit definitions and macros for MCF_UART_UIPCR */
0479 #define MCF_UART_UIPCR_CTS            (0x01)
0480 #define MCF_UART_UIPCR_COS            (0x10)
0481 
0482 /* Bit definitions and macros for MCF_UART_UACR */
0483 #define MCF_UART_UACR_IEC             (0x01)
0484 
0485 /* Bit definitions and macros for MCF_UART_UISR */
0486 #define MCF_UART_UISR_TXRDY           (0x01)
0487 #define MCF_UART_UISR_RXRDY_FU        (0x02)
0488 #define MCF_UART_UISR_DB              (0x04)
0489 #define MCF_UART_UISR_RXFTO           (0x08)
0490 #define MCF_UART_UISR_TXFIFO          (0x10)
0491 #define MCF_UART_UISR_RXFIFO          (0x20)
0492 #define MCF_UART_UISR_COS             (0x80)
0493 
0494 /* Bit definitions and macros for MCF_UART_UIMR */
0495 #define MCF_UART_UIMR_TXRDY           (0x01)
0496 #define MCF_UART_UIMR_RXRDY_FU        (0x02)
0497 #define MCF_UART_UIMR_DB              (0x04)
0498 #define MCF_UART_UIMR_COS             (0x80)
0499 
0500 /* Bit definitions and macros for MCF_UART_UIP */
0501 #define MCF_UART_UIP_CTS              (0x01)
0502 
0503 /* Bit definitions and macros for MCF_UART_UOP1 */
0504 #define MCF_UART_UOP1_RTS             (0x01)
0505 
0506 /* Bit definitions and macros for MCF_UART_UOP0 */
0507 #define MCF_UART_UOP0_RTS             (0x01)
0508 
0509 /*********************************************************************
0510 *
0511 * I2C Module (I2C)
0512 *
0513 *********************************************************************/
0514 
0515 /* Register read/write macros */
0516 #define MCF_I2C_I2AR          (*(vuint8 *)(&__IPSBAR[0x000300]))
0517 #define MCF_I2C_I2FDR         (*(vuint8 *)(&__IPSBAR[0x000304]))
0518 #define MCF_I2C_I2CR          (*(vuint8 *)(&__IPSBAR[0x000308]))
0519 #define MCF_I2C_I2SR          (*(vuint8 *)(&__IPSBAR[0x00030C]))
0520 #define MCF_I2C_I2DR          (*(vuint8 *)(&__IPSBAR[0x000310]))
0521 
0522 /* Bit definitions and macros for MCF_I2C_I2AR */
0523 #define MCF_I2C_I2AR_ADR(x)   (((x)&0x7F)<<1)
0524 
0525 /* Bit definitions and macros for MCF_I2C_I2FDR */
0526 #define MCF_I2C_I2FDR_IC(x)   (((x)&0x3F)<<0)
0527 
0528 /* Bit definitions and macros for MCF_I2C_I2CR */
0529 #define MCF_I2C_I2CR_RSTA     (0x04)
0530 #define MCF_I2C_I2CR_TXAK     (0x08)
0531 #define MCF_I2C_I2CR_MTX      (0x10)
0532 #define MCF_I2C_I2CR_MSTA     (0x20)
0533 #define MCF_I2C_I2CR_IIEN     (0x40)
0534 #define MCF_I2C_I2CR_IEN      (0x80)
0535 
0536 /* Bit definitions and macros for MCF_I2C_I2SR */
0537 #define MCF_I2C_I2SR_RXAK     (0x01)
0538 #define MCF_I2C_I2SR_IIF      (0x02)
0539 #define MCF_I2C_I2SR_SRW      (0x04)
0540 #define MCF_I2C_I2SR_IAL      (0x10)
0541 #define MCF_I2C_I2SR_IBB      (0x20)
0542 #define MCF_I2C_I2SR_IAAS     (0x40)
0543 #define MCF_I2C_I2SR_ICF      (0x80)
0544 
0545 /* Bit definitions and macros for MCF_I2C_I2DR */
0546 #define MCF_I2C_I2DR_DATA(x)  (((x)&0xFF)<<0)
0547 
0548 /* Bit definitions and macros for MCF_I2C_I2ICR */
0549 #define MCF_I2C_I2ICR_IE      (0x01)
0550 #define MCF_I2C_I2ICR_RE      (0x02)
0551 #define MCF_I2C_I2ICR_TE      (0x04)
0552 #define MCF_I2C_I2ICR_BNBE    (0x08)
0553 
0554 /*********************************************************************
0555 *
0556 * Queued Serial Peripheral Interface (QSPI)
0557 *
0558 *********************************************************************/
0559 
0560 /* Register read/write macros */
0561 #define MCF_QSPI_QMR           (*(vuint16*)(&__IPSBAR[0x000340]))
0562 #define MCF_QSPI_QDLYR         (*(vuint16*)(&__IPSBAR[0x000344]))
0563 #define MCF_QSPI_QWR           (*(vuint16*)(&__IPSBAR[0x000348]))
0564 #define MCF_QSPI_QIR           (*(vuint16*)(&__IPSBAR[0x00034C]))
0565 #define MCF_QSPI_QAR           (*(vuint16*)(&__IPSBAR[0x000350]))
0566 #define MCF_QSPI_QDR           (*(vuint16*)(&__IPSBAR[0x000354]))
0567 
0568 /* Bit definitions and macros for MCF_QSPI_QMR */
0569 #define MCF_QSPI_QMR_BAUD(x)   (((x)&0x00FF)<<0)
0570 #define MCF_QSPI_QMR_CPHA      (0x0100)
0571 #define MCF_QSPI_QMR_CPOL      (0x0200)
0572 #define MCF_QSPI_QMR_BITS(x)   (((x)&0x000F)<<10)
0573 #define MCF_QSPI_QMR_DOHIE     (0x4000)
0574 #define MCF_QSPI_QMR_MSTR      (0x8000)
0575 
0576 /* Bit definitions and macros for MCF_QSPI_QDLYR */
0577 #define MCF_QSPI_QDLYR_DTL(x)  (((x)&0x00FF)<<0)
0578 #define MCF_QSPI_QDLYR_QCD(x)  (((x)&0x007F)<<8)
0579 #define MCF_QSPI_QDLYR_SPE     (0x8000)
0580 
0581 /* Bit definitions and macros for MCF_QSPI_QWR */
0582 #define MCF_QSPI_QWR_NEWQP(x)  (((x)&0x000F)<<0)
0583 #define MCF_QSPI_QWR_ENDQP(x)  (((x)&0x000F)<<8)
0584 #define MCF_QSPI_QWR_CSIV      (0x1000)
0585 #define MCF_QSPI_QWR_WRTO      (0x2000)
0586 #define MCF_QSPI_QWR_WREN      (0x4000)
0587 #define MCF_QSPI_QWR_HALT      (0x8000)
0588 
0589 /* Bit definitions and macros for MCF_QSPI_QIR */
0590 #define MCF_QSPI_QIR_SPIF      (0x0001)
0591 #define MCF_QSPI_QIR_ABRT      (0x0004)
0592 #define MCF_QSPI_QIR_WCEF      (0x0008)
0593 #define MCF_QSPI_QIR_SPIFE     (0x0100)
0594 #define MCF_QSPI_QIR_ABRTE     (0x0400)
0595 #define MCF_QSPI_QIR_WCEFE     (0x0800)
0596 #define MCF_QSPI_QIR_ABRTL     (0x1000)
0597 #define MCF_QSPI_QIR_ABRTB     (0x4000)
0598 #define MCF_QSPI_QIR_WCEFB     (0x8000)
0599 
0600 /* Bit definitions and macros for MCF_QSPI_QAR */
0601 #define MCF_QSPI_QAR_ADDR(x)   (((x)&0x003F)<<0)
0602 
0603 /* Bit definitions and macros for MCF_QSPI_QDR */
0604 #define MCF_QSPI_QDR_DATA(x)   (((x)&0xFFFF)<<0)
0605 
0606 /*********************************************************************
0607 *
0608 * DMA Timers (DTIM)
0609 *
0610 *********************************************************************/
0611 
0612 /* Register read/write macros */
0613 #define MCF_DTIM0_DTMR           (*(vuint16*)(&__IPSBAR[0x000400]))
0614 #define MCF_DTIM0_DTXMR          (*(vuint8 *)(&__IPSBAR[0x000402]))
0615 #define MCF_DTIM0_DTER           (*(vuint8 *)(&__IPSBAR[0x000403]))
0616 #define MCF_DTIM0_DTRR           (*(vuint32*)(&__IPSBAR[0x000404]))
0617 #define MCF_DTIM0_DTCR           (*(vuint32*)(&__IPSBAR[0x000408]))
0618 #define MCF_DTIM0_DTCN           (*(vuint32*)(&__IPSBAR[0x00040C]))
0619 #define MCF_DTIM1_DTMR           (*(vuint16*)(&__IPSBAR[0x000440]))
0620 #define MCF_DTIM1_DTXMR          (*(vuint8 *)(&__IPSBAR[0x000442]))
0621 #define MCF_DTIM1_DTER           (*(vuint8 *)(&__IPSBAR[0x000443]))
0622 #define MCF_DTIM1_DTRR           (*(vuint32*)(&__IPSBAR[0x000444]))
0623 #define MCF_DTIM1_DTCR           (*(vuint32*)(&__IPSBAR[0x000448]))
0624 #define MCF_DTIM1_DTCN           (*(vuint32*)(&__IPSBAR[0x00044C]))
0625 #define MCF_DTIM2_DTMR           (*(vuint16*)(&__IPSBAR[0x000480]))
0626 #define MCF_DTIM2_DTXMR          (*(vuint8 *)(&__IPSBAR[0x000482]))
0627 #define MCF_DTIM2_DTER           (*(vuint8 *)(&__IPSBAR[0x000483]))
0628 #define MCF_DTIM2_DTRR           (*(vuint32*)(&__IPSBAR[0x000484]))
0629 #define MCF_DTIM2_DTCR           (*(vuint32*)(&__IPSBAR[0x000488]))
0630 #define MCF_DTIM2_DTCN           (*(vuint32*)(&__IPSBAR[0x00048C]))
0631 #define MCF_DTIM3_DTMR           (*(vuint16*)(&__IPSBAR[0x0004C0]))
0632 #define MCF_DTIM3_DTXMR          (*(vuint8 *)(&__IPSBAR[0x0004C2]))
0633 #define MCF_DTIM3_DTER           (*(vuint8 *)(&__IPSBAR[0x0004C3]))
0634 #define MCF_DTIM3_DTRR           (*(vuint32*)(&__IPSBAR[0x0004C4]))
0635 #define MCF_DTIM3_DTCR           (*(vuint32*)(&__IPSBAR[0x0004C8]))
0636 #define MCF_DTIM3_DTCN           (*(vuint32*)(&__IPSBAR[0x0004CC]))
0637 #define MCF_DTIM_DTMR(x)         (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)]))
0638 #define MCF_DTIM_DTXMR(x)        (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)]))
0639 #define MCF_DTIM_DTER(x)         (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)]))
0640 #define MCF_DTIM_DTRR(x)         (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)]))
0641 #define MCF_DTIM_DTCR(x)         (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)]))
0642 #define MCF_DTIM_DTCN(x)         (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)]))
0643 
0644 /* Bit definitions and macros for MCF_DTIM_DTMR */
0645 #define MCF_DTIM_DTMR_RST        (0x0001)
0646 #define MCF_DTIM_DTMR_CLK(x)     (((x)&0x0003)<<1)
0647 #define MCF_DTIM_DTMR_FRR        (0x0008)
0648 #define MCF_DTIM_DTMR_ORRI       (0x0010)
0649 #define MCF_DTIM_DTMR_OM         (0x0020)
0650 #define MCF_DTIM_DTMR_CE(x)      (((x)&0x0003)<<6)
0651 #define MCF_DTIM_DTMR_PS(x)      (((x)&0x00FF)<<8)
0652 #define MCF_DTIM_DTMR_CE_ANY     (0x00C0)
0653 #define MCF_DTIM_DTMR_CE_FALL    (0x0080)
0654 #define MCF_DTIM_DTMR_CE_RISE    (0x0040)
0655 #define MCF_DTIM_DTMR_CE_NONE    (0x0000)
0656 #define MCF_DTIM_DTMR_CLK_DTIN   (0x0006)
0657 #define MCF_DTIM_DTMR_CLK_DIV16  (0x0004)
0658 #define MCF_DTIM_DTMR_CLK_DIV1   (0x0002)
0659 #define MCF_DTIM_DTMR_CLK_STOP   (0x0000)
0660 
0661 /* Bit definitions and macros for MCF_DTIM_DTXMR */
0662 #define MCF_DTIM_DTXMR_MODE16    (0x01)
0663 #define MCF_DTIM_DTXMR_DMAEN     (0x80)
0664 
0665 /* Bit definitions and macros for MCF_DTIM_DTER */
0666 #define MCF_DTIM_DTER_CAP        (0x01)
0667 #define MCF_DTIM_DTER_REF        (0x02)
0668 
0669 /* Bit definitions and macros for MCF_DTIM_DTRR */
0670 #define MCF_DTIM_DTRR_REF(x)     (((x)&0xFFFFFFFF)<<0)
0671 
0672 /* Bit definitions and macros for MCF_DTIM_DTCR */
0673 #define MCF_DTIM_DTCR_CAP(x)     (((x)&0xFFFFFFFF)<<0)
0674 
0675 /* Bit definitions and macros for MCF_DTIM_DTCN */
0676 #define MCF_DTIM_DTCN_CNT(x)     (((x)&0xFFFFFFFF)<<0)
0677 
0678 /*********************************************************************
0679 *
0680 * Interrupt Controller (INTC)
0681 *
0682 *********************************************************************/
0683 
0684 /* Register read/write macros */
0685 #define MCF_INTC0_IPRH             (*(vuint32*)(&__IPSBAR[0x000C00]))
0686 #define MCF_INTC0_IPRL             (*(vuint32*)(&__IPSBAR[0x000C04]))
0687 #define MCF_INTC0_IMRH             (*(vuint32*)(&__IPSBAR[0x000C08]))
0688 #define MCF_INTC0_IMRL             (*(vuint32*)(&__IPSBAR[0x000C0C]))
0689 #define MCF_INTC0_INTFRCH          (*(vuint32*)(&__IPSBAR[0x000C10]))
0690 #define MCF_INTC0_INTFRCL          (*(vuint32*)(&__IPSBAR[0x000C14]))
0691 #define MCF_INTC0_IRLR             (*(vuint8 *)(&__IPSBAR[0x000C18]))
0692 #define MCF_INTC0_IACKLPR          (*(vuint8 *)(&__IPSBAR[0x000C19]))
0693 #define MCF_INTC0_ICR1             (*(vuint8 *)(&__IPSBAR[0x000C41]))
0694 #define MCF_INTC0_ICR2             (*(vuint8 *)(&__IPSBAR[0x000C42]))
0695 #define MCF_INTC0_ICR3             (*(vuint8 *)(&__IPSBAR[0x000C43]))
0696 #define MCF_INTC0_ICR4             (*(vuint8 *)(&__IPSBAR[0x000C44]))
0697 #define MCF_INTC0_ICR5             (*(vuint8 *)(&__IPSBAR[0x000C45]))
0698 #define MCF_INTC0_ICR6             (*(vuint8 *)(&__IPSBAR[0x000C46]))
0699 #define MCF_INTC0_ICR7             (*(vuint8 *)(&__IPSBAR[0x000C47]))
0700 #define MCF_INTC0_ICR8             (*(vuint8 *)(&__IPSBAR[0x000C48]))
0701 #define MCF_INTC0_ICR9             (*(vuint8 *)(&__IPSBAR[0x000C49]))
0702 #define MCF_INTC0_ICR10            (*(vuint8 *)(&__IPSBAR[0x000C4A]))
0703 #define MCF_INTC0_ICR11            (*(vuint8 *)(&__IPSBAR[0x000C4B]))
0704 #define MCF_INTC0_ICR12            (*(vuint8 *)(&__IPSBAR[0x000C4C]))
0705 #define MCF_INTC0_ICR13            (*(vuint8 *)(&__IPSBAR[0x000C4D]))
0706 #define MCF_INTC0_ICR14            (*(vuint8 *)(&__IPSBAR[0x000C4E]))
0707 #define MCF_INTC0_ICR15            (*(vuint8 *)(&__IPSBAR[0x000C4F]))
0708 #define MCF_INTC0_ICR16            (*(vuint8 *)(&__IPSBAR[0x000C50]))
0709 #define MCF_INTC0_ICR17            (*(vuint8 *)(&__IPSBAR[0x000C51]))
0710 #define MCF_INTC0_ICR18            (*(vuint8 *)(&__IPSBAR[0x000C52]))
0711 #define MCF_INTC0_ICR19            (*(vuint8 *)(&__IPSBAR[0x000C53]))
0712 #define MCF_INTC0_ICR20            (*(vuint8 *)(&__IPSBAR[0x000C54]))
0713 #define MCF_INTC0_ICR21            (*(vuint8 *)(&__IPSBAR[0x000C55]))
0714 #define MCF_INTC0_ICR22            (*(vuint8 *)(&__IPSBAR[0x000C56]))
0715 #define MCF_INTC0_ICR23            (*(vuint8 *)(&__IPSBAR[0x000C57]))
0716 #define MCF_INTC0_ICR24            (*(vuint8 *)(&__IPSBAR[0x000C58]))
0717 #define MCF_INTC0_ICR25            (*(vuint8 *)(&__IPSBAR[0x000C59]))
0718 #define MCF_INTC0_ICR26            (*(vuint8 *)(&__IPSBAR[0x000C5A]))
0719 #define MCF_INTC0_ICR27            (*(vuint8 *)(&__IPSBAR[0x000C5B]))
0720 #define MCF_INTC0_ICR28            (*(vuint8 *)(&__IPSBAR[0x000C5C]))
0721 #define MCF_INTC0_ICR29            (*(vuint8 *)(&__IPSBAR[0x000C5D]))
0722 #define MCF_INTC0_ICR30            (*(vuint8 *)(&__IPSBAR[0x000C5E]))
0723 #define MCF_INTC0_ICR31            (*(vuint8 *)(&__IPSBAR[0x000C5F]))
0724 #define MCF_INTC0_ICR32            (*(vuint8 *)(&__IPSBAR[0x000C60]))
0725 #define MCF_INTC0_ICR33            (*(vuint8 *)(&__IPSBAR[0x000C61]))
0726 #define MCF_INTC0_ICR34            (*(vuint8 *)(&__IPSBAR[0x000C62]))
0727 #define MCF_INTC0_ICR35            (*(vuint8 *)(&__IPSBAR[0x000C63]))
0728 #define MCF_INTC0_ICR36            (*(vuint8 *)(&__IPSBAR[0x000C64]))
0729 #define MCF_INTC0_ICR37            (*(vuint8 *)(&__IPSBAR[0x000C65]))
0730 #define MCF_INTC0_ICR38            (*(vuint8 *)(&__IPSBAR[0x000C66]))
0731 #define MCF_INTC0_ICR39            (*(vuint8 *)(&__IPSBAR[0x000C67]))
0732 #define MCF_INTC0_ICR40            (*(vuint8 *)(&__IPSBAR[0x000C68]))
0733 #define MCF_INTC0_ICR41            (*(vuint8 *)(&__IPSBAR[0x000C69]))
0734 #define MCF_INTC0_ICR42            (*(vuint8 *)(&__IPSBAR[0x000C6A]))
0735 #define MCF_INTC0_ICR43            (*(vuint8 *)(&__IPSBAR[0x000C6B]))
0736 #define MCF_INTC0_ICR44            (*(vuint8 *)(&__IPSBAR[0x000C6C]))
0737 #define MCF_INTC0_ICR45            (*(vuint8 *)(&__IPSBAR[0x000C6D]))
0738 #define MCF_INTC0_ICR46            (*(vuint8 *)(&__IPSBAR[0x000C6E]))
0739 #define MCF_INTC0_ICR47            (*(vuint8 *)(&__IPSBAR[0x000C6F]))
0740 #define MCF_INTC0_ICR48            (*(vuint8 *)(&__IPSBAR[0x000C70]))
0741 #define MCF_INTC0_ICR49            (*(vuint8 *)(&__IPSBAR[0x000C71]))
0742 #define MCF_INTC0_ICR50            (*(vuint8 *)(&__IPSBAR[0x000C72]))
0743 #define MCF_INTC0_ICR51            (*(vuint8 *)(&__IPSBAR[0x000C73]))
0744 #define MCF_INTC0_ICR52            (*(vuint8 *)(&__IPSBAR[0x000C74]))
0745 #define MCF_INTC0_ICR53            (*(vuint8 *)(&__IPSBAR[0x000C75]))
0746 #define MCF_INTC0_ICR54            (*(vuint8 *)(&__IPSBAR[0x000C76]))
0747 #define MCF_INTC0_ICR55            (*(vuint8 *)(&__IPSBAR[0x000C77]))
0748 #define MCF_INTC0_ICR56            (*(vuint8 *)(&__IPSBAR[0x000C78]))
0749 #define MCF_INTC0_ICR57            (*(vuint8 *)(&__IPSBAR[0x000C79]))
0750 #define MCF_INTC0_ICR58            (*(vuint8 *)(&__IPSBAR[0x000C7A]))
0751 #define MCF_INTC0_ICR59            (*(vuint8 *)(&__IPSBAR[0x000C7B]))
0752 #define MCF_INTC0_ICR60            (*(vuint8 *)(&__IPSBAR[0x000C7C]))
0753 #define MCF_INTC0_ICR61            (*(vuint8 *)(&__IPSBAR[0x000C7D]))
0754 #define MCF_INTC0_ICR62            (*(vuint8 *)(&__IPSBAR[0x000C7E]))
0755 #define MCF_INTC0_ICR63            (*(vuint8 *)(&__IPSBAR[0x000C7F]))
0756 #define MCF_INTC0_ICR(x)           (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)]))
0757 #define MCF_INTC0_SWIACK           (*(vuint8 *)(&__IPSBAR[0x000CE0]))
0758 #define MCF_INTC0_L1IACK           (*(vuint8 *)(&__IPSBAR[0x000CE4]))
0759 #define MCF_INTC0_L2IACK           (*(vuint8 *)(&__IPSBAR[0x000CE8]))
0760 #define MCF_INTC0_L3IACK           (*(vuint8 *)(&__IPSBAR[0x000CEC]))
0761 #define MCF_INTC0_L4IACK           (*(vuint8 *)(&__IPSBAR[0x000CF0]))
0762 #define MCF_INTC0_L5IACK           (*(vuint8 *)(&__IPSBAR[0x000CF4]))
0763 #define MCF_INTC0_L6IACK           (*(vuint8 *)(&__IPSBAR[0x000CF8]))
0764 #define MCF_INTC0_L7IACK           (*(vuint8 *)(&__IPSBAR[0x000CFC]))
0765 #define MCF_INTC0_LIACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)]))
0766 #define MCF_INTC1_IPRH             (*(vuint32*)(&__IPSBAR[0x000D00]))
0767 #define MCF_INTC1_IPRL             (*(vuint32*)(&__IPSBAR[0x000D04]))
0768 #define MCF_INTC1_IMRH             (*(vuint32*)(&__IPSBAR[0x000D08]))
0769 #define MCF_INTC1_IMRL             (*(vuint32*)(&__IPSBAR[0x000D0C]))
0770 #define MCF_INTC1_INTFRCH          (*(vuint32*)(&__IPSBAR[0x000D10]))
0771 #define MCF_INTC1_INTFRCL          (*(vuint32*)(&__IPSBAR[0x000D14]))
0772 #define MCF_INTC1_IRLR             (*(vuint8 *)(&__IPSBAR[0x000D18]))
0773 #define MCF_INTC1_IACKLPR          (*(vuint8 *)(&__IPSBAR[0x000D19]))
0774 #define MCF_INTC1_ICR1             (*(vuint8 *)(&__IPSBAR[0x000D41]))
0775 #define MCF_INTC1_ICR2             (*(vuint8 *)(&__IPSBAR[0x000D42]))
0776 #define MCF_INTC1_ICR3             (*(vuint8 *)(&__IPSBAR[0x000D43]))
0777 #define MCF_INTC1_ICR4             (*(vuint8 *)(&__IPSBAR[0x000D44]))
0778 #define MCF_INTC1_ICR5             (*(vuint8 *)(&__IPSBAR[0x000D45]))
0779 #define MCF_INTC1_ICR6             (*(vuint8 *)(&__IPSBAR[0x000D46]))
0780 #define MCF_INTC1_ICR7             (*(vuint8 *)(&__IPSBAR[0x000D47]))
0781 #define MCF_INTC1_ICR8             (*(vuint8 *)(&__IPSBAR[0x000D48]))
0782 #define MCF_INTC1_ICR9             (*(vuint8 *)(&__IPSBAR[0x000D49]))
0783 #define MCF_INTC1_ICR10            (*(vuint8 *)(&__IPSBAR[0x000D4A]))
0784 #define MCF_INTC1_ICR11            (*(vuint8 *)(&__IPSBAR[0x000D4B]))
0785 #define MCF_INTC1_ICR12            (*(vuint8 *)(&__IPSBAR[0x000D4C]))
0786 #define MCF_INTC1_ICR13            (*(vuint8 *)(&__IPSBAR[0x000D4D]))
0787 #define MCF_INTC1_ICR14            (*(vuint8 *)(&__IPSBAR[0x000D4E]))
0788 #define MCF_INTC1_ICR15            (*(vuint8 *)(&__IPSBAR[0x000D4F]))
0789 #define MCF_INTC1_ICR16            (*(vuint8 *)(&__IPSBAR[0x000D50]))
0790 #define MCF_INTC1_ICR17            (*(vuint8 *)(&__IPSBAR[0x000D51]))
0791 #define MCF_INTC1_ICR18            (*(vuint8 *)(&__IPSBAR[0x000D52]))
0792 #define MCF_INTC1_ICR19            (*(vuint8 *)(&__IPSBAR[0x000D53]))
0793 #define MCF_INTC1_ICR20            (*(vuint8 *)(&__IPSBAR[0x000D54]))
0794 #define MCF_INTC1_ICR21            (*(vuint8 *)(&__IPSBAR[0x000D55]))
0795 #define MCF_INTC1_ICR22            (*(vuint8 *)(&__IPSBAR[0x000D56]))
0796 #define MCF_INTC1_ICR23            (*(vuint8 *)(&__IPSBAR[0x000D57]))
0797 #define MCF_INTC1_ICR24            (*(vuint8 *)(&__IPSBAR[0x000D58]))
0798 #define MCF_INTC1_ICR25            (*(vuint8 *)(&__IPSBAR[0x000D59]))
0799 #define MCF_INTC1_ICR26            (*(vuint8 *)(&__IPSBAR[0x000D5A]))
0800 #define MCF_INTC1_ICR27            (*(vuint8 *)(&__IPSBAR[0x000D5B]))
0801 #define MCF_INTC1_ICR28            (*(vuint8 *)(&__IPSBAR[0x000D5C]))
0802 #define MCF_INTC1_ICR29            (*(vuint8 *)(&__IPSBAR[0x000D5D]))
0803 #define MCF_INTC1_ICR30            (*(vuint8 *)(&__IPSBAR[0x000D5E]))
0804 #define MCF_INTC1_ICR31            (*(vuint8 *)(&__IPSBAR[0x000D5F]))
0805 #define MCF_INTC1_ICR32            (*(vuint8 *)(&__IPSBAR[0x000D60]))
0806 #define MCF_INTC1_ICR33            (*(vuint8 *)(&__IPSBAR[0x000D61]))
0807 #define MCF_INTC1_ICR34            (*(vuint8 *)(&__IPSBAR[0x000D62]))
0808 #define MCF_INTC1_ICR35            (*(vuint8 *)(&__IPSBAR[0x000D63]))
0809 #define MCF_INTC1_ICR36            (*(vuint8 *)(&__IPSBAR[0x000D64]))
0810 #define MCF_INTC1_ICR37            (*(vuint8 *)(&__IPSBAR[0x000D65]))
0811 #define MCF_INTC1_ICR38            (*(vuint8 *)(&__IPSBAR[0x000D66]))
0812 #define MCF_INTC1_ICR39            (*(vuint8 *)(&__IPSBAR[0x000D67]))
0813 #define MCF_INTC1_ICR40            (*(vuint8 *)(&__IPSBAR[0x000D68]))
0814 #define MCF_INTC1_ICR41            (*(vuint8 *)(&__IPSBAR[0x000D69]))
0815 #define MCF_INTC1_ICR42            (*(vuint8 *)(&__IPSBAR[0x000D6A]))
0816 #define MCF_INTC1_ICR43            (*(vuint8 *)(&__IPSBAR[0x000D6B]))
0817 #define MCF_INTC1_ICR44            (*(vuint8 *)(&__IPSBAR[0x000D6C]))
0818 #define MCF_INTC1_ICR45            (*(vuint8 *)(&__IPSBAR[0x000D6D]))
0819 #define MCF_INTC1_ICR46            (*(vuint8 *)(&__IPSBAR[0x000D6E]))
0820 #define MCF_INTC1_ICR47            (*(vuint8 *)(&__IPSBAR[0x000D6F]))
0821 #define MCF_INTC1_ICR48            (*(vuint8 *)(&__IPSBAR[0x000D70]))
0822 #define MCF_INTC1_ICR49            (*(vuint8 *)(&__IPSBAR[0x000D71]))
0823 #define MCF_INTC1_ICR50            (*(vuint8 *)(&__IPSBAR[0x000D72]))
0824 #define MCF_INTC1_ICR51            (*(vuint8 *)(&__IPSBAR[0x000D73]))
0825 #define MCF_INTC1_ICR52            (*(vuint8 *)(&__IPSBAR[0x000D74]))
0826 #define MCF_INTC1_ICR53            (*(vuint8 *)(&__IPSBAR[0x000D75]))
0827 #define MCF_INTC1_ICR54            (*(vuint8 *)(&__IPSBAR[0x000D76]))
0828 #define MCF_INTC1_ICR55            (*(vuint8 *)(&__IPSBAR[0x000D77]))
0829 #define MCF_INTC1_ICR56            (*(vuint8 *)(&__IPSBAR[0x000D78]))
0830 #define MCF_INTC1_ICR57            (*(vuint8 *)(&__IPSBAR[0x000D79]))
0831 #define MCF_INTC1_ICR58            (*(vuint8 *)(&__IPSBAR[0x000D7A]))
0832 #define MCF_INTC1_ICR59            (*(vuint8 *)(&__IPSBAR[0x000D7B]))
0833 #define MCF_INTC1_ICR60            (*(vuint8 *)(&__IPSBAR[0x000D7C]))
0834 #define MCF_INTC1_ICR61            (*(vuint8 *)(&__IPSBAR[0x000D7D]))
0835 #define MCF_INTC1_ICR62            (*(vuint8 *)(&__IPSBAR[0x000D7E]))
0836 #define MCF_INTC1_ICR63            (*(vuint8 *)(&__IPSBAR[0x000D7F]))
0837 #define MCF_INTC1_ICR(x)           (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)]))
0838 #define MCF_INTC1_SWIACK           (*(vuint8 *)(&__IPSBAR[0x000DE0]))
0839 #define MCF_INTC1_L1IACK           (*(vuint8 *)(&__IPSBAR[0x000DE4]))
0840 #define MCF_INTC1_L2IACK           (*(vuint8 *)(&__IPSBAR[0x000DE8]))
0841 #define MCF_INTC1_L3IACK           (*(vuint8 *)(&__IPSBAR[0x000DEC]))
0842 #define MCF_INTC1_L4IACK           (*(vuint8 *)(&__IPSBAR[0x000DF0]))
0843 #define MCF_INTC1_L5IACK           (*(vuint8 *)(&__IPSBAR[0x000DF4]))
0844 #define MCF_INTC1_L6IACK           (*(vuint8 *)(&__IPSBAR[0x000DF8]))
0845 #define MCF_INTC1_L7IACK           (*(vuint8 *)(&__IPSBAR[0x000DFC]))
0846 #define MCF_INTC1_LIACK(x)         (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)]))
0847 #define MCF_INTC_IPRH(x)           (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)]))
0848 #define MCF_INTC_IPRL(x)           (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)]))
0849 #define MCF_INTC_IMRH(x)           (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)]))
0850 #define MCF_INTC_IMRL(x)           (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)]))
0851 #define MCF_INTC_INTFRCH(x)        (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)]))
0852 #define MCF_INTC_INTFRCL(x)        (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)]))
0853 #define MCF_INTC_IRLR(x)           (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)]))
0854 #define MCF_INTC_IACKLPR(x)        (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)]))
0855 #define MCF_INTC_ICR1(x)           (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)]))
0856 #define MCF_INTC_ICR2(x)           (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)]))
0857 #define MCF_INTC_ICR3(x)           (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)]))
0858 #define MCF_INTC_ICR4(x)           (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)]))
0859 #define MCF_INTC_ICR5(x)           (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)]))
0860 #define MCF_INTC_ICR6(x)           (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)]))
0861 #define MCF_INTC_ICR7(x)           (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)]))
0862 #define MCF_INTC_ICR8(x)           (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)]))
0863 #define MCF_INTC_ICR9(x)           (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)]))
0864 #define MCF_INTC_ICR10(x)          (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)]))
0865 #define MCF_INTC_ICR11(x)          (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)]))
0866 #define MCF_INTC_ICR12(x)          (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)]))
0867 #define MCF_INTC_ICR13(x)          (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)]))
0868 #define MCF_INTC_ICR14(x)          (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)]))
0869 #define MCF_INTC_ICR15(x)          (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)]))
0870 #define MCF_INTC_ICR16(x)          (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)]))
0871 #define MCF_INTC_ICR17(x)          (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)]))
0872 #define MCF_INTC_ICR18(x)          (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)]))
0873 #define MCF_INTC_ICR19(x)          (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)]))
0874 #define MCF_INTC_ICR20(x)          (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)]))
0875 #define MCF_INTC_ICR21(x)          (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)]))
0876 #define MCF_INTC_ICR22(x)          (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)]))
0877 #define MCF_INTC_ICR23(x)          (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)]))
0878 #define MCF_INTC_ICR24(x)          (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)]))
0879 #define MCF_INTC_ICR25(x)          (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)]))
0880 #define MCF_INTC_ICR26(x)          (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)]))
0881 #define MCF_INTC_ICR27(x)          (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)]))
0882 #define MCF_INTC_ICR28(x)          (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)]))
0883 #define MCF_INTC_ICR29(x)          (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)]))
0884 #define MCF_INTC_ICR30(x)          (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)]))
0885 #define MCF_INTC_ICR31(x)          (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)]))
0886 #define MCF_INTC_ICR32(x)          (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)]))
0887 #define MCF_INTC_ICR33(x)          (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)]))
0888 #define MCF_INTC_ICR34(x)          (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)]))
0889 #define MCF_INTC_ICR35(x)          (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)]))
0890 #define MCF_INTC_ICR36(x)          (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)]))
0891 #define MCF_INTC_ICR37(x)          (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)]))
0892 #define MCF_INTC_ICR38(x)          (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)]))
0893 #define MCF_INTC_ICR39(x)          (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)]))
0894 #define MCF_INTC_ICR40(x)          (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)]))
0895 #define MCF_INTC_ICR41(x)          (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)]))
0896 #define MCF_INTC_ICR42(x)          (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)]))
0897 #define MCF_INTC_ICR43(x)          (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)]))
0898 #define MCF_INTC_ICR44(x)          (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)]))
0899 #define MCF_INTC_ICR45(x)          (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)]))
0900 #define MCF_INTC_ICR46(x)          (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)]))
0901 #define MCF_INTC_ICR47(x)          (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)]))
0902 #define MCF_INTC_ICR48(x)          (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)]))
0903 #define MCF_INTC_ICR49(x)          (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)]))
0904 #define MCF_INTC_ICR50(x)          (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)]))
0905 #define MCF_INTC_ICR51(x)          (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)]))
0906 #define MCF_INTC_ICR52(x)          (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)]))
0907 #define MCF_INTC_ICR53(x)          (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)]))
0908 #define MCF_INTC_ICR54(x)          (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)]))
0909 #define MCF_INTC_ICR55(x)          (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)]))
0910 #define MCF_INTC_ICR56(x)          (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)]))
0911 #define MCF_INTC_ICR57(x)          (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)]))
0912 #define MCF_INTC_ICR58(x)          (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)]))
0913 #define MCF_INTC_ICR59(x)          (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)]))
0914 #define MCF_INTC_ICR60(x)          (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)]))
0915 #define MCF_INTC_ICR61(x)          (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)]))
0916 #define MCF_INTC_ICR62(x)          (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)]))
0917 #define MCF_INTC_ICR63(x)          (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)]))
0918 #define MCF_INTC_SWIACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)]))
0919 #define MCF_INTC_L1IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)]))
0920 #define MCF_INTC_L2IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)]))
0921 #define MCF_INTC_L3IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)]))
0922 #define MCF_INTC_L4IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)]))
0923 #define MCF_INTC_L5IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)]))
0924 #define MCF_INTC_L6IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)]))
0925 #define MCF_INTC_L7IACK(x)         (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)]))
0926 
0927 /* Bit definitions and macros for MCF_INTC_IPRH */
0928 #define MCF_INTC_IPRH_INT32        (0x00000001)
0929 #define MCF_INTC_IPRH_INT33        (0x00000002)
0930 #define MCF_INTC_IPRH_INT34        (0x00000004)
0931 #define MCF_INTC_IPRH_INT35        (0x00000008)
0932 #define MCF_INTC_IPRH_INT36        (0x00000010)
0933 #define MCF_INTC_IPRH_INT37        (0x00000020)
0934 #define MCF_INTC_IPRH_INT38        (0x00000040)
0935 #define MCF_INTC_IPRH_INT39        (0x00000080)
0936 #define MCF_INTC_IPRH_INT40        (0x00000100)
0937 #define MCF_INTC_IPRH_INT41        (0x00000200)
0938 #define MCF_INTC_IPRH_INT42        (0x00000400)
0939 #define MCF_INTC_IPRH_INT43        (0x00000800)
0940 #define MCF_INTC_IPRH_INT44        (0x00001000)
0941 #define MCF_INTC_IPRH_INT45        (0x00002000)
0942 #define MCF_INTC_IPRH_INT46        (0x00004000)
0943 #define MCF_INTC_IPRH_INT47        (0x00008000)
0944 #define MCF_INTC_IPRH_INT48        (0x00010000)
0945 #define MCF_INTC_IPRH_INT49        (0x00020000)
0946 #define MCF_INTC_IPRH_INT50        (0x00040000)
0947 #define MCF_INTC_IPRH_INT51        (0x00080000)
0948 #define MCF_INTC_IPRH_INT52        (0x00100000)
0949 #define MCF_INTC_IPRH_INT53        (0x00200000)
0950 #define MCF_INTC_IPRH_INT54        (0x00400000)
0951 #define MCF_INTC_IPRH_INT55        (0x00800000)
0952 #define MCF_INTC_IPRH_INT56        (0x01000000)
0953 #define MCF_INTC_IPRH_INT57        (0x02000000)
0954 #define MCF_INTC_IPRH_INT58        (0x04000000)
0955 #define MCF_INTC_IPRH_INT59        (0x08000000)
0956 #define MCF_INTC_IPRH_INT60        (0x10000000)
0957 #define MCF_INTC_IPRH_INT61        (0x20000000)
0958 #define MCF_INTC_IPRH_INT62        (0x40000000)
0959 #define MCF_INTC_IPRH_INT63        (0x80000000)
0960 
0961 /* Bit definitions and macros for MCF_INTC_IPRL */
0962 #define MCF_INTC_IPRL_INT1         (0x00000002)
0963 #define MCF_INTC_IPRL_INT2         (0x00000004)
0964 #define MCF_INTC_IPRL_INT3         (0x00000008)
0965 #define MCF_INTC_IPRL_INT4         (0x00000010)
0966 #define MCF_INTC_IPRL_INT5         (0x00000020)
0967 #define MCF_INTC_IPRL_INT6         (0x00000040)
0968 #define MCF_INTC_IPRL_INT7         (0x00000080)
0969 #define MCF_INTC_IPRL_INT8         (0x00000100)
0970 #define MCF_INTC_IPRL_INT9         (0x00000200)
0971 #define MCF_INTC_IPRL_INT10        (0x00000400)
0972 #define MCF_INTC_IPRL_INT11        (0x00000800)
0973 #define MCF_INTC_IPRL_INT12        (0x00001000)
0974 #define MCF_INTC_IPRL_INT13        (0x00002000)
0975 #define MCF_INTC_IPRL_INT14        (0x00004000)
0976 #define MCF_INTC_IPRL_INT15        (0x00008000)
0977 #define MCF_INTC_IPRL_INT16        (0x00010000)
0978 #define MCF_INTC_IPRL_INT17        (0x00020000)
0979 #define MCF_INTC_IPRL_INT18        (0x00040000)
0980 #define MCF_INTC_IPRL_INT19        (0x00080000)
0981 #define MCF_INTC_IPRL_INT20        (0x00100000)
0982 #define MCF_INTC_IPRL_INT21        (0x00200000)
0983 #define MCF_INTC_IPRL_INT22        (0x00400000)
0984 #define MCF_INTC_IPRL_INT23        (0x00800000)
0985 #define MCF_INTC_IPRL_INT24        (0x01000000)
0986 #define MCF_INTC_IPRL_INT25        (0x02000000)
0987 #define MCF_INTC_IPRL_INT26        (0x04000000)
0988 #define MCF_INTC_IPRL_INT27        (0x08000000)
0989 #define MCF_INTC_IPRL_INT28        (0x10000000)
0990 #define MCF_INTC_IPRL_INT29        (0x20000000)
0991 #define MCF_INTC_IPRL_INT30        (0x40000000)
0992 #define MCF_INTC_IPRL_INT31        (0x80000000)
0993 
0994 /* Bit definitions and macros for MCF_INTC_IMRH */
0995 #define MCF_INTC_IMRH_MASK32       (0x00000001)
0996 #define MCF_INTC_IMRH_MASK33       (0x00000002)
0997 #define MCF_INTC_IMRH_MASK34       (0x00000004)
0998 #define MCF_INTC_IMRH_MASK35       (0x00000008)
0999 #define MCF_INTC_IMRH_MASK36       (0x00000010)
1000 #define MCF_INTC_IMRH_MASK37       (0x00000020)
1001 #define MCF_INTC_IMRH_MASK38       (0x00000040)
1002 #define MCF_INTC_IMRH_MASK39       (0x00000080)
1003 #define MCF_INTC_IMRH_MASK40       (0x00000100)
1004 #define MCF_INTC_IMRH_MASK41       (0x00000200)
1005 #define MCF_INTC_IMRH_MASK42       (0x00000400)
1006 #define MCF_INTC_IMRH_MASK43       (0x00000800)
1007 #define MCF_INTC_IMRH_MASK44       (0x00001000)
1008 #define MCF_INTC_IMRH_MASK45       (0x00002000)
1009 #define MCF_INTC_IMRH_MASK46       (0x00004000)
1010 #define MCF_INTC_IMRH_MASK47       (0x00008000)
1011 #define MCF_INTC_IMRH_MASK48       (0x00010000)
1012 #define MCF_INTC_IMRH_MASK49       (0x00020000)
1013 #define MCF_INTC_IMRH_MASK50       (0x00040000)
1014 #define MCF_INTC_IMRH_MASK51       (0x00080000)
1015 #define MCF_INTC_IMRH_MASK52       (0x00100000)
1016 #define MCF_INTC_IMRH_MASK53       (0x00200000)
1017 #define MCF_INTC_IMRH_MASK54       (0x00400000)
1018 #define MCF_INTC_IMRH_MASK55       (0x00800000)
1019 #define MCF_INTC_IMRH_MASK56       (0x01000000)
1020 #define MCF_INTC_IMRH_MASK57       (0x02000000)
1021 #define MCF_INTC_IMRH_MASK58       (0x04000000)
1022 #define MCF_INTC_IMRH_MASK59       (0x08000000)
1023 #define MCF_INTC_IMRH_MASK60       (0x10000000)
1024 #define MCF_INTC_IMRH_MASK61       (0x20000000)
1025 #define MCF_INTC_IMRH_MASK62       (0x40000000)
1026 #define MCF_INTC_IMRH_MASK63       (0x80000000)
1027 
1028 /* Bit definitions and macros for MCF_INTC_IMRL */
1029 #define MCF_INTC_IMRL_MASKALL      (0x00000001)
1030 #define MCF_INTC_IMRL_MASK1        (0x00000002)
1031 #define MCF_INTC_IMRL_MASK2        (0x00000004)
1032 #define MCF_INTC_IMRL_MASK3        (0x00000008)
1033 #define MCF_INTC_IMRL_MASK4        (0x00000010)
1034 #define MCF_INTC_IMRL_MASK5        (0x00000020)
1035 #define MCF_INTC_IMRL_MASK6        (0x00000040)
1036 #define MCF_INTC_IMRL_MASK7        (0x00000080)
1037 #define MCF_INTC_IMRL_MASK8        (0x00000100)
1038 #define MCF_INTC_IMRL_MASK9        (0x00000200)
1039 #define MCF_INTC_IMRL_MASK10       (0x00000400)
1040 #define MCF_INTC_IMRL_MASK11       (0x00000800)
1041 #define MCF_INTC_IMRL_MASK12       (0x00001000)
1042 #define MCF_INTC_IMRL_MASK13       (0x00002000)
1043 #define MCF_INTC_IMRL_MASK14       (0x00004000)
1044 #define MCF_INTC_IMRL_MASK15       (0x00008000)
1045 #define MCF_INTC_IMRL_MASK16       (0x00010000)
1046 #define MCF_INTC_IMRL_MASK17       (0x00020000)
1047 #define MCF_INTC_IMRL_MASK18       (0x00040000)
1048 #define MCF_INTC_IMRL_MASK19       (0x00080000)
1049 #define MCF_INTC_IMRL_MASK20       (0x00100000)
1050 #define MCF_INTC_IMRL_MASK21       (0x00200000)
1051 #define MCF_INTC_IMRL_MASK22       (0x00400000)
1052 #define MCF_INTC_IMRL_MASK23       (0x00800000)
1053 #define MCF_INTC_IMRL_MASK24       (0x01000000)
1054 #define MCF_INTC_IMRL_MASK25       (0x02000000)
1055 #define MCF_INTC_IMRL_MASK26       (0x04000000)
1056 #define MCF_INTC_IMRL_MASK27       (0x08000000)
1057 #define MCF_INTC_IMRL_MASK28       (0x10000000)
1058 #define MCF_INTC_IMRL_MASK29       (0x20000000)
1059 #define MCF_INTC_IMRL_MASK30       (0x40000000)
1060 #define MCF_INTC_IMRL_MASK31       (0x80000000)
1061 
1062 /* Bit definitions and macros for MCF_INTC_INTFRCH */
1063 #define MCF_INTC_INTFRCH_INTFRC32  (0x00000001)
1064 #define MCF_INTC_INTFRCH_INTFRC33  (0x00000002)
1065 #define MCF_INTC_INTFRCH_INTFRC34  (0x00000004)
1066 #define MCF_INTC_INTFRCH_INTFRC35  (0x00000008)
1067 #define MCF_INTC_INTFRCH_INTFRC36  (0x00000010)
1068 #define MCF_INTC_INTFRCH_INTFRC37  (0x00000020)
1069 #define MCF_INTC_INTFRCH_INTFRC38  (0x00000040)
1070 #define MCF_INTC_INTFRCH_INTFRC39  (0x00000080)
1071 #define MCF_INTC_INTFRCH_INTFRC40  (0x00000100)
1072 #define MCF_INTC_INTFRCH_INTFRC41  (0x00000200)
1073 #define MCF_INTC_INTFRCH_INTFRC42  (0x00000400)
1074 #define MCF_INTC_INTFRCH_INTFRC43  (0x00000800)
1075 #define MCF_INTC_INTFRCH_INTFRC44  (0x00001000)
1076 #define MCF_INTC_INTFRCH_INTFRC45  (0x00002000)
1077 #define MCF_INTC_INTFRCH_INTFRC46  (0x00004000)
1078 #define MCF_INTC_INTFRCH_INTFRC47  (0x00008000)
1079 #define MCF_INTC_INTFRCH_INTFRC48  (0x00010000)
1080 #define MCF_INTC_INTFRCH_INTFRC49  (0x00020000)
1081 #define MCF_INTC_INTFRCH_INTFRC50  (0x00040000)
1082 #define MCF_INTC_INTFRCH_INTFRC51  (0x00080000)
1083 #define MCF_INTC_INTFRCH_INTFRC52  (0x00100000)
1084 #define MCF_INTC_INTFRCH_INTFRC53  (0x00200000)
1085 #define MCF_INTC_INTFRCH_INTFRC54  (0x00400000)
1086 #define MCF_INTC_INTFRCH_INTFRC55  (0x00800000)
1087 #define MCF_INTC_INTFRCH_INTFRC56  (0x01000000)
1088 #define MCF_INTC_INTFRCH_INTFRC57  (0x02000000)
1089 #define MCF_INTC_INTFRCH_INTFRC58  (0x04000000)
1090 #define MCF_INTC_INTFRCH_INTFRC59  (0x08000000)
1091 #define MCF_INTC_INTFRCH_INTFRC60  (0x10000000)
1092 #define MCF_INTC_INTFRCH_INTFRC61  (0x20000000)
1093 #define MCF_INTC_INTFRCH_INTFRC62  (0x40000000)
1094 #define MCF_INTC_INTFRCH_INTFRC63  (0x80000000)
1095 
1096 /* Bit definitions and macros for MCF_INTC_INTFRCL */
1097 #define MCF_INTC_INTFRCL_INTFRC1   (0x00000002)
1098 #define MCF_INTC_INTFRCL_INTFRC2   (0x00000004)
1099 #define MCF_INTC_INTFRCL_INTFRC3   (0x00000008)
1100 #define MCF_INTC_INTFRCL_INTFRC4   (0x00000010)
1101 #define MCF_INTC_INTFRCL_INTFRC5   (0x00000020)
1102 #define MCF_INTC_INTFRCL_INTFRC6   (0x00000040)
1103 #define MCF_INTC_INTFRCL_INTFRC7   (0x00000080)
1104 #define MCF_INTC_INTFRCL_INTFRC8   (0x00000100)
1105 #define MCF_INTC_INTFRCL_INTFRC9   (0x00000200)
1106 #define MCF_INTC_INTFRCL_INTFRC10  (0x00000400)
1107 #define MCF_INTC_INTFRCL_INTFRC11  (0x00000800)
1108 #define MCF_INTC_INTFRCL_INTFRC12  (0x00001000)
1109 #define MCF_INTC_INTFRCL_INTFRC13  (0x00002000)
1110 #define MCF_INTC_INTFRCL_INTFRC14  (0x00004000)
1111 #define MCF_INTC_INTFRCL_INTFRC15  (0x00008000)
1112 #define MCF_INTC_INTFRCL_INTFRC16  (0x00010000)
1113 #define MCF_INTC_INTFRCL_INTFRC17  (0x00020000)
1114 #define MCF_INTC_INTFRCL_INTFRC18  (0x00040000)
1115 #define MCF_INTC_INTFRCL_INTFRC19  (0x00080000)
1116 #define MCF_INTC_INTFRCL_INTFRC20  (0x00100000)
1117 #define MCF_INTC_INTFRCL_INTFRC21  (0x00200000)
1118 #define MCF_INTC_INTFRCL_INTFRC22  (0x00400000)
1119 #define MCF_INTC_INTFRCL_INTFRC23  (0x00800000)
1120 #define MCF_INTC_INTFRCL_INTFRC24  (0x01000000)
1121 #define MCF_INTC_INTFRCL_INTFRC25  (0x02000000)
1122 #define MCF_INTC_INTFRCL_INTFRC26  (0x04000000)
1123 #define MCF_INTC_INTFRCL_INTFRC27  (0x08000000)
1124 #define MCF_INTC_INTFRCL_INTFRC28  (0x10000000)
1125 #define MCF_INTC_INTFRCL_INTFRC29  (0x20000000)
1126 #define MCF_INTC_INTFRCL_INTFRC30  (0x40000000)
1127 #define MCF_INTC_INTFRCL_INTFRC31  (0x80000000)
1128 
1129 /* Bit definitions and macros for MCF_INTC_IRLR */
1130 #define MCF_INTC_IRLR_IRQ(x)       (((x)&0x7F)<<1)
1131 
1132 /* Bit definitions and macros for MCF_INTC_IACKLPR */
1133 #define MCF_INTC_IACKLPR_PRI(x)    (((x)&0x0F)<<0)
1134 #define MCF_INTC_IACKLPR_LEVEL(x)  (((x)&0x07)<<4)
1135 
1136 /* Bit definitions and macros for MCF_INTC_ICR */
1137 #define MCF_INTC_ICR_IP(x)         (((x)&0x07)<<0)
1138 #define MCF_INTC_ICR_IL(x)         (((x)&0x07)<<3)
1139 
1140 /* Bit definitions and macros for MCF_INTC_SWIACK */
1141 #define MCF_INTC_SWIACK_VECTOR(x)  (((x)&0xFF)<<0)
1142 
1143 /* Bit definitions and macros for MCF_INTC_LIACK */
1144 #define MCF_INTC_LIACK_VECTOR(x)   (((x)&0xFF)<<0)
1145 
1146 /*********************************************************************
1147 *
1148 * General Purpose I/O (GPIO)
1149 *
1150 *********************************************************************/
1151 
1152 /* Register read/write macros */
1153 #define MCF_GPIO_PORTNQ                (*(vuint8 *)(&__IPSBAR[0x100008]))
1154 #define MCF_GPIO_PORTAN                (*(vuint8 *)(&__IPSBAR[0x10000A]))
1155 #define MCF_GPIO_PORTAS                (*(vuint8 *)(&__IPSBAR[0x10000B]))
1156 #define MCF_GPIO_PORTQS                (*(vuint8 *)(&__IPSBAR[0x10000C]))
1157 #define MCF_GPIO_PORTTA                (*(vuint8 *)(&__IPSBAR[0x10000E]))
1158 #define MCF_GPIO_PORTTC                (*(vuint8 *)(&__IPSBAR[0x10000F]))
1159 #define MCF_GPIO_PORTTD                (*(vuint8 *)(&__IPSBAR[0x100010]))
1160 #define MCF_GPIO_PORTUA                (*(vuint8 *)(&__IPSBAR[0x100011]))
1161 #define MCF_GPIO_PORTUB                (*(vuint8 *)(&__IPSBAR[0x100012]))
1162 #define MCF_GPIO_PORTUC                (*(vuint8 *)(&__IPSBAR[0x100013]))
1163 #define MCF_GPIO_PORTDD                (*(vuint8 *)(&__IPSBAR[0x100014]))
1164 #define MCF_GPIO_PORTLD                (*(vuint8 *)(&__IPSBAR[0x100015]))
1165 #define MCF_GPIO_PORTGP                (*(vuint8 *)(&__IPSBAR[0x100016]))
1166 #define MCF_GPIO_DDRNQ                 (*(vuint8 *)(&__IPSBAR[0x100020]))
1167 #define MCF_GPIO_DDRAN                 (*(vuint8 *)(&__IPSBAR[0x100022]))
1168 #define MCF_GPIO_DDRAS                 (*(vuint8 *)(&__IPSBAR[0x100023]))
1169 #define MCF_GPIO_DDRQS                 (*(vuint8 *)(&__IPSBAR[0x100024]))
1170 #define MCF_GPIO_DDRTA                 (*(vuint8 *)(&__IPSBAR[0x100026]))
1171 #define MCF_GPIO_DDRTC                 (*(vuint8 *)(&__IPSBAR[0x100027]))
1172 #define MCF_GPIO_DDRTD                 (*(vuint8 *)(&__IPSBAR[0x100028]))
1173 #define MCF_GPIO_DDRUA                 (*(vuint8 *)(&__IPSBAR[0x100029]))
1174 #define MCF_GPIO_DDRUB                 (*(vuint8 *)(&__IPSBAR[0x10002A]))
1175 #define MCF_GPIO_DDRUC                 (*(vuint8 *)(&__IPSBAR[0x10002B]))
1176 #define MCF_GPIO_DDRDD                 (*(vuint8 *)(&__IPSBAR[0x10002C]))
1177 #define MCF_GPIO_DDRLD                 (*(vuint8 *)(&__IPSBAR[0x10002D]))
1178 #define MCF_GPIO_DDRGP                 (*(vuint8 *)(&__IPSBAR[0x10002E]))
1179 #define MCF_GPIO_SETNQ                 (*(vuint8 *)(&__IPSBAR[0x100038]))
1180 #define MCF_GPIO_SETAN                 (*(vuint8 *)(&__IPSBAR[0x10003A]))
1181 #define MCF_GPIO_SETAS                 (*(vuint8 *)(&__IPSBAR[0x10003B]))
1182 #define MCF_GPIO_SETQS                 (*(vuint8 *)(&__IPSBAR[0x10003C]))
1183 #define MCF_GPIO_SETTA                 (*(vuint8 *)(&__IPSBAR[0x10003E]))
1184 #define MCF_GPIO_SETTC                 (*(vuint8 *)(&__IPSBAR[0x10003F]))
1185 #define MCF_GPIO_SETTD                 (*(vuint8 *)(&__IPSBAR[0x100040]))
1186 #define MCF_GPIO_SETUA                 (*(vuint8 *)(&__IPSBAR[0x100041]))
1187 #define MCF_GPIO_SETUB                 (*(vuint8 *)(&__IPSBAR[0x100042]))
1188 #define MCF_GPIO_SETUC                 (*(vuint8 *)(&__IPSBAR[0x100043]))
1189 #define MCF_GPIO_SETDD                 (*(vuint8 *)(&__IPSBAR[0x100044]))
1190 #define MCF_GPIO_SETLD                 (*(vuint8 *)(&__IPSBAR[0x100045]))
1191 #define MCF_GPIO_SETGP                 (*(vuint8 *)(&__IPSBAR[0x100046]))
1192 #define MCF_GPIO_CLRNQ                 (*(vuint8 *)(&__IPSBAR[0x100050]))
1193 #define MCF_GPIO_CLRAN                 (*(vuint8 *)(&__IPSBAR[0x100052]))
1194 #define MCF_GPIO_CLRAS                 (*(vuint8 *)(&__IPSBAR[0x100053]))
1195 #define MCF_GPIO_CLRQS                 (*(vuint8 *)(&__IPSBAR[0x100054]))
1196 #define MCF_GPIO_CLRTA                 (*(vuint8 *)(&__IPSBAR[0x100056]))
1197 #define MCF_GPIO_CLRTC                 (*(vuint8 *)(&__IPSBAR[0x100057]))
1198 #define MCF_GPIO_CLRTD                 (*(vuint8 *)(&__IPSBAR[0x100058]))
1199 #define MCF_GPIO_CLRUA                 (*(vuint8 *)(&__IPSBAR[0x100059]))
1200 #define MCF_GPIO_CLRUB                 (*(vuint8 *)(&__IPSBAR[0x10005A]))
1201 #define MCF_GPIO_CLRUC                 (*(vuint8 *)(&__IPSBAR[0x10005B]))
1202 #define MCF_GPIO_CLRDD                 (*(vuint8 *)(&__IPSBAR[0x10005C]))
1203 #define MCF_GPIO_CLRLD                 (*(vuint8 *)(&__IPSBAR[0x10005D]))
1204 #define MCF_GPIO_CLRGP                 (*(vuint8 *)(&__IPSBAR[0x10005E]))
1205 #define MCF_GPIO_PNQPAR                (*(vuint16*)(&__IPSBAR[0x100068]))
1206 #define MCF_GPIO_PANPAR                (*(vuint8 *)(&__IPSBAR[0x10006A]))
1207 #define MCF_GPIO_PASPAR                (*(vuint8 *)(&__IPSBAR[0x10006B]))
1208 #define MCF_GPIO_PQSPAR                (*(vuint16*)(&__IPSBAR[0x10006C]))
1209 #define MCF_GPIO_PTAPAR                (*(vuint8 *)(&__IPSBAR[0x10006E]))
1210 #define MCF_GPIO_PTCPAR                (*(vuint8 *)(&__IPSBAR[0x10006F]))
1211 #define MCF_GPIO_PTDPAR                (*(vuint8 *)(&__IPSBAR[0x100070]))
1212 #define MCF_GPIO_PUAPAR                (*(vuint8 *)(&__IPSBAR[0x100071]))
1213 #define MCF_GPIO_PUBPAR                (*(vuint8 *)(&__IPSBAR[0x100072]))
1214 #define MCF_GPIO_PUCPAR                (*(vuint8 *)(&__IPSBAR[0x100073]))
1215 #define MCF_GPIO_PDDPAR                (*(vuint8 *)(&__IPSBAR[0x100074]))
1216 #define MCF_GPIO_PLDPAR                (*(vuint8 *)(&__IPSBAR[0x100075]))
1217 #define MCF_GPIO_PGPPAR                (*(vuint8 *)(&__IPSBAR[0x100076]))
1218 #define MCF_GPIO_PWOR                  (*(vuint16*)(&__IPSBAR[0x100078]))
1219 #define MCF_GPIO_PDSRH                 (*(vuint16*)(&__IPSBAR[0x10007A]))
1220 #define MCF_GPIO_PDSRL                 (*(vuint32*)(&__IPSBAR[0x10007C]))
1221 
1222 /* Bit definitions and macros for MCF_GPIO_PORTNQ */
1223 #define MCF_GPIO_PORTNQ_PORTNQ0        (0x01)
1224 #define MCF_GPIO_PORTNQ_PORTNQ1        (0x02)
1225 #define MCF_GPIO_PORTNQ_PORTNQ2        (0x04)
1226 #define MCF_GPIO_PORTNQ_PORTNQ3        (0x08)
1227 #define MCF_GPIO_PORTNQ_PORTNQ4        (0x10)
1228 #define MCF_GPIO_PORTNQ_PORTNQ5        (0x20)
1229 #define MCF_GPIO_PORTNQ_PORTNQ6        (0x40)
1230 #define MCF_GPIO_PORTNQ_PORTNQ7        (0x80)
1231 
1232 /* Bit definitions and macros for MCF_GPIO_PORTAN */
1233 #define MCF_GPIO_PORTAN_PORTAN0        (0x01)
1234 #define MCF_GPIO_PORTAN_PORTAN1        (0x02)
1235 #define MCF_GPIO_PORTAN_PORTAN2        (0x04)
1236 #define MCF_GPIO_PORTAN_PORTAN3        (0x08)
1237 #define MCF_GPIO_PORTAN_PORTAN4        (0x10)
1238 #define MCF_GPIO_PORTAN_PORTAN5        (0x20)
1239 #define MCF_GPIO_PORTAN_PORTAN6        (0x40)
1240 #define MCF_GPIO_PORTAN_PORTAN7        (0x80)
1241 
1242 /* Bit definitions and macros for MCF_GPIO_PORTAS */
1243 #define MCF_GPIO_PORTAS_PORTAS0        (0x01)
1244 #define MCF_GPIO_PORTAS_PORTAS1        (0x02)
1245 #define MCF_GPIO_PORTAS_PORTAS2        (0x04)
1246 #define MCF_GPIO_PORTAS_PORTAS3        (0x08)
1247 #define MCF_GPIO_PORTAS_PORTAS4        (0x10)
1248 #define MCF_GPIO_PORTAS_PORTAS5        (0x20)
1249 #define MCF_GPIO_PORTAS_PORTAS6        (0x40)
1250 #define MCF_GPIO_PORTAS_PORTAS7        (0x80)
1251 
1252 /* Bit definitions and macros for MCF_GPIO_PORTQS */
1253 #define MCF_GPIO_PORTQS_PORTQS0        (0x01)
1254 #define MCF_GPIO_PORTQS_PORTQS1        (0x02)
1255 #define MCF_GPIO_PORTQS_PORTQS2        (0x04)
1256 #define MCF_GPIO_PORTQS_PORTQS3        (0x08)
1257 #define MCF_GPIO_PORTQS_PORTQS4        (0x10)
1258 #define MCF_GPIO_PORTQS_PORTQS5        (0x20)
1259 #define MCF_GPIO_PORTQS_PORTQS6        (0x40)
1260 #define MCF_GPIO_PORTQS_PORTQS7        (0x80)
1261 
1262 /* Bit definitions and macros for MCF_GPIO_PORTTA */
1263 #define MCF_GPIO_PORTTA_PORTTA0        (0x01)
1264 #define MCF_GPIO_PORTTA_PORTTA1        (0x02)
1265 #define MCF_GPIO_PORTTA_PORTTA2        (0x04)
1266 #define MCF_GPIO_PORTTA_PORTTA3        (0x08)
1267 #define MCF_GPIO_PORTTA_PORTTA4        (0x10)
1268 #define MCF_GPIO_PORTTA_PORTTA5        (0x20)
1269 #define MCF_GPIO_PORTTA_PORTTA6        (0x40)
1270 #define MCF_GPIO_PORTTA_PORTTA7        (0x80)
1271 
1272 /* Bit definitions and macros for MCF_GPIO_PORTTC */
1273 #define MCF_GPIO_PORTTC_PORTTC0        (0x01)
1274 #define MCF_GPIO_PORTTC_PORTTC1        (0x02)
1275 #define MCF_GPIO_PORTTC_PORTTC2        (0x04)
1276 #define MCF_GPIO_PORTTC_PORTTC3        (0x08)
1277 #define MCF_GPIO_PORTTC_PORTTC4        (0x10)
1278 #define MCF_GPIO_PORTTC_PORTTC5        (0x20)
1279 #define MCF_GPIO_PORTTC_PORTTC6        (0x40)
1280 #define MCF_GPIO_PORTTC_PORTTC7        (0x80)
1281 
1282 /* Bit definitions and macros for MCF_GPIO_PORTTD */
1283 #define MCF_GPIO_PORTTD_PORTTD0        (0x01)
1284 #define MCF_GPIO_PORTTD_PORTTD1        (0x02)
1285 #define MCF_GPIO_PORTTD_PORTTD2        (0x04)
1286 #define MCF_GPIO_PORTTD_PORTTD3        (0x08)
1287 #define MCF_GPIO_PORTTD_PORTTD4        (0x10)
1288 #define MCF_GPIO_PORTTD_PORTTD5        (0x20)
1289 #define MCF_GPIO_PORTTD_PORTTD6        (0x40)
1290 #define MCF_GPIO_PORTTD_PORTTD7        (0x80)
1291 
1292 /* Bit definitions and macros for MCF_GPIO_PORTUA */
1293 #define MCF_GPIO_PORTUA_PORTUA0        (0x01)
1294 #define MCF_GPIO_PORTUA_PORTUA1        (0x02)
1295 #define MCF_GPIO_PORTUA_PORTUA2        (0x04)
1296 #define MCF_GPIO_PORTUA_PORTUA3        (0x08)
1297 #define MCF_GPIO_PORTUA_PORTUA4        (0x10)
1298 #define MCF_GPIO_PORTUA_PORTUA5        (0x20)
1299 #define MCF_GPIO_PORTUA_PORTUA6        (0x40)
1300 #define MCF_GPIO_PORTUA_PORTUA7        (0x80)
1301 
1302 /* Bit definitions and macros for MCF_GPIO_PORTUB */
1303 #define MCF_GPIO_PORTUB_PORTUB0        (0x01)
1304 #define MCF_GPIO_PORTUB_PORTUB1        (0x02)
1305 #define MCF_GPIO_PORTUB_PORTUB2        (0x04)
1306 #define MCF_GPIO_PORTUB_PORTUB3        (0x08)
1307 #define MCF_GPIO_PORTUB_PORTUB4        (0x10)
1308 #define MCF_GPIO_PORTUB_PORTUB5        (0x20)
1309 #define MCF_GPIO_PORTUB_PORTUB6        (0x40)
1310 #define MCF_GPIO_PORTUB_PORTUB7        (0x80)
1311 
1312 /* Bit definitions and macros for MCF_GPIO_PORTUC */
1313 #define MCF_GPIO_PORTUC_PORTUC0        (0x01)
1314 #define MCF_GPIO_PORTUC_PORTUC1        (0x02)
1315 #define MCF_GPIO_PORTUC_PORTUC2        (0x04)
1316 #define MCF_GPIO_PORTUC_PORTUC3        (0x08)
1317 #define MCF_GPIO_PORTUC_PORTUC4        (0x10)
1318 #define MCF_GPIO_PORTUC_PORTUC5        (0x20)
1319 #define MCF_GPIO_PORTUC_PORTUC6        (0x40)
1320 #define MCF_GPIO_PORTUC_PORTUC7        (0x80)
1321 
1322 /* Bit definitions and macros for MCF_GPIO_PORTDD */
1323 #define MCF_GPIO_PORTDD_PORTDD0        (0x01)
1324 #define MCF_GPIO_PORTDD_PORTDD1        (0x02)
1325 #define MCF_GPIO_PORTDD_PORTDD2        (0x04)
1326 #define MCF_GPIO_PORTDD_PORTDD3        (0x08)
1327 #define MCF_GPIO_PORTDD_PORTDD4        (0x10)
1328 #define MCF_GPIO_PORTDD_PORTDD5        (0x20)
1329 #define MCF_GPIO_PORTDD_PORTDD6        (0x40)
1330 #define MCF_GPIO_PORTDD_PORTDD7        (0x80)
1331 
1332 /* Bit definitions and macros for MCF_GPIO_PORTLD */
1333 #define MCF_GPIO_PORTLD_PORTLD0        (0x01)
1334 #define MCF_GPIO_PORTLD_PORTLD1        (0x02)
1335 #define MCF_GPIO_PORTLD_PORTLD2        (0x04)
1336 #define MCF_GPIO_PORTLD_PORTLD3        (0x08)
1337 #define MCF_GPIO_PORTLD_PORTLD4        (0x10)
1338 #define MCF_GPIO_PORTLD_PORTLD5        (0x20)
1339 #define MCF_GPIO_PORTLD_PORTLD6        (0x40)
1340 #define MCF_GPIO_PORTLD_PORTLD7        (0x80)
1341 
1342 /* Bit definitions and macros for MCF_GPIO_PORTGP */
1343 #define MCF_GPIO_PORTGP_PORTGP0        (0x01)
1344 #define MCF_GPIO_PORTGP_PORTGP1        (0x02)
1345 #define MCF_GPIO_PORTGP_PORTGP2        (0x04)
1346 #define MCF_GPIO_PORTGP_PORTGP3        (0x08)
1347 #define MCF_GPIO_PORTGP_PORTGP4        (0x10)
1348 #define MCF_GPIO_PORTGP_PORTGP5        (0x20)
1349 #define MCF_GPIO_PORTGP_PORTGP6        (0x40)
1350 #define MCF_GPIO_PORTGP_PORTGP7        (0x80)
1351 
1352 /* Bit definitions and macros for MCF_GPIO_DDRNQ */
1353 #define MCF_GPIO_DDRNQ_DDRNQ0          (0x01)
1354 #define MCF_GPIO_DDRNQ_DDRNQ1          (0x02)
1355 #define MCF_GPIO_DDRNQ_DDRNQ2          (0x04)
1356 #define MCF_GPIO_DDRNQ_DDRNQ3          (0x08)
1357 #define MCF_GPIO_DDRNQ_DDRNQ4          (0x10)
1358 #define MCF_GPIO_DDRNQ_DDRNQ5          (0x20)
1359 #define MCF_GPIO_DDRNQ_DDRNQ6          (0x40)
1360 #define MCF_GPIO_DDRNQ_DDRNQ7          (0x80)
1361 
1362 /* Bit definitions and macros for MCF_GPIO_DDRAN */
1363 #define MCF_GPIO_DDRAN_DDRAN0          (0x01)
1364 #define MCF_GPIO_DDRAN_DDRAN1          (0x02)
1365 #define MCF_GPIO_DDRAN_DDRAN2          (0x04)
1366 #define MCF_GPIO_DDRAN_DDRAN3          (0x08)
1367 #define MCF_GPIO_DDRAN_DDRAN4          (0x10)
1368 #define MCF_GPIO_DDRAN_DDRAN5          (0x20)
1369 #define MCF_GPIO_DDRAN_DDRAN6          (0x40)
1370 #define MCF_GPIO_DDRAN_DDRAN7          (0x80)
1371 
1372 /* Bit definitions and macros for MCF_GPIO_DDRAS */
1373 #define MCF_GPIO_DDRAS_DDRAS0          (0x01)
1374 #define MCF_GPIO_DDRAS_DDRAS1          (0x02)
1375 #define MCF_GPIO_DDRAS_DDRAS2          (0x04)
1376 #define MCF_GPIO_DDRAS_DDRAS3          (0x08)
1377 #define MCF_GPIO_DDRAS_DDRAS4          (0x10)
1378 #define MCF_GPIO_DDRAS_DDRAS5          (0x20)
1379 #define MCF_GPIO_DDRAS_DDRAS6          (0x40)
1380 #define MCF_GPIO_DDRAS_DDRAS7          (0x80)
1381 
1382 /* Bit definitions and macros for MCF_GPIO_DDRQS */
1383 #define MCF_GPIO_DDRQS_DDRQS0          (0x01)
1384 #define MCF_GPIO_DDRQS_DDRQS1          (0x02)
1385 #define MCF_GPIO_DDRQS_DDRQS2          (0x04)
1386 #define MCF_GPIO_DDRQS_DDRQS3          (0x08)
1387 #define MCF_GPIO_DDRQS_DDRQS4          (0x10)
1388 #define MCF_GPIO_DDRQS_DDRQS5          (0x20)
1389 #define MCF_GPIO_DDRQS_DDRQS6          (0x40)
1390 #define MCF_GPIO_DDRQS_DDRQS7          (0x80)
1391 
1392 /* Bit definitions and macros for MCF_GPIO_DDRTA */
1393 #define MCF_GPIO_DDRTA_DDRTA0          (0x01)
1394 #define MCF_GPIO_DDRTA_DDRTA1          (0x02)
1395 #define MCF_GPIO_DDRTA_DDRTA2          (0x04)
1396 #define MCF_GPIO_DDRTA_DDRTA3          (0x08)
1397 #define MCF_GPIO_DDRTA_DDRTA4          (0x10)
1398 #define MCF_GPIO_DDRTA_DDRTA5          (0x20)
1399 #define MCF_GPIO_DDRTA_DDRTA6          (0x40)
1400 #define MCF_GPIO_DDRTA_DDRTA7          (0x80)
1401 
1402 /* Bit definitions and macros for MCF_GPIO_DDRTC */
1403 #define MCF_GPIO_DDRTC_DDRTC0          (0x01)
1404 #define MCF_GPIO_DDRTC_DDRTC1          (0x02)
1405 #define MCF_GPIO_DDRTC_DDRTC2          (0x04)
1406 #define MCF_GPIO_DDRTC_DDRTC3          (0x08)
1407 #define MCF_GPIO_DDRTC_DDRTC4          (0x10)
1408 #define MCF_GPIO_DDRTC_DDRTC5          (0x20)
1409 #define MCF_GPIO_DDRTC_DDRTC6          (0x40)
1410 #define MCF_GPIO_DDRTC_DDRTC7          (0x80)
1411 
1412 /* Bit definitions and macros for MCF_GPIO_DDRTD */
1413 #define MCF_GPIO_DDRTD_DDRTD0          (0x01)
1414 #define MCF_GPIO_DDRTD_DDRTD1          (0x02)
1415 #define MCF_GPIO_DDRTD_DDRTD2          (0x04)
1416 #define MCF_GPIO_DDRTD_DDRTD3          (0x08)
1417 #define MCF_GPIO_DDRTD_DDRTD4          (0x10)
1418 #define MCF_GPIO_DDRTD_DDRTD5          (0x20)
1419 #define MCF_GPIO_DDRTD_DDRTD6          (0x40)
1420 #define MCF_GPIO_DDRTD_DDRTD7          (0x80)
1421 
1422 /* Bit definitions and macros for MCF_GPIO_DDRUA */
1423 #define MCF_GPIO_DDRUA_DDRUA0          (0x01)
1424 #define MCF_GPIO_DDRUA_DDRUA1          (0x02)
1425 #define MCF_GPIO_DDRUA_DDRUA2          (0x04)
1426 #define MCF_GPIO_DDRUA_DDRUA3          (0x08)
1427 #define MCF_GPIO_DDRUA_DDRUA4          (0x10)
1428 #define MCF_GPIO_DDRUA_DDRUA5          (0x20)
1429 #define MCF_GPIO_DDRUA_DDRUA6          (0x40)
1430 #define MCF_GPIO_DDRUA_DDRUA7          (0x80)
1431 
1432 /* Bit definitions and macros for MCF_GPIO_DDRUB */
1433 #define MCF_GPIO_DDRUB_DDRUB0          (0x01)
1434 #define MCF_GPIO_DDRUB_DDRUB1          (0x02)
1435 #define MCF_GPIO_DDRUB_DDRUB2          (0x04)
1436 #define MCF_GPIO_DDRUB_DDRUB3          (0x08)
1437 #define MCF_GPIO_DDRUB_DDRUB4          (0x10)
1438 #define MCF_GPIO_DDRUB_DDRUB5          (0x20)
1439 #define MCF_GPIO_DDRUB_DDRUB6          (0x40)
1440 #define MCF_GPIO_DDRUB_DDRUB7          (0x80)
1441 
1442 /* Bit definitions and macros for MCF_GPIO_DDRUC */
1443 #define MCF_GPIO_DDRUC_DDRUC0          (0x01)
1444 #define MCF_GPIO_DDRUC_DDRUC1          (0x02)
1445 #define MCF_GPIO_DDRUC_DDRUC2          (0x04)
1446 #define MCF_GPIO_DDRUC_DDRUC3          (0x08)
1447 #define MCF_GPIO_DDRUC_DDRUC4          (0x10)
1448 #define MCF_GPIO_DDRUC_DDRUC5          (0x20)
1449 #define MCF_GPIO_DDRUC_DDRUC6          (0x40)
1450 #define MCF_GPIO_DDRUC_DDRUC7          (0x80)
1451 
1452 /* Bit definitions and macros for MCF_GPIO_DDRDD */
1453 #define MCF_GPIO_DDRDD_DDRDD0          (0x01)
1454 #define MCF_GPIO_DDRDD_DDRDD1          (0x02)
1455 #define MCF_GPIO_DDRDD_DDRDD2          (0x04)
1456 #define MCF_GPIO_DDRDD_DDRDD3          (0x08)
1457 #define MCF_GPIO_DDRDD_DDRDD4          (0x10)
1458 #define MCF_GPIO_DDRDD_DDRDD5          (0x20)
1459 #define MCF_GPIO_DDRDD_DDRDD6          (0x40)
1460 #define MCF_GPIO_DDRDD_DDRDD7          (0x80)
1461 
1462 /* Bit definitions and macros for MCF_GPIO_DDRLD */
1463 #define MCF_GPIO_DDRLD_DDRLD0          (0x01)
1464 #define MCF_GPIO_DDRLD_DDRLD1          (0x02)
1465 #define MCF_GPIO_DDRLD_DDRLD2          (0x04)
1466 #define MCF_GPIO_DDRLD_DDRLD3          (0x08)
1467 #define MCF_GPIO_DDRLD_DDRLD4          (0x10)
1468 #define MCF_GPIO_DDRLD_DDRLD5          (0x20)
1469 #define MCF_GPIO_DDRLD_DDRLD6          (0x40)
1470 #define MCF_GPIO_DDRLD_DDRLD7          (0x80)
1471 
1472 /* Bit definitions and macros for MCF_GPIO_DDRGP */
1473 #define MCF_GPIO_DDRGP_DDRGP0          (0x01)
1474 #define MCF_GPIO_DDRGP_DDRGP1          (0x02)
1475 #define MCF_GPIO_DDRGP_DDRGP2          (0x04)
1476 #define MCF_GPIO_DDRGP_DDRGP3          (0x08)
1477 #define MCF_GPIO_DDRGP_DDRGP4          (0x10)
1478 #define MCF_GPIO_DDRGP_DDRGP5          (0x20)
1479 #define MCF_GPIO_DDRGP_DDRGP6          (0x40)
1480 #define MCF_GPIO_DDRGP_DDRGP7          (0x80)
1481 
1482 /* Bit definitions and macros for MCF_GPIO_SETNQ */
1483 #define MCF_GPIO_SETNQ_SETNQ0          (0x01)
1484 #define MCF_GPIO_SETNQ_SETNQ1          (0x02)
1485 #define MCF_GPIO_SETNQ_SETNQ2          (0x04)
1486 #define MCF_GPIO_SETNQ_SETNQ3          (0x08)
1487 #define MCF_GPIO_SETNQ_SETNQ4          (0x10)
1488 #define MCF_GPIO_SETNQ_SETNQ5          (0x20)
1489 #define MCF_GPIO_SETNQ_SETNQ6          (0x40)
1490 #define MCF_GPIO_SETNQ_SETNQ7          (0x80)
1491 
1492 /* Bit definitions and macros for MCF_GPIO_SETAN */
1493 #define MCF_GPIO_SETAN_SETAN0          (0x01)
1494 #define MCF_GPIO_SETAN_SETAN1          (0x02)
1495 #define MCF_GPIO_SETAN_SETAN2          (0x04)
1496 #define MCF_GPIO_SETAN_SETAN3          (0x08)
1497 #define MCF_GPIO_SETAN_SETAN4          (0x10)
1498 #define MCF_GPIO_SETAN_SETAN5          (0x20)
1499 #define MCF_GPIO_SETAN_SETAN6          (0x40)
1500 #define MCF_GPIO_SETAN_SETAN7          (0x80)
1501 
1502 /* Bit definitions and macros for MCF_GPIO_SETAS */
1503 #define MCF_GPIO_SETAS_SETAS0          (0x01)
1504 #define MCF_GPIO_SETAS_SETAS1          (0x02)
1505 #define MCF_GPIO_SETAS_SETAS2          (0x04)
1506 #define MCF_GPIO_SETAS_SETAS3          (0x08)
1507 #define MCF_GPIO_SETAS_SETAS4          (0x10)
1508 #define MCF_GPIO_SETAS_SETAS5          (0x20)
1509 #define MCF_GPIO_SETAS_SETAS6          (0x40)
1510 #define MCF_GPIO_SETAS_SETAS7          (0x80)
1511 
1512 /* Bit definitions and macros for MCF_GPIO_SETQS */
1513 #define MCF_GPIO_SETQS_SETQS0          (0x01)
1514 #define MCF_GPIO_SETQS_SETQS1          (0x02)
1515 #define MCF_GPIO_SETQS_SETQS2          (0x04)
1516 #define MCF_GPIO_SETQS_SETQS3          (0x08)
1517 #define MCF_GPIO_SETQS_SETQS4          (0x10)
1518 #define MCF_GPIO_SETQS_SETQS5          (0x20)
1519 #define MCF_GPIO_SETQS_SETQS6          (0x40)
1520 #define MCF_GPIO_SETQS_SETQS7          (0x80)
1521 
1522 /* Bit definitions and macros for MCF_GPIO_SETTA */
1523 #define MCF_GPIO_SETTA_SETTA0          (0x01)
1524 #define MCF_GPIO_SETTA_SETTA1          (0x02)
1525 #define MCF_GPIO_SETTA_SETTA2          (0x04)
1526 #define MCF_GPIO_SETTA_SETTA3          (0x08)
1527 #define MCF_GPIO_SETTA_SETTA4          (0x10)
1528 #define MCF_GPIO_SETTA_SETTA5          (0x20)
1529 #define MCF_GPIO_SETTA_SETTA6          (0x40)
1530 #define MCF_GPIO_SETTA_SETTA7          (0x80)
1531 
1532 /* Bit definitions and macros for MCF_GPIO_SETTC */
1533 #define MCF_GPIO_SETTC_SETTC0          (0x01)
1534 #define MCF_GPIO_SETTC_SETTC1          (0x02)
1535 #define MCF_GPIO_SETTC_SETTC2          (0x04)
1536 #define MCF_GPIO_SETTC_SETTC3          (0x08)
1537 #define MCF_GPIO_SETTC_SETTC4          (0x10)
1538 #define MCF_GPIO_SETTC_SETTC5          (0x20)
1539 #define MCF_GPIO_SETTC_SETTC6          (0x40)
1540 #define MCF_GPIO_SETTC_SETTC7          (0x80)
1541 
1542 /* Bit definitions and macros for MCF_GPIO_SETTD */
1543 #define MCF_GPIO_SETTD_SETTD0          (0x01)
1544 #define MCF_GPIO_SETTD_SETTD1          (0x02)
1545 #define MCF_GPIO_SETTD_SETTD2          (0x04)
1546 #define MCF_GPIO_SETTD_SETTD3          (0x08)
1547 #define MCF_GPIO_SETTD_SETTD4          (0x10)
1548 #define MCF_GPIO_SETTD_SETTD5          (0x20)
1549 #define MCF_GPIO_SETTD_SETTD6          (0x40)
1550 #define MCF_GPIO_SETTD_SETTD7          (0x80)
1551 
1552 /* Bit definitions and macros for MCF_GPIO_SETUA */
1553 #define MCF_GPIO_SETUA_SETUA0          (0x01)
1554 #define MCF_GPIO_SETUA_SETUA1          (0x02)
1555 #define MCF_GPIO_SETUA_SETUA2          (0x04)
1556 #define MCF_GPIO_SETUA_SETUA3          (0x08)
1557 #define MCF_GPIO_SETUA_SETUA4          (0x10)
1558 #define MCF_GPIO_SETUA_SETUA5          (0x20)
1559 #define MCF_GPIO_SETUA_SETUA6          (0x40)
1560 #define MCF_GPIO_SETUA_SETUA7          (0x80)
1561 
1562 /* Bit definitions and macros for MCF_GPIO_SETUB */
1563 #define MCF_GPIO_SETUB_SETUB0          (0x01)
1564 #define MCF_GPIO_SETUB_SETUB1          (0x02)
1565 #define MCF_GPIO_SETUB_SETUB2          (0x04)
1566 #define MCF_GPIO_SETUB_SETUB3          (0x08)
1567 #define MCF_GPIO_SETUB_SETUB4          (0x10)
1568 #define MCF_GPIO_SETUB_SETUB5          (0x20)
1569 #define MCF_GPIO_SETUB_SETUB6          (0x40)
1570 #define MCF_GPIO_SETUB_SETUB7          (0x80)
1571 
1572 /* Bit definitions and macros for MCF_GPIO_SETUC */
1573 #define MCF_GPIO_SETUC_SETUC0          (0x01)
1574 #define MCF_GPIO_SETUC_SETUC1          (0x02)
1575 #define MCF_GPIO_SETUC_SETUC2          (0x04)
1576 #define MCF_GPIO_SETUC_SETUC3          (0x08)
1577 #define MCF_GPIO_SETUC_SETUC4          (0x10)
1578 #define MCF_GPIO_SETUC_SETUC5          (0x20)
1579 #define MCF_GPIO_SETUC_SETUC6          (0x40)
1580 #define MCF_GPIO_SETUC_SETUC7          (0x80)
1581 
1582 /* Bit definitions and macros for MCF_GPIO_SETDD */
1583 #define MCF_GPIO_SETDD_SETDD0          (0x01)
1584 #define MCF_GPIO_SETDD_SETDD1          (0x02)
1585 #define MCF_GPIO_SETDD_SETDD2          (0x04)
1586 #define MCF_GPIO_SETDD_SETDD3          (0x08)
1587 #define MCF_GPIO_SETDD_SETDD4          (0x10)
1588 #define MCF_GPIO_SETDD_SETDD5          (0x20)
1589 #define MCF_GPIO_SETDD_SETDD6          (0x40)
1590 #define MCF_GPIO_SETDD_SETDD7          (0x80)
1591 
1592 /* Bit definitions and macros for MCF_GPIO_SETLD */
1593 #define MCF_GPIO_SETLD_SETLD0          (0x01)
1594 #define MCF_GPIO_SETLD_SETLD1          (0x02)
1595 #define MCF_GPIO_SETLD_SETLD2          (0x04)
1596 #define MCF_GPIO_SETLD_SETLD3          (0x08)
1597 #define MCF_GPIO_SETLD_SETLD4          (0x10)
1598 #define MCF_GPIO_SETLD_SETLD5          (0x20)
1599 #define MCF_GPIO_SETLD_SETLD6          (0x40)
1600 #define MCF_GPIO_SETLD_SETLD7          (0x80)
1601 
1602 /* Bit definitions and macros for MCF_GPIO_SETGP */
1603 #define MCF_GPIO_SETGP_SETGP0          (0x01)
1604 #define MCF_GPIO_SETGP_SETGP1          (0x02)
1605 #define MCF_GPIO_SETGP_SETGP2          (0x04)
1606 #define MCF_GPIO_SETGP_SETGP3          (0x08)
1607 #define MCF_GPIO_SETGP_SETGP4          (0x10)
1608 #define MCF_GPIO_SETGP_SETGP5          (0x20)
1609 #define MCF_GPIO_SETGP_SETGP6          (0x40)
1610 #define MCF_GPIO_SETGP_SETGP7          (0x80)
1611 
1612 /* Bit definitions and macros for MCF_GPIO_CLRNQ */
1613 #define MCF_GPIO_CLRNQ_CLRNQ0          (0x01)
1614 #define MCF_GPIO_CLRNQ_CLRNQ1          (0x02)
1615 #define MCF_GPIO_CLRNQ_CLRNQ2          (0x04)
1616 #define MCF_GPIO_CLRNQ_CLRNQ3          (0x08)
1617 #define MCF_GPIO_CLRNQ_CLRNQ4          (0x10)
1618 #define MCF_GPIO_CLRNQ_CLRNQ5          (0x20)
1619 #define MCF_GPIO_CLRNQ_CLRNQ6          (0x40)
1620 #define MCF_GPIO_CLRNQ_CLRNQ7          (0x80)
1621 
1622 /* Bit definitions and macros for MCF_GPIO_CLRAN */
1623 #define MCF_GPIO_CLRAN_CLRAN0          (0x01)
1624 #define MCF_GPIO_CLRAN_CLRAN1          (0x02)
1625 #define MCF_GPIO_CLRAN_CLRAN2          (0x04)
1626 #define MCF_GPIO_CLRAN_CLRAN3          (0x08)
1627 #define MCF_GPIO_CLRAN_CLRAN4          (0x10)
1628 #define MCF_GPIO_CLRAN_CLRAN5          (0x20)
1629 #define MCF_GPIO_CLRAN_CLRAN6          (0x40)
1630 #define MCF_GPIO_CLRAN_CLRAN7          (0x80)
1631 
1632 /* Bit definitions and macros for MCF_GPIO_CLRAS */
1633 #define MCF_GPIO_CLRAS_CLRAS0          (0x01)
1634 #define MCF_GPIO_CLRAS_CLRAS1          (0x02)
1635 #define MCF_GPIO_CLRAS_CLRAS2          (0x04)
1636 #define MCF_GPIO_CLRAS_CLRAS3          (0x08)
1637 #define MCF_GPIO_CLRAS_CLRAS4          (0x10)
1638 #define MCF_GPIO_CLRAS_CLRAS5          (0x20)
1639 #define MCF_GPIO_CLRAS_CLRAS6          (0x40)
1640 #define MCF_GPIO_CLRAS_CLRAS7          (0x80)
1641 
1642 /* Bit definitions and macros for MCF_GPIO_CLRQS */
1643 #define MCF_GPIO_CLRQS_CLRQS0          (0x01)
1644 #define MCF_GPIO_CLRQS_CLRQS1          (0x02)
1645 #define MCF_GPIO_CLRQS_CLRQS2          (0x04)
1646 #define MCF_GPIO_CLRQS_CLRQS3          (0x08)
1647 #define MCF_GPIO_CLRQS_CLRQS4          (0x10)
1648 #define MCF_GPIO_CLRQS_CLRQS5          (0x20)
1649 #define MCF_GPIO_CLRQS_CLRQS6          (0x40)
1650 #define MCF_GPIO_CLRQS_CLRQS7          (0x80)
1651 
1652 /* Bit definitions and macros for MCF_GPIO_CLRTA */
1653 #define MCF_GPIO_CLRTA_CLRTA0          (0x01)
1654 #define MCF_GPIO_CLRTA_CLRTA1          (0x02)
1655 #define MCF_GPIO_CLRTA_CLRTA2          (0x04)
1656 #define MCF_GPIO_CLRTA_CLRTA3          (0x08)
1657 #define MCF_GPIO_CLRTA_CLRTA4          (0x10)
1658 #define MCF_GPIO_CLRTA_CLRTA5          (0x20)
1659 #define MCF_GPIO_CLRTA_CLRTA6          (0x40)
1660 #define MCF_GPIO_CLRTA_CLRTA7          (0x80)
1661 
1662 /* Bit definitions and macros for MCF_GPIO_CLRTC */
1663 #define MCF_GPIO_CLRTC_CLRTC0          (0x01)
1664 #define MCF_GPIO_CLRTC_CLRTC1          (0x02)
1665 #define MCF_GPIO_CLRTC_CLRTC2          (0x04)
1666 #define MCF_GPIO_CLRTC_CLRTC3          (0x08)
1667 #define MCF_GPIO_CLRTC_CLRTC4          (0x10)
1668 #define MCF_GPIO_CLRTC_CLRTC5          (0x20)
1669 #define MCF_GPIO_CLRTC_CLRTC6          (0x40)
1670 #define MCF_GPIO_CLRTC_CLRTC7          (0x80)
1671 
1672 /* Bit definitions and macros for MCF_GPIO_CLRTD */
1673 #define MCF_GPIO_CLRTD_CLRTD0          (0x01)
1674 #define MCF_GPIO_CLRTD_CLRTD1          (0x02)
1675 #define MCF_GPIO_CLRTD_CLRTD2          (0x04)
1676 #define MCF_GPIO_CLRTD_CLRTD3          (0x08)
1677 #define MCF_GPIO_CLRTD_CLRTD4          (0x10)
1678 #define MCF_GPIO_CLRTD_CLRTD5          (0x20)
1679 #define MCF_GPIO_CLRTD_CLRTD6          (0x40)
1680 #define MCF_GPIO_CLRTD_CLRTD7          (0x80)
1681 
1682 /* Bit definitions and macros for MCF_GPIO_CLRUA */
1683 #define MCF_GPIO_CLRUA_CLRUA0          (0x01)
1684 #define MCF_GPIO_CLRUA_CLRUA1          (0x02)
1685 #define MCF_GPIO_CLRUA_CLRUA2          (0x04)
1686 #define MCF_GPIO_CLRUA_CLRUA3          (0x08)
1687 #define MCF_GPIO_CLRUA_CLRUA4          (0x10)
1688 #define MCF_GPIO_CLRUA_CLRUA5          (0x20)
1689 #define MCF_GPIO_CLRUA_CLRUA6          (0x40)
1690 #define MCF_GPIO_CLRUA_CLRUA7          (0x80)
1691 
1692 /* Bit definitions and macros for MCF_GPIO_CLRUB */
1693 #define MCF_GPIO_CLRUB_CLRUB0          (0x01)
1694 #define MCF_GPIO_CLRUB_CLRUB1          (0x02)
1695 #define MCF_GPIO_CLRUB_CLRUB2          (0x04)
1696 #define MCF_GPIO_CLRUB_CLRUB3          (0x08)
1697 #define MCF_GPIO_CLRUB_CLRUB4          (0x10)
1698 #define MCF_GPIO_CLRUB_CLRUB5          (0x20)
1699 #define MCF_GPIO_CLRUB_CLRUB6          (0x40)
1700 #define MCF_GPIO_CLRUB_CLRUB7          (0x80)
1701 
1702 /* Bit definitions and macros for MCF_GPIO_CLRUC */
1703 #define MCF_GPIO_CLRUC_CLRUC0          (0x01)
1704 #define MCF_GPIO_CLRUC_CLRUC1          (0x02)
1705 #define MCF_GPIO_CLRUC_CLRUC2          (0x04)
1706 #define MCF_GPIO_CLRUC_CLRUC3          (0x08)
1707 #define MCF_GPIO_CLRUC_CLRUC4          (0x10)
1708 #define MCF_GPIO_CLRUC_CLRUC5          (0x20)
1709 #define MCF_GPIO_CLRUC_CLRUC6          (0x40)
1710 #define MCF_GPIO_CLRUC_CLRUC7          (0x80)
1711 
1712 /* Bit definitions and macros for MCF_GPIO_CLRDD */
1713 #define MCF_GPIO_CLRDD_CLRDD0          (0x01)
1714 #define MCF_GPIO_CLRDD_CLRDD1          (0x02)
1715 #define MCF_GPIO_CLRDD_CLRDD2          (0x04)
1716 #define MCF_GPIO_CLRDD_CLRDD3          (0x08)
1717 #define MCF_GPIO_CLRDD_CLRDD4          (0x10)
1718 #define MCF_GPIO_CLRDD_CLRDD5          (0x20)
1719 #define MCF_GPIO_CLRDD_CLRDD6          (0x40)
1720 #define MCF_GPIO_CLRDD_CLRDD7          (0x80)
1721 
1722 /* Bit definitions and macros for MCF_GPIO_CLRLD */
1723 #define MCF_GPIO_CLRLD_CLRLD0          (0x01)
1724 #define MCF_GPIO_CLRLD_CLRLD1          (0x02)
1725 #define MCF_GPIO_CLRLD_CLRLD2          (0x04)
1726 #define MCF_GPIO_CLRLD_CLRLD3          (0x08)
1727 #define MCF_GPIO_CLRLD_CLRLD4          (0x10)
1728 #define MCF_GPIO_CLRLD_CLRLD5          (0x20)
1729 #define MCF_GPIO_CLRLD_CLRLD6          (0x40)
1730 #define MCF_GPIO_CLRLD_CLRLD7          (0x80)
1731 
1732 /* Bit definitions and macros for MCF_GPIO_CLRGP */
1733 #define MCF_GPIO_CLRGP_CLRGP0          (0x01)
1734 #define MCF_GPIO_CLRGP_CLRGP1          (0x02)
1735 #define MCF_GPIO_CLRGP_CLRGP2          (0x04)
1736 #define MCF_GPIO_CLRGP_CLRGP3          (0x08)
1737 #define MCF_GPIO_CLRGP_CLRGP4          (0x10)
1738 #define MCF_GPIO_CLRGP_CLRGP5          (0x20)
1739 #define MCF_GPIO_CLRGP_CLRGP6          (0x40)
1740 #define MCF_GPIO_CLRGP_CLRGP7          (0x80)
1741 
1742 /* Bit definitions and macros for MCF_GPIO_PNQPAR */
1743 #define MCF_GPIO_PNQPAR_PNQPAR1(x)     (((x)&0x0003)<<2)
1744 #define MCF_GPIO_PNQPAR_PNQPAR2(x)     (((x)&0x0003)<<4)
1745 #define MCF_GPIO_PNQPAR_PNQPAR3(x)     (((x)&0x0003)<<6)
1746 #define MCF_GPIO_PNQPAR_PNQPAR4(x)     (((x)&0x0003)<<8)
1747 #define MCF_GPIO_PNQPAR_PNQPAR5(x)     (((x)&0x0003)<<10)
1748 #define MCF_GPIO_PNQPAR_PNQPAR6(x)     (((x)&0x0003)<<12)
1749 #define MCF_GPIO_PNQPAR_PNQPAR7(x)     (((x)&0x0003)<<14)
1750 #define MCF_GPIO_PNQPAR_IRQ1_GPIO      (0x0000)
1751 #define MCF_GPIO_PNQPAR_IRQ2_GPIO      (0x0000)
1752 #define MCF_GPIO_PNQPAR_IRQ3_GPIO      (0x0000)
1753 #define MCF_GPIO_PNQPAR_IRQ4_GPIO      (0x0000)
1754 #define MCF_GPIO_PNQPAR_IRQ5_GPIO      (0x0000)
1755 #define MCF_GPIO_PNQPAR_IRQ6_GPIO      (0x0000)
1756 #define MCF_GPIO_PNQPAR_IRQ7_GPIO      (0x0000)
1757 #define MCF_GPIO_PNQPAR_IRQ1_IRQ1      (0x0004)
1758 #define MCF_GPIO_PNQPAR_IRQ2_IRQ2      (0x0010)
1759 #define MCF_GPIO_PNQPAR_IRQ3_IRQ3      (0x0040)
1760 #define MCF_GPIO_PNQPAR_IRQ4_IRQ4      (0x0100)
1761 #define MCF_GPIO_PNQPAR_IRQ5_IRQ5      (0x0400)
1762 #define MCF_GPIO_PNQPAR_IRQ6_IRQ6      (0x1000)
1763 #define MCF_GPIO_PNQPAR_IRQ7_IRQ7      (0x4000)
1764 #define MCF_GPIO_PNQPAR_IRQ1_SYNCA     (0x0008)
1765 #define MCF_GPIO_PNQPAR_IRQ1_PWM1      (0x000C)
1766 
1767 /* Bit definitions and macros for MCF_GPIO_PANPAR */
1768 #define MCF_GPIO_PANPAR_PANPAR0        (0x01)
1769 #define MCF_GPIO_PANPAR_PANPAR1        (0x02)
1770 #define MCF_GPIO_PANPAR_PANPAR2        (0x04)
1771 #define MCF_GPIO_PANPAR_PANPAR3        (0x08)
1772 #define MCF_GPIO_PANPAR_PANPAR4        (0x10)
1773 #define MCF_GPIO_PANPAR_PANPAR5        (0x20)
1774 #define MCF_GPIO_PANPAR_PANPAR6        (0x40)
1775 #define MCF_GPIO_PANPAR_PANPAR7        (0x80)
1776 #define MCF_GPIO_PANPAR_AN0_GPIO       (0x00)
1777 #define MCF_GPIO_PANPAR_AN1_GPIO       (0x00)
1778 #define MCF_GPIO_PANPAR_AN2_GPIO       (0x00)
1779 #define MCF_GPIO_PANPAR_AN3_GPIO       (0x00)
1780 #define MCF_GPIO_PANPAR_AN4_GPIO       (0x00)
1781 #define MCF_GPIO_PANPAR_AN5_GPIO       (0x00)
1782 #define MCF_GPIO_PANPAR_AN6_GPIO       (0x00)
1783 #define MCF_GPIO_PANPAR_AN7_GPIO       (0x00)
1784 #define MCF_GPIO_PANPAR_AN0_AN0        (0x01)
1785 #define MCF_GPIO_PANPAR_AN1_AN1        (0x02)
1786 #define MCF_GPIO_PANPAR_AN2_AN2        (0x04)
1787 #define MCF_GPIO_PANPAR_AN3_AN3        (0x08)
1788 #define MCF_GPIO_PANPAR_AN4_AN4        (0x10)
1789 #define MCF_GPIO_PANPAR_AN5_AN5        (0x20)
1790 #define MCF_GPIO_PANPAR_AN6_AN6        (0x40)
1791 #define MCF_GPIO_PANPAR_AN7_AN7        (0x80)
1792 
1793 /* Bit definitions and macros for MCF_GPIO_PASPAR */
1794 #define MCF_GPIO_PASPAR_PASPAR0(x)     (((x)&0x03)<<0)
1795 #define MCF_GPIO_PASPAR_PASPAR1(x)     (((x)&0x03)<<2)
1796 #define MCF_GPIO_PASPAR_PASPAR2(x)     (((x)&0x03)<<4)
1797 #define MCF_GPIO_PASPAR_PASPAR3(x)     (((x)&0x03)<<6)
1798 #define MCF_GPIO_PASPAR_SCL_GPIO       (0x00)
1799 #define MCF_GPIO_PASPAR_SDA_GPIO       (0x00)
1800 #define MCF_GPIO_PASPAR_SYNCA_GPIO     (0x00)
1801 #define MCF_GPIO_PASPAR_SYNCB_GPIO     (0x00)
1802 #define MCF_GPIO_PASPAR_SCL_SCL        (0x01)
1803 #define MCF_GPIO_PASPAR_SDA_SDA        (0x04)
1804 #define MCF_GPIO_PASPAR_SYNCA_SYNCA    (0x10)
1805 #define MCF_GPIO_PASPAR_SYNCB_SYNCB    (0x40)
1806 #define MCF_GPIO_PASPAR_SCL_CANTX      (0x02)
1807 #define MCF_GPIO_PASPAR_SDA_CANRX      (0x08)
1808 #define MCF_GPIO_PASPAR_SYNCA_CANRX    (0x20)
1809 #define MCF_GPIO_PASPAR_SYNCB_CANTX    (0x80)
1810 #define MCF_GPIO_PASPAR_SCL_TXD2       (0x30)
1811 #define MCF_GPIO_PASPAR_SDA_RXD2       (0xC0)
1812 
1813 /* Bit definitions and macros for MCF_GPIO_PQSPAR */
1814 #define MCF_GPIO_PQSPAR_PQSPAR0(x)     (((x)&0x0003)<<0)
1815 #define MCF_GPIO_PQSPAR_PQSPAR1(x)     (((x)&0x0003)<<2)
1816 #define MCF_GPIO_PQSPAR_PQSPAR2(x)     (((x)&0x0003)<<4)
1817 #define MCF_GPIO_PQSPAR_PQSPAR3(x)     (((x)&0x0003)<<6)
1818 #define MCF_GPIO_PQSPAR_PQSPAR4(x)     (((x)&0x0003)<<8)
1819 #define MCF_GPIO_PQSPAR_PQSPAR5(x)     (((x)&0x0003)<<10)
1820 #define MCF_GPIO_PQSPAR_PQSPAR6(x)     (((x)&0x0003)<<12)
1821 #define MCF_GPIO_PQSPAR_DOUT_GPIO      (0x0000)
1822 #define MCF_GPIO_PQSPAR_DIN_GPIO       (0x0000)
1823 #define MCF_GPIO_PQSPAR_SCK_GPIO       (0x0000)
1824 #define MCF_GPIO_PQSPAR_CS0_GPIO       (0x0000)
1825 #define MCF_GPIO_PQSPAR_CS1_GPIO       (0x0000)
1826 #define MCF_GPIO_PQSPAR_CS2_GPIO       (0x0000)
1827 #define MCF_GPIO_PQSPAR_CS3_GPIO       (0x0000)
1828 #define MCF_GPIO_PQSPAR_DOUT_DOUT      (0x0001)
1829 #define MCF_GPIO_PQSPAR_DIN_DIN        (0x0004)
1830 #define MCF_GPIO_PQSPAR_SCK_SCK        (0x0010)
1831 #define MCF_GPIO_PQSPAR_CS0_CS0        (0x0040)
1832 #define MCF_GPIO_PQSPAR_CS1_CS1        (0x0100)
1833 #define MCF_GPIO_PQSPAR_CS2_CS2        (0x0400)
1834 #define MCF_GPIO_PQSPAR_CS3_CS3        (0x1000)
1835 #define MCF_GPIO_PQSPAR_DOUT_CANTX     (0x0002)
1836 #define MCF_GPIO_PQSPAR_DIN_CANRX      (0x0008)
1837 #define MCF_GPIO_PQSPAR_SCK_SCL        (0x0020)
1838 #define MCF_GPIO_PQSPAR_CS0_SDA        (0x0080)
1839 #define MCF_GPIO_PQSPAR_CS3_SYNCA      (0x2000)
1840 #define MCF_GPIO_PQSPAR_DOUT_TXD1      (0x0003)
1841 #define MCF_GPIO_PQSPAR_DIN_RXD1       (0x000C)
1842 #define MCF_GPIO_PQSPAR_SCK_RTS1       (0x0030)
1843 #define MCF_GPIO_PQSPAR_CS0_CTS1       (0x00C0)
1844 #define MCF_GPIO_PQSPAR_CS3_SYNCB      (0x3000)
1845 
1846 /* Bit definitions and macros for MCF_GPIO_PTAPAR */
1847 #define MCF_GPIO_PTAPAR_PTAPAR0(x)     (((x)&0x03)<<0)
1848 #define MCF_GPIO_PTAPAR_PTAPAR1(x)     (((x)&0x03)<<2)
1849 #define MCF_GPIO_PTAPAR_PTAPAR2(x)     (((x)&0x03)<<4)
1850 #define MCF_GPIO_PTAPAR_PTAPAR3(x)     (((x)&0x03)<<6)
1851 #define MCF_GPIO_PTAPAR_ICOC0_GPIO     (0x00)
1852 #define MCF_GPIO_PTAPAR_ICOC1_GPIO     (0x00)
1853 #define MCF_GPIO_PTAPAR_ICOC2_GPIO     (0x00)
1854 #define MCF_GPIO_PTAPAR_ICOC3_GPIO     (0x00)
1855 #define MCF_GPIO_PTAPAR_ICOC0_ICOC0    (0x01)
1856 #define MCF_GPIO_PTAPAR_ICOC1_ICOC1    (0x04)
1857 #define MCF_GPIO_PTAPAR_ICOC2_ICOC2    (0x10)
1858 #define MCF_GPIO_PTAPAR_ICOC3_ICOC3    (0x40)
1859 #define MCF_GPIO_PTAPAR_ICOC0_PWM1     (0x02)
1860 #define MCF_GPIO_PTAPAR_ICOC1_PWM3     (0x08)
1861 #define MCF_GPIO_PTAPAR_ICOC2_PWM5     (0x20)
1862 #define MCF_GPIO_PTAPAR_ICOC3_PWM7     (0x80)
1863 
1864 /* Bit definitions and macros for MCF_GPIO_PTCPAR */
1865 #define MCF_GPIO_PTCPAR_PTCPAR0(x)     (((x)&0x03)<<0)
1866 #define MCF_GPIO_PTCPAR_PTCPAR1(x)     (((x)&0x03)<<2)
1867 #define MCF_GPIO_PTCPAR_PTCPAR2(x)     (((x)&0x03)<<4)
1868 #define MCF_GPIO_PTCPAR_PTCPAR3(x)     (((x)&0x03)<<6)
1869 #define MCF_GPIO_PTCPAR_TIN0_GPIO      (0x00)
1870 #define MCF_GPIO_PTCPAR_TIN1_GPIO      (0x00)
1871 #define MCF_GPIO_PTCPAR_TIN2_GPIO      (0x00)
1872 #define MCF_GPIO_PTCPAR_TIN3_GPIO      (0x00)
1873 #define MCF_GPIO_PTCPAR_TIN0_TIN0      (0x01)
1874 #define MCF_GPIO_PTCPAR_TIN1_TIN1      (0x04)
1875 #define MCF_GPIO_PTCPAR_TIN2_TIN2      (0x10)
1876 #define MCF_GPIO_PTCPAR_TIN3_TIN3      (0x40)
1877 #define MCF_GPIO_PTCPAR_TIN0_TOUT0     (0x02)
1878 #define MCF_GPIO_PTCPAR_TIN1_TOUT1     (0x08)
1879 #define MCF_GPIO_PTCPAR_TIN2_TOUT2     (0x20)
1880 #define MCF_GPIO_PTCPAR_TIN3_TOUT3     (0x80)
1881 #define MCF_GPIO_PTCPAR_TIN0_PWM0      (0x03)
1882 #define MCF_GPIO_PTCPAR_TIN1_PWM2      (0x0C)
1883 #define MCF_GPIO_PTCPAR_TIN2_PWM4      (0x30)
1884 #define MCF_GPIO_PTCPAR_TIN3_PWM6      (0xC0)
1885 
1886 /* Bit definitions and macros for MCF_GPIO_PTDPAR */
1887 #define MCF_GPIO_PTDPAR_PTDPAR0        (0x01)
1888 #define MCF_GPIO_PTDPAR_PTDPAR1        (0x02)
1889 #define MCF_GPIO_PTDPAR_PTDPAR2        (0x04)
1890 #define MCF_GPIO_PTDPAR_PTDPAR3        (0x08)
1891 #define MCF_GPIO_PTDPAR_PWM1_GPIO      (0x00)
1892 #define MCF_GPIO_PTDPAR_PWM3_GPIO      (0x00)
1893 #define MCF_GPIO_PTDPAR_PWM5_GPIO      (0x00)
1894 #define MCF_GPIO_PTDPAR_PWM7_GPIO      (0x00)
1895 #define MCF_GPIO_PTDPAR_PWM1_PWM1      (0x01)
1896 #define MCF_GPIO_PTDPAR_PWM3_PWM3      (0x02)
1897 #define MCF_GPIO_PTDPAR_PWM5_PWM5      (0x04)
1898 #define MCF_GPIO_PTDPAR_PWM7_PWM7      (0x08)
1899 
1900 /* Bit definitions and macros for MCF_GPIO_PUAPAR */
1901 #define MCF_GPIO_PUAPAR_PUAPAR0(x)     (((x)&0x03)<<0)
1902 #define MCF_GPIO_PUAPAR_PUAPAR1(x)     (((x)&0x03)<<2)
1903 #define MCF_GPIO_PUAPAR_PUAPAR2(x)     (((x)&0x03)<<4)
1904 #define MCF_GPIO_PUAPAR_PUAPAR3(x)     (((x)&0x03)<<6)
1905 #define MCF_GPIO_PUAPAR_TXD0_GPIO      (0x00)
1906 #define MCF_GPIO_PUAPAR_RXD0_GPIO      (0x00)
1907 #define MCF_GPIO_PUAPAR_RTS0_GPIO      (0x00)
1908 #define MCF_GPIO_PUAPAR_CTS0_GPIO      (0x00)
1909 #define MCF_GPIO_PUAPAR_TXD0_TXD0      (0x01)
1910 #define MCF_GPIO_PUAPAR_RXD0_RXD0      (0x04)
1911 #define MCF_GPIO_PUAPAR_RTS0_RTS0      (0x10)
1912 #define MCF_GPIO_PUAPAR_CTS0_CTS0      (0x40)
1913 #define MCF_GPIO_PUAPAR_RTS0_CANTX     (0x20)
1914 #define MCF_GPIO_PUAPAR_CTS0_CANRX     (0x80)
1915 
1916 /* Bit definitions and macros for MCF_GPIO_PUBPAR */
1917 #define MCF_GPIO_PUBPAR_PUBPAR0(x)     (((x)&0x03)<<0)
1918 #define MCF_GPIO_PUBPAR_PUBPAR1(x)     (((x)&0x03)<<2)
1919 #define MCF_GPIO_PUBPAR_PUBPAR2(x)     (((x)&0x03)<<4)
1920 #define MCF_GPIO_PUBPAR_PUBPAR3(x)     (((x)&0x03)<<6)
1921 #define MCF_GPIO_PUBPAR_TXD1_GPIO      (0x00)
1922 #define MCF_GPIO_PUBPAR_RXD1_GPIO      (0x00)
1923 #define MCF_GPIO_PUBPAR_RTS1_GPIO      (0x00)
1924 #define MCF_GPIO_PUBPAR_CTS1_GPIO      (0x00)
1925 #define MCF_GPIO_PUBPAR_TXD1_TXD1      (0x01)
1926 #define MCF_GPIO_PUBPAR_RXD1_RXD1      (0x04)
1927 #define MCF_GPIO_PUBPAR_RTS1_RTS1      (0x10)
1928 #define MCF_GPIO_PUBPAR_CTS1_CTS1      (0x40)
1929 #define MCF_GPIO_PUBPAR_RTS1_SYNCB     (0x20)
1930 #define MCF_GPIO_PUBPAR_CTS1_SYNCA     (0x80)
1931 #define MCF_GPIO_PUBPAR_RTS1_TXD2      (0x30)
1932 #define MCF_GPIO_PUBPAR_CTS1_RXD2      (0xC0)
1933 
1934 /* Bit definitions and macros for MCF_GPIO_PUCPAR */
1935 #define MCF_GPIO_PUCPAR_PUCPAR0        (0x01)
1936 #define MCF_GPIO_PUCPAR_PUCPAR1        (0x02)
1937 #define MCF_GPIO_PUCPAR_PUCPAR2        (0x04)
1938 #define MCF_GPIO_PUCPAR_PUCPAR3        (0x08)
1939 #define MCF_GPIO_PUCPAR_TXD2_GPIO      (0x00)
1940 #define MCF_GPIO_PUCPAR_RXD2_GPIO      (0x00)
1941 #define MCF_GPIO_PUCPAR_RTS2_GPIO      (0x00)
1942 #define MCF_GPIO_PUCPAR_CTS2_GPIO      (0x00)
1943 #define MCF_GPIO_PUCPAR_TXD2_TXD2      (0x01)
1944 #define MCF_GPIO_PUCPAR_RXD2_RXD2      (0x02)
1945 #define MCF_GPIO_PUCPAR_RTS2_RTS2      (0x04)
1946 #define MCF_GPIO_PUCPAR_CTS2_CTS2      (0x08)
1947 
1948 /* Bit definitions and macros for MCF_GPIO_PDDPAR */
1949 #define MCF_GPIO_PDDPAR_PDDPAR0        (0x01)
1950 #define MCF_GPIO_PDDPAR_PDDPAR1        (0x02)
1951 #define MCF_GPIO_PDDPAR_PDDPAR2        (0x04)
1952 #define MCF_GPIO_PDDPAR_PDDPAR3        (0x08)
1953 #define MCF_GPIO_PDDPAR_PDDPAR4        (0x10)
1954 #define MCF_GPIO_PDDPAR_PDDPAR5        (0x20)
1955 #define MCF_GPIO_PDDPAR_PDDPAR6        (0x40)
1956 #define MCF_GPIO_PDDPAR_PDDPAR7        (0x80)
1957 #define MCF_GPIO_PDDPAR_PDD0_GPIO      (0x00)
1958 #define MCF_GPIO_PDDPAR_PDD1_GPIO      (0x00)
1959 #define MCF_GPIO_PDDPAR_PDD2_GPIO      (0x00)
1960 #define MCF_GPIO_PDDPAR_PDD3_GPIO      (0x00)
1961 #define MCF_GPIO_PDDPAR_PDD4_GPIO      (0x00)
1962 #define MCF_GPIO_PDDPAR_PDD5_GPIO      (0x00)
1963 #define MCF_GPIO_PDDPAR_PDD6_GPIO      (0x00)
1964 #define MCF_GPIO_PDDPAR_PDD7_GPIO      (0x00)
1965 #define MCF_GPIO_PDDPAR_PDD0_PST0      (0x01)
1966 #define MCF_GPIO_PDDPAR_PDD1_PST1      (0x02)
1967 #define MCF_GPIO_PDDPAR_PDD2_PST2      (0x04)
1968 #define MCF_GPIO_PDDPAR_PDD3_PST3      (0x08)
1969 #define MCF_GPIO_PDDPAR_PDD4_DDATA0    (0x10)
1970 #define MCF_GPIO_PDDPAR_PDD5_DDATA1    (0x20)
1971 #define MCF_GPIO_PDDPAR_PDD6_DDATA2    (0x40)
1972 #define MCF_GPIO_PDDPAR_PDD7_DDATA3    (0x80)
1973 
1974 /* Bit definitions and macros for MCF_GPIO_PLDPAR */
1975 #define MCF_GPIO_PLDPAR_PLDPAR0        (0x01)
1976 #define MCF_GPIO_PLDPAR_PLDPAR1        (0x02)
1977 #define MCF_GPIO_PLDPAR_PLDPAR2        (0x04)
1978 #define MCF_GPIO_PLDPAR_PLDPAR3        (0x08)
1979 #define MCF_GPIO_PLDPAR_PLDPAR4        (0x10)
1980 #define MCF_GPIO_PLDPAR_PLDPAR5        (0x20)
1981 #define MCF_GPIO_PLDPAR_PLDPAR6        (0x40)
1982 #define MCF_GPIO_PLDPAR_ACTLED_GPIO    (0x00)
1983 #define MCF_GPIO_PLDPAR_LNKLED_GPIO    (0x00)
1984 #define MCF_GPIO_PLDPAR_SPDLED_GPIO    (0x00)
1985 #define MCF_GPIO_PLDPAR_DUPLED_GPIO    (0x00)
1986 #define MCF_GPIO_PLDPAR_COLLED_GPIO    (0x00)
1987 #define MCF_GPIO_PLDPAR_RXLED_GPIO     (0x00)
1988 #define MCF_GPIO_PLDPAR_TXLED_GPIO     (0x00)
1989 #define MCF_GPIO_PLDPAR_ACTLED_ACTLED  (0x01)
1990 #define MCF_GPIO_PLDPAR_LNKLED_LNKLED  (0x02)
1991 #define MCF_GPIO_PLDPAR_SPDLED_SPDLED  (0x04)
1992 #define MCF_GPIO_PLDPAR_DUPLED_DUPLED  (0x08)
1993 #define MCF_GPIO_PLDPAR_COLLED_COLLED  (0x10)
1994 #define MCF_GPIO_PLDPAR_RXLED_RXLED    (0x20)
1995 #define MCF_GPIO_PLDPAR_TXLED_TXLED    (0x40)
1996 
1997 /* Bit definitions and macros for MCF_GPIO_PGPPAR */
1998 #define MCF_GPIO_PGPPAR_PGPPAR0        (0x01)
1999 #define MCF_GPIO_PGPPAR_PGPPAR1        (0x02)
2000 #define MCF_GPIO_PGPPAR_PGPPAR2        (0x04)
2001 #define MCF_GPIO_PGPPAR_PGPPAR3        (0x08)
2002 #define MCF_GPIO_PGPPAR_PGPPAR4        (0x10)
2003 #define MCF_GPIO_PGPPAR_PGPPAR5        (0x20)
2004 #define MCF_GPIO_PGPPAR_PGPPAR6        (0x40)
2005 #define MCF_GPIO_PGPPAR_PGPPAR7        (0x80)
2006 #define MCF_GPIO_PGPPAR_IRQ8_GPIO      (0x00)
2007 #define MCF_GPIO_PGPPAR_IRQ9_GPIO      (0x00)
2008 #define MCF_GPIO_PGPPAR_IRQ10_GPIO     (0x00)
2009 #define MCF_GPIO_PGPPAR_IRQ11_GPIO     (0x00)
2010 #define MCF_GPIO_PGPPAR_IRQ12_GPIO     (0x00)
2011 #define MCF_GPIO_PGPPAR_IRQ13_GPIO     (0x00)
2012 #define MCF_GPIO_PGPPAR_IRQ14_GPIO     (0x00)
2013 #define MCF_GPIO_PGPPAR_IRQ15_GPIO     (0x00)
2014 #define MCF_GPIO_PGPPAR_IRQ8_IRQ8      (0x01)
2015 #define MCF_GPIO_PGPPAR_IRQ9_IRQ9      (0x02)
2016 #define MCF_GPIO_PGPPAR_IRQ10_IRQ10    (0x04)
2017 #define MCF_GPIO_PGPPAR_IRQ11_IRQ11    (0x08)
2018 #define MCF_GPIO_PGPPAR_IRQ12_IRQ12    (0x10)
2019 #define MCF_GPIO_PGPPAR_IRQ13_IRQ13    (0x30)
2020 #define MCF_GPIO_PGPPAR_IRQ14_IRQ14    (0x40)
2021 #define MCF_GPIO_PGPPAR_IRQ15_IRQ15    (0x80)
2022 
2023 /* Bit definitions and macros for MCF_GPIO_PWOR */
2024 #define MCF_GPIO_PWOR_PWOR0            (0x0001)
2025 #define MCF_GPIO_PWOR_PWOR1            (0x0002)
2026 #define MCF_GPIO_PWOR_PWOR2            (0x0004)
2027 #define MCF_GPIO_PWOR_PWOR3            (0x0008)
2028 #define MCF_GPIO_PWOR_PWOR4            (0x0010)
2029 #define MCF_GPIO_PWOR_PWOR5            (0x0020)
2030 #define MCF_GPIO_PWOR_PWOR6            (0x0040)
2031 #define MCF_GPIO_PWOR_PWOR7            (0x0080)
2032 #define MCF_GPIO_PWOR_PWOR8            (0x0100)
2033 #define MCF_GPIO_PWOR_PWOR9            (0x0200)
2034 #define MCF_GPIO_PWOR_PWOR10           (0x0400)
2035 #define MCF_GPIO_PWOR_PWOR11           (0x0800)
2036 #define MCF_GPIO_PWOR_PWOR12           (0x1000)
2037 #define MCF_GPIO_PWOR_PWOR13           (0x2000)
2038 #define MCF_GPIO_PWOR_PWOR14           (0x4000)
2039 #define MCF_GPIO_PWOR_PWOR15           (0x8000)
2040 
2041 /* Bit definitions and macros for MCF_GPIO_PDSRH */
2042 #define MCF_GPIO_PDSRH_PDSR32          (0x0001)
2043 #define MCF_GPIO_PDSRH_PDSR33          (0x0002)
2044 #define MCF_GPIO_PDSRH_PDSR34          (0x0004)
2045 #define MCF_GPIO_PDSRH_PDSR35          (0x0008)
2046 #define MCF_GPIO_PDSRH_PDSR36          (0x0010)
2047 #define MCF_GPIO_PDSRH_PDSR37          (0x0020)
2048 #define MCF_GPIO_PDSRH_PDSR38          (0x0040)
2049 #define MCF_GPIO_PDSRH_PDSR39          (0x0080)
2050 #define MCF_GPIO_PDSRH_PDSR40          (0x0100)
2051 #define MCF_GPIO_PDSRH_PDSR41          (0x0200)
2052 #define MCF_GPIO_PDSRH_PDSR42          (0x0400)
2053 #define MCF_GPIO_PDSRH_PDSR43          (0x0800)
2054 #define MCF_GPIO_PDSRH_PDSR44          (0x1000)
2055 #define MCF_GPIO_PDSRH_PDSR45          (0x2000)
2056 #define MCF_GPIO_PDSRH_PDSR46          (0x4000)
2057 #define MCF_GPIO_PDSRH_PDSR47          (0x8000)
2058 
2059 /* Bit definitions and macros for MCF_GPIO_PDSRL */
2060 #define MCF_GPIO_PDSRL_PDSR0           (0x00000001)
2061 #define MCF_GPIO_PDSRL_PDSR1           (0x00000002)
2062 #define MCF_GPIO_PDSRL_PDSR2           (0x00000004)
2063 #define MCF_GPIO_PDSRL_PDSR3           (0x00000008)
2064 #define MCF_GPIO_PDSRL_PDSR4           (0x00000010)
2065 #define MCF_GPIO_PDSRL_PDSR5           (0x00000020)
2066 #define MCF_GPIO_PDSRL_PDSR6           (0x00000040)
2067 #define MCF_GPIO_PDSRL_PDSR7           (0x00000080)
2068 #define MCF_GPIO_PDSRL_PDSR8           (0x00000100)
2069 #define MCF_GPIO_PDSRL_PDSR9           (0x00000200)
2070 #define MCF_GPIO_PDSRL_PDSR10          (0x00000400)
2071 #define MCF_GPIO_PDSRL_PDSR11          (0x00000800)
2072 #define MCF_GPIO_PDSRL_PDSR12          (0x00001000)
2073 #define MCF_GPIO_PDSRL_PDSR13          (0x00002000)
2074 #define MCF_GPIO_PDSRL_PDSR14          (0x00004000)
2075 #define MCF_GPIO_PDSRL_PDSR15          (0x00008000)
2076 #define MCF_GPIO_PDSRL_PDSR16          (0x00010000)
2077 #define MCF_GPIO_PDSRL_PDSR17          (0x00020000)
2078 #define MCF_GPIO_PDSRL_PDSR18          (0x00040000)
2079 #define MCF_GPIO_PDSRL_PDSR19          (0x00080000)
2080 #define MCF_GPIO_PDSRL_PDSR20          (0x00100000)
2081 #define MCF_GPIO_PDSRL_PDSR21          (0x00200000)
2082 #define MCF_GPIO_PDSRL_PDSR22          (0x00400000)
2083 #define MCF_GPIO_PDSRL_PDSR23          (0x00800000)
2084 #define MCF_GPIO_PDSRL_PDSR24          (0x01000000)
2085 #define MCF_GPIO_PDSRL_PDSR25          (0x02000000)
2086 #define MCF_GPIO_PDSRL_PDSR26          (0x04000000)
2087 #define MCF_GPIO_PDSRL_PDSR27          (0x08000000)
2088 #define MCF_GPIO_PDSRL_PDSR28          (0x10000000)
2089 #define MCF_GPIO_PDSRL_PDSR29          (0x20000000)
2090 #define MCF_GPIO_PDSRL_PDSR30          (0x40000000)
2091 #define MCF_GPIO_PDSRL_PDSR31          (0x80000000)
2092 
2093 /*********************************************************************
2094 *
2095 * ColdFire Integration Module (CIM)
2096 *
2097 *********************************************************************/
2098 
2099 /* Register read/write macros */
2100 #define MCF_CIM_RCR             (*(vuint8 *)(&__IPSBAR[0x110000]))
2101 #define MCF_CIM_RSR             (*(vuint8 *)(&__IPSBAR[0x110001]))
2102 #define MCF_CIM_CCR             (*(vuint16*)(&__IPSBAR[0x110004]))
2103 #define MCF_CIM_LPCR            (*(vuint8 *)(&__IPSBAR[0x110007]))
2104 #define MCF_CIM_RCON            (*(vuint16*)(&__IPSBAR[0x110008]))
2105 #define MCF_CIM_CIR             (*(vuint16*)(&__IPSBAR[0x11000A]))
2106 
2107 /* Bit definitions and macros for MCF_CIM_RCR */
2108 #define MCF_CIM_RCR_LVDE        (0x01)
2109 #define MCF_CIM_RCR_LVDRE       (0x04)
2110 #define MCF_CIM_RCR_LVDIE       (0x08)
2111 #define MCF_CIM_RCR_LVDF        (0x10)
2112 #define MCF_CIM_RCR_FRCRSTOUT   (0x40)
2113 #define MCF_CIM_RCR_SOFTRST     (0x80)
2114 
2115 /* Bit definitions and macros for MCF_CIM_RSR */
2116 #define MCF_CIM_RSR_LOL         (0x01)
2117 #define MCF_CIM_RSR_LOC         (0x02)
2118 #define MCF_CIM_RSR_EXT         (0x04)
2119 #define MCF_CIM_RSR_POR         (0x08)
2120 #define MCF_CIM_RSR_WDR         (0x10)
2121 #define MCF_CIM_RSR_SOFT        (0x20)
2122 #define MCF_CIM_RSR_LVD         (0x40)
2123 
2124 /* Bit definitions and macros for MCF_CIM_CCR */
2125 #define MCF_CIM_CCR_LOAD        (0x8000)
2126 
2127 /* Bit definitions and macros for MCF_CIM_LPCR */
2128 #define MCF_CIM_LPCR_LVDSE      (0x02)
2129 #define MCF_CIM_LPCR_STPMD(x)   (((x)&0x03)<<3)
2130 #define MCF_CIM_LPCR_LPMD(x)    (((x)&0x03)<<6)
2131 #define MCF_CIM_LPCR_LPMD_STOP  (0xC0)
2132 #define MCF_CIM_LPCR_LPMD_WAIT  (0x80)
2133 #define MCF_CIM_LPCR_LPMD_DOZE  (0x40)
2134 #define MCF_CIM_LPCR_LPMD_RUN   (0x00)
2135 
2136 /* Bit definitions and macros for MCF_CIM_RCON */
2137 #define MCF_CIM_RCON_RLOAD      (0x0020)
2138 
2139 /*********************************************************************
2140 *
2141 * Clock Module (CLOCK)
2142 *
2143 *********************************************************************/
2144 
2145 /* Register read/write macros */
2146 #define MCF_CLOCK_SYNCR           (*(vuint16*)(&__IPSBAR[0x120000]))
2147 #define MCF_CLOCK_SYNSR           (*(vuint8 *)(&__IPSBAR[0x120002]))
2148 #define MCF_CLOCK_LPCR            (*(vuint8 *)(&__IPSBAR[0x120007]))
2149 #define MCF_CLOCK_CCHR            (*(vuint8 *)(&__IPSBAR[0x120008]))
2150 #define MCF_CLOCK_RTCDR           (*(vuint32*)(&__IPSBAR[0x12000C]))
2151 
2152 /* Bit definitions and macros for MCF_CLOCK_SYNCR */
2153 #define MCF_CLOCK_SYNCR_PLLEN     (0x0001)
2154 #define MCF_CLOCK_SYNCR_PLLMODE   (0x0002)
2155 #define MCF_CLOCK_SYNCR_CLKSRC    (0x0004)
2156 #define MCF_CLOCK_SYNCR_FWKUP     (0x0020)
2157 #define MCF_CLOCK_SYNCR_DISCLK    (0x0040)
2158 #define MCF_CLOCK_SYNCR_LOCEN     (0x0080)
2159 #define MCF_CLOCK_SYNCR_RFD(x)    (((x)&0x0007)<<8)
2160 #define MCF_CLOCK_SYNCR_LOCRE     (0x0800)
2161 #define MCF_CLOCK_SYNCR_MFD(x)    (((x)&0x0007)<<12)
2162 #define MCF_CLOCK_SYNCR_LOLRE     (0x8000)
2163 
2164 /* Bit definitions and macros for MCF_CLOCK_SYNSR */
2165 #define MCF_CLOCK_SYNSR_LOCS      (0x04)
2166 #define MCF_CLOCK_SYNSR_LOCK      (0x08)
2167 #define MCF_CLOCK_SYNSR_LOCKS     (0x10)
2168 #define MCF_CLOCK_SYNSR_CRYOSC    (0x20)
2169 #define MCF_CLOCK_SYNSR_OCOSC     (0x40)
2170 #define MCF_CLOCK_SYNSR_EXTOSC    (0x80)
2171 
2172 /* Bit definitions and macros for MCF_CLOCK_LPCR */
2173 #define MCF_CLOCK_LPCR_LPD(x)     (((x)&0x0F)<<0)
2174 
2175 /* Bit definitions and macros for MCF_CLOCK_CCHR */
2176 #define MCF_CLOCK_CCHR_PFD(x)     (((x)&0x07)<<0)
2177 
2178 /* Bit definitions and macros for MCF_CLOCK_RTCDR */
2179 #define MCF_CLOCK_RTCDR_RTCDF(x)  (((x)&0xFFFFFFFF)<<0)
2180 
2181 /*********************************************************************
2182 *
2183 * Edge Port Module (EPORT)
2184 *
2185 *********************************************************************/
2186 
2187 /* Register read/write macros */
2188 #define MCF_EPORT_EPPAR0                (*(vuint16*)(&__IPSBAR[0x130000]))
2189 #define MCF_EPORT_EPPAR1                (*(vuint16*)(&__IPSBAR[0x140000]))
2190 #define MCF_EPORT_EPDDR0                (*(vuint8 *)(&__IPSBAR[0x130002]))
2191 #define MCF_EPORT_EPDDR1                (*(vuint8 *)(&__IPSBAR[0x140002]))
2192 #define MCF_EPORT_EPIER0                (*(vuint8 *)(&__IPSBAR[0x130003]))
2193 #define MCF_EPORT_EPIER1                (*(vuint8 *)(&__IPSBAR[0x140003]))
2194 #define MCF_EPORT_EPDR0                 (*(vuint8 *)(&__IPSBAR[0x130004]))
2195 #define MCF_EPORT_EPDR1                 (*(vuint8 *)(&__IPSBAR[0x140004]))
2196 #define MCF_EPORT_EPPDR0                (*(vuint8 *)(&__IPSBAR[0x130005]))
2197 #define MCF_EPORT_EPPDR1                (*(vuint8 *)(&__IPSBAR[0x140005]))
2198 #define MCF_EPORT_EPFR0                 (*(vuint8 *)(&__IPSBAR[0x130006]))
2199 #define MCF_EPORT_EPFR1                 (*(vuint8 *)(&__IPSBAR[0x140006]))
2200 
2201 /* Bit definitions and macros for MCF_EPORT_EPPAR */
2202 #define MCF_EPORT_EPPAR_EPPA1(x)        (((x)&0x0003)<<2)
2203 #define MCF_EPORT_EPPAR_EPPA2(x)        (((x)&0x0003)<<4)
2204 #define MCF_EPORT_EPPAR_EPPA3(x)        (((x)&0x0003)<<6)
2205 #define MCF_EPORT_EPPAR_EPPA4(x)        (((x)&0x0003)<<8)
2206 #define MCF_EPORT_EPPAR_EPPA5(x)        (((x)&0x0003)<<10)
2207 #define MCF_EPORT_EPPAR_EPPA6(x)        (((x)&0x0003)<<12)
2208 #define MCF_EPORT_EPPAR_EPPA7(x)        (((x)&0x0003)<<14)
2209 #define MCF_EPORT_EPPAR_EPPA8(x)        (((x)&0x0003)<<0)
2210 #define MCF_EPORT_EPPAR_EPPA9(x)        (((x)&0x0003)<<2)
2211 #define MCF_EPORT_EPPAR_EPPA10(x)       (((x)&0x0003)<<4)
2212 #define MCF_EPORT_EPPAR_EPPA11(x)       (((x)&0x0003)<<6)
2213 #define MCF_EPORT_EPPAR_EPPA12(x)       (((x)&0x0003)<<8)
2214 #define MCF_EPORT_EPPAR_EPPA13(x)       (((x)&0x0003)<<10)
2215 #define MCF_EPORT_EPPAR_EPPA14(x)       (((x)&0x0003)<<12)
2216 #define MCF_EPORT_EPPAR_EPPA15(x)       (((x)&0x0003)<<14)
2217 #define MCF_EPORT_EPPAR_LEVEL           (0)
2218 #define MCF_EPORT_EPPAR_RISING          (1)
2219 #define MCF_EPORT_EPPAR_FALLING         (2)
2220 #define MCF_EPORT_EPPAR_BOTH            (3)
2221 #define MCF_EPORT_EPPAR_EPPA15_LEVEL    (0x0000)
2222 #define MCF_EPORT_EPPAR_EPPA15_RISING   (0x4000)
2223 #define MCF_EPORT_EPPAR_EPPA15_FALLING  (0x8000)
2224 #define MCF_EPORT_EPPAR_EPPA15_BOTH     (0xC000)
2225 #define MCF_EPORT_EPPAR_EPPA14_LEVEL    (0x0000)
2226 #define MCF_EPORT_EPPAR_EPPA14_RISING   (0x1000)
2227 #define MCF_EPORT_EPPAR_EPPA14_FALLING  (0x2000)
2228 #define MCF_EPORT_EPPAR_EPPA14_BOTH     (0x3000)
2229 #define MCF_EPORT_EPPAR_EPPA13_LEVEL    (0x0000)
2230 #define MCF_EPORT_EPPAR_EPPA13_RISING   (0x0400)
2231 #define MCF_EPORT_EPPAR_EPPA13_FALLING  (0x0800)
2232 #define MCF_EPORT_EPPAR_EPPA13_BOTH     (0x0C00)
2233 #define MCF_EPORT_EPPAR_EPPA12_LEVEL    (0x0000)
2234 #define MCF_EPORT_EPPAR_EPPA12_RISING   (0x0100)
2235 #define MCF_EPORT_EPPAR_EPPA12_FALLING  (0x0200)
2236 #define MCF_EPORT_EPPAR_EPPA12_BOTH     (0x0300)
2237 #define MCF_EPORT_EPPAR_EPPA11_LEVEL    (0x0000)
2238 #define MCF_EPORT_EPPAR_EPPA11_RISING   (0x0040)
2239 #define MCF_EPORT_EPPAR_EPPA11_FALLING  (0x0080)
2240 #define MCF_EPORT_EPPAR_EPPA11_BOTH     (0x00C0)
2241 #define MCF_EPORT_EPPAR_EPPA10_LEVEL    (0x0000)
2242 #define MCF_EPORT_EPPAR_EPPA10_RISING   (0x0010)
2243 #define MCF_EPORT_EPPAR_EPPA10_FALLING  (0x0020)
2244 #define MCF_EPORT_EPPAR_EPPA10_BOTH     (0x0030)
2245 #define MCF_EPORT_EPPAR_EPPA9_LEVEL     (0x0000)
2246 #define MCF_EPORT_EPPAR_EPPA9_RISING    (0x0004)
2247 #define MCF_EPORT_EPPAR_EPPA9_FALLING   (0x0008)
2248 #define MCF_EPORT_EPPAR_EPPA9_BOTH      (0x000C)
2249 #define MCF_EPORT_EPPAR_EPPA8_LEVEL     (0x0000)
2250 #define MCF_EPORT_EPPAR_EPPA8_RISING    (0x0001)
2251 #define MCF_EPORT_EPPAR_EPPA8_FALLING   (0x0002)
2252 #define MCF_EPORT_EPPAR_EPPA8_BOTH      (0x0003)
2253 #define MCF_EPORT_EPPAR_EPPA7_LEVEL     (0x0000)
2254 #define MCF_EPORT_EPPAR_EPPA7_RISING    (0x4000)
2255 #define MCF_EPORT_EPPAR_EPPA7_FALLING   (0x8000)
2256 #define MCF_EPORT_EPPAR_EPPA7_BOTH      (0xC000)
2257 #define MCF_EPORT_EPPAR_EPPA6_LEVEL     (0x0000)
2258 #define MCF_EPORT_EPPAR_EPPA6_RISING    (0x1000)
2259 #define MCF_EPORT_EPPAR_EPPA6_FALLING   (0x2000)
2260 #define MCF_EPORT_EPPAR_EPPA6_BOTH      (0x3000)
2261 #define MCF_EPORT_EPPAR_EPPA5_LEVEL     (0x0000)
2262 #define MCF_EPORT_EPPAR_EPPA5_RISING    (0x0400)
2263 #define MCF_EPORT_EPPAR_EPPA5_FALLING   (0x0800)
2264 #define MCF_EPORT_EPPAR_EPPA5_BOTH      (0x0C00)
2265 #define MCF_EPORT_EPPAR_EPPA4_LEVEL     (0x0000)
2266 #define MCF_EPORT_EPPAR_EPPA4_RISING    (0x0100)
2267 #define MCF_EPORT_EPPAR_EPPA4_FALLING   (0x0200)
2268 #define MCF_EPORT_EPPAR_EPPA4_BOTH      (0x0300)
2269 #define MCF_EPORT_EPPAR_EPPA3_LEVEL     (0x0000)
2270 #define MCF_EPORT_EPPAR_EPPA3_RISING    (0x0040)
2271 #define MCF_EPORT_EPPAR_EPPA3_FALLING   (0x0080)
2272 #define MCF_EPORT_EPPAR_EPPA3_BOTH      (0x00C0)
2273 #define MCF_EPORT_EPPAR_EPPA2_LEVEL     (0x0000)
2274 #define MCF_EPORT_EPPAR_EPPA2_RISING    (0x0010)
2275 #define MCF_EPORT_EPPAR_EPPA2_FALLING   (0x0020)
2276 #define MCF_EPORT_EPPAR_EPPA2_BOTH      (0x0030)
2277 #define MCF_EPORT_EPPAR_EPPA1_LEVEL     (0x0000)
2278 #define MCF_EPORT_EPPAR_EPPA1_RISING    (0x0004)
2279 #define MCF_EPORT_EPPAR_EPPA1_FALLING   (0x0008)
2280 #define MCF_EPORT_EPPAR_EPPA1_BOTH      (0x000C)
2281 
2282 /* Bit definitions and macros for MCF_EPORT_EPDDR */
2283 #define MCF_EPORT_EPDDR_EPDD1           (0x02)
2284 #define MCF_EPORT_EPDDR_EPDD2           (0x04)
2285 #define MCF_EPORT_EPDDR_EPDD3           (0x08)
2286 #define MCF_EPORT_EPDDR_EPDD4           (0x10)
2287 #define MCF_EPORT_EPDDR_EPDD5           (0x20)
2288 #define MCF_EPORT_EPDDR_EPDD6           (0x40)
2289 #define MCF_EPORT_EPDDR_EPDD7           (0x80)
2290 #define MCF_EPORT_EPDDR_EPDD8           (0x01)
2291 #define MCF_EPORT_EPDDR_EPDD9           (0x02)
2292 #define MCF_EPORT_EPDDR_EPDD10          (0x04)
2293 #define MCF_EPORT_EPDDR_EPDD11          (0x08)
2294 #define MCF_EPORT_EPDDR_EPDD12          (0x10)
2295 #define MCF_EPORT_EPDDR_EPDD13          (0x20)
2296 #define MCF_EPORT_EPDDR_EPDD14          (0x40)
2297 #define MCF_EPORT_EPDDR_EPDD15          (0x80)
2298 
2299 /* Bit definitions and macros for MCF_EPORT_EPIER */
2300 #define MCF_EPORT_EPIER_EPIE1           (0x02)
2301 #define MCF_EPORT_EPIER_EPIE2           (0x04)
2302 #define MCF_EPORT_EPIER_EPIE3           (0x08)
2303 #define MCF_EPORT_EPIER_EPIE4           (0x10)
2304 #define MCF_EPORT_EPIER_EPIE5           (0x20)
2305 #define MCF_EPORT_EPIER_EPIE6           (0x40)
2306 #define MCF_EPORT_EPIER_EPIE7           (0x80)
2307 #define MCF_EPORT_EPIER_EPIE8           (0x01)
2308 #define MCF_EPORT_EPIER_EPIE9           (0x02)
2309 #define MCF_EPORT_EPIER_EPIE10          (0x04)
2310 #define MCF_EPORT_EPIER_EPIE11          (0x08)
2311 #define MCF_EPORT_EPIER_EPIE12          (0x10)
2312 #define MCF_EPORT_EPIER_EPIE13          (0x20)
2313 #define MCF_EPORT_EPIER_EPIE14          (0x40)
2314 #define MCF_EPORT_EPIER_EPIE15          (0x80)
2315 
2316 /* Bit definitions and macros for MCF_EPORT_EPDR */
2317 #define MCF_EPORT_EPDR_EPD1             (0x02)
2318 #define MCF_EPORT_EPDR_EPD2             (0x04)
2319 #define MCF_EPORT_EPDR_EPD3             (0x08)
2320 #define MCF_EPORT_EPDR_EPD4             (0x10)
2321 #define MCF_EPORT_EPDR_EPD5             (0x20)
2322 #define MCF_EPORT_EPDR_EPD6             (0x40)
2323 #define MCF_EPORT_EPDR_EPD7             (0x80)
2324 #define MCF_EPORT_EPDR_EPD8             (0x01)
2325 #define MCF_EPORT_EPDR_EPD9             (0x02)
2326 #define MCF_EPORT_EPDR_EPD10            (0x04)
2327 #define MCF_EPORT_EPDR_EPD11            (0x08)
2328 #define MCF_EPORT_EPDR_EPD12            (0x10)
2329 #define MCF_EPORT_EPDR_EPD13            (0x20)
2330 #define MCF_EPORT_EPDR_EPD14            (0x40)
2331 #define MCF_EPORT_EPDR_EPD15            (0x80)
2332 
2333 /* Bit definitions and macros for MCF_EPORT_EPPDR */
2334 #define MCF_EPORT_EPPDR_EPPD1           (0x02)
2335 #define MCF_EPORT_EPPDR_EPPD2           (0x04)
2336 #define MCF_EPORT_EPPDR_EPPD3           (0x08)
2337 #define MCF_EPORT_EPPDR_EPPD4           (0x10)
2338 #define MCF_EPORT_EPPDR_EPPD5           (0x20)
2339 #define MCF_EPORT_EPPDR_EPPD6           (0x40)
2340 #define MCF_EPORT_EPPDR_EPPD7           (0x80)
2341 #define MCF_EPORT_EPPDR_EPPD8           (0x01)
2342 #define MCF_EPORT_EPPDR_EPPD9           (0x02)
2343 #define MCF_EPORT_EPPDR_EPPD10          (0x04)
2344 #define MCF_EPORT_EPPDR_EPPD11          (0x08)
2345 #define MCF_EPORT_EPPDR_EPPD12          (0x10)
2346 #define MCF_EPORT_EPPDR_EPPD13          (0x20)
2347 #define MCF_EPORT_EPPDR_EPPD14          (0x40)
2348 #define MCF_EPORT_EPPDR_EPPD15          (0x80)
2349 
2350 /* Bit definitions and macros for MCF_EPORT_EPFR */
2351 #define MCF_EPORT_EPFR_EPF1             (0x02)
2352 #define MCF_EPORT_EPFR_EPF2             (0x04)
2353 #define MCF_EPORT_EPFR_EPF3             (0x08)
2354 #define MCF_EPORT_EPFR_EPF4             (0x10)
2355 #define MCF_EPORT_EPFR_EPF5             (0x20)
2356 #define MCF_EPORT_EPFR_EPF6             (0x40)
2357 #define MCF_EPORT_EPFR_EPF7             (0x80)
2358 #define MCF_EPORT_EPFR_EPF8             (0x01)
2359 #define MCF_EPORT_EPFR_EPF9             (0x02)
2360 #define MCF_EPORT_EPFR_EPF10            (0x04)
2361 #define MCF_EPORT_EPFR_EPF11            (0x08)
2362 #define MCF_EPORT_EPFR_EPF12            (0x10)
2363 #define MCF_EPORT_EPFR_EPF13            (0x20)
2364 #define MCF_EPORT_EPFR_EPF14            (0x40)
2365 #define MCF_EPORT_EPFR_EPF15            (0x80)
2366 
2367 /*********************************************************************
2368 *
2369 * Programmable Interrupt Timer Modules (PIT)
2370 *
2371 *********************************************************************/
2372 
2373 /* Register read/write macros */
2374 #define MCF_PIT0_PCSR        (*(vuint16*)(&__IPSBAR[0x150000]))
2375 #define MCF_PIT0_PMR         (*(vuint16*)(&__IPSBAR[0x150002]))
2376 #define MCF_PIT0_PCNTR       (*(vuint16*)(&__IPSBAR[0x150004]))
2377 #define MCF_PIT1_PCSR        (*(vuint16*)(&__IPSBAR[0x160000]))
2378 #define MCF_PIT1_PMR         (*(vuint16*)(&__IPSBAR[0x160002]))
2379 #define MCF_PIT1_PCNTR       (*(vuint16*)(&__IPSBAR[0x160004]))
2380 #define MCF_PIT_PCSR(x)      (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)]))
2381 #define MCF_PIT_PMR(x)       (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)]))
2382 #define MCF_PIT_PCNTR(x)     (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)]))
2383 
2384 /* Bit definitions and macros for MCF_PIT_PCSR */
2385 #define MCF_PIT_PCSR_EN      (0x0001)
2386 #define MCF_PIT_PCSR_RLD     (0x0002)
2387 #define MCF_PIT_PCSR_PIF     (0x0004)
2388 #define MCF_PIT_PCSR_PIE     (0x0008)
2389 #define MCF_PIT_PCSR_OVW     (0x0010)
2390 #define MCF_PIT_PCSR_HALTED  (0x0020)
2391 #define MCF_PIT_PCSR_DOZE    (0x0040)
2392 #define MCF_PIT_PCSR_PRE(x)  (((x)&0x000F)<<8)
2393 
2394 /* Bit definitions and macros for MCF_PIT_PMR */
2395 #define MCF_PIT_PMR_PM(x)    (((x)&0xFFFF)<<0)
2396 
2397 /* Bit definitions and macros for MCF_PIT_PCNTR */
2398 #define MCF_PIT_PCNTR_PC(x)  (((x)&0xFFFF)<<0)
2399 
2400 /*********************************************************************
2401 *
2402 * Analog-to-Digital Converter (ADC)
2403 *
2404 *********************************************************************/
2405 
2406 /* Register read/write macros */
2407 #define MCF_ADC_CTRL1              (*(vuint16*)(&__IPSBAR[0x190000]))
2408 #define MCF_ADC_CTRL2              (*(vuint16*)(&__IPSBAR[0x190002]))
2409 #define MCF_ADC_ADZCC              (*(vuint16*)(&__IPSBAR[0x190004]))
2410 #define MCF_ADC_ADLST1             (*(vuint16*)(&__IPSBAR[0x190006]))
2411 #define MCF_ADC_ADLST2             (*(vuint16*)(&__IPSBAR[0x190008]))
2412 #define MCF_ADC_ADSDIS             (*(vuint16*)(&__IPSBAR[0x19000A]))
2413 #define MCF_ADC_ADSTAT             (*(vuint16*)(&__IPSBAR[0x19000C]))
2414 #define MCF_ADC_ADLSTAT            (*(vuint16*)(&__IPSBAR[0x19000E]))
2415 #define MCF_ADC_ADZCSTAT           (*(vuint16*)(&__IPSBAR[0x190010]))
2416 #define MCF_ADC_ADRSLT0            (*(vuint16*)(&__IPSBAR[0x190012]))
2417 #define MCF_ADC_ADRSLT1            (*(vuint16*)(&__IPSBAR[0x190014]))
2418 #define MCF_ADC_ADRSLT2            (*(vuint16*)(&__IPSBAR[0x190016]))
2419 #define MCF_ADC_ADRSLT3            (*(vuint16*)(&__IPSBAR[0x190018]))
2420 #define MCF_ADC_ADRSLT4            (*(vuint16*)(&__IPSBAR[0x19001A]))
2421 #define MCF_ADC_ADRSLT5            (*(vuint16*)(&__IPSBAR[0x19001C]))
2422 #define MCF_ADC_ADRSLT6            (*(vuint16*)(&__IPSBAR[0x19001E]))
2423 #define MCF_ADC_ADRSLT7            (*(vuint16*)(&__IPSBAR[0x190020]))
2424 #define MCF_ADC_ADRSLT(x)          (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)]))
2425 #define MCF_ADC_ADLLMT0            (*(vuint16*)(&__IPSBAR[0x190022]))
2426 #define MCF_ADC_ADLLMT1            (*(vuint16*)(&__IPSBAR[0x190024]))
2427 #define MCF_ADC_ADLLMT2            (*(vuint16*)(&__IPSBAR[0x190026]))
2428 #define MCF_ADC_ADLLMT3            (*(vuint16*)(&__IPSBAR[0x190028]))
2429 #define MCF_ADC_ADLLMT4            (*(vuint16*)(&__IPSBAR[0x19002A]))
2430 #define MCF_ADC_ADLLMT5            (*(vuint16*)(&__IPSBAR[0x19002C]))
2431 #define MCF_ADC_ADLLMT6            (*(vuint16*)(&__IPSBAR[0x19002E]))
2432 #define MCF_ADC_ADLLMT7            (*(vuint16*)(&__IPSBAR[0x190030]))
2433 #define MCF_ADC_ADLLMT(x)          (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)]))
2434 #define MCF_ADC_ADHLMT0            (*(vuint16*)(&__IPSBAR[0x190032]))
2435 #define MCF_ADC_ADHLMT1            (*(vuint16*)(&__IPSBAR[0x190034]))
2436 #define MCF_ADC_ADHLMT2            (*(vuint16*)(&__IPSBAR[0x190036]))
2437 #define MCF_ADC_ADHLMT3            (*(vuint16*)(&__IPSBAR[0x190038]))
2438 #define MCF_ADC_ADHLMT4            (*(vuint16*)(&__IPSBAR[0x19003A]))
2439 #define MCF_ADC_ADHLMT5            (*(vuint16*)(&__IPSBAR[0x19003C]))
2440 #define MCF_ADC_ADHLMT6            (*(vuint16*)(&__IPSBAR[0x19003E]))
2441 #define MCF_ADC_ADHLMT7            (*(vuint16*)(&__IPSBAR[0x190040]))
2442 #define MCF_ADC_ADHLMT(x)          (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)]))
2443 #define MCF_ADC_ADOFS0             (*(vuint16*)(&__IPSBAR[0x190042]))
2444 #define MCF_ADC_ADOFS1             (*(vuint16*)(&__IPSBAR[0x190044]))
2445 #define MCF_ADC_ADOFS2             (*(vuint16*)(&__IPSBAR[0x190046]))
2446 #define MCF_ADC_ADOFS3             (*(vuint16*)(&__IPSBAR[0x190048]))
2447 #define MCF_ADC_ADOFS4             (*(vuint16*)(&__IPSBAR[0x19004A]))
2448 #define MCF_ADC_ADOFS5             (*(vuint16*)(&__IPSBAR[0x19004C]))
2449 #define MCF_ADC_ADOFS6             (*(vuint16*)(&__IPSBAR[0x19004E]))
2450 #define MCF_ADC_ADOFS7             (*(vuint16*)(&__IPSBAR[0x190050]))
2451 #define MCF_ADC_ADOFS(x)           (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)]))
2452 #define MCF_ADC_POWER              (*(vuint16*)(&__IPSBAR[0x190052]))
2453 #define MCF_ADC_CAL                (*(vuint16*)(&__IPSBAR[0x190054]))
2454 
2455 /* Bit definitions and macros for MCF_ADC_CTRL1 */
2456 #define MCF_ADC_CTRL1_SMODE(x)     (((x)&0x0007)<<0)
2457 #define MCF_ADC_CTRL1_CHNCFG(x)    (((x)&0x000F)<<4)
2458 #define MCF_ADC_CTRL1_HLMTIE       (0x0100)
2459 #define MCF_ADC_CTRL1_LLMTIE       (0x0200)
2460 #define MCF_ADC_CTRL1_ZCIE         (0x0400)
2461 #define MCF_ADC_CTRL1_EOSIE0       (0x0800)
2462 #define MCF_ADC_CTRL1_SYNC0        (0x1000)
2463 #define MCF_ADC_CTRL1_START0       (0x2000)
2464 #define MCF_ADC_CTRL1_STOP0        (0x4000)
2465 
2466 /* Bit definitions and macros for MCF_ADC_CTRL2 */
2467 #define MCF_ADC_CTRL2_DIV(x)       (((x)&0x001F)<<0)
2468 #define MCF_ADC_CTRL2_SIMULT       (0x0020)
2469 #define MCF_ADC_CTRL2_EOSIE1       (0x0800)
2470 #define MCF_ADC_CTRL2_SYNC1        (0x1000)
2471 #define MCF_ADC_CTRL2_START1       (0x2000)
2472 #define MCF_ADC_CTRL2_STOP1        (0x4000)
2473 
2474 /* Bit definitions and macros for MCF_ADC_ADZCC */
2475 #define MCF_ADC_ADZCC_ZCE0(x)      (((x)&0x0003)<<0)
2476 #define MCF_ADC_ADZCC_ZCE1(x)      (((x)&0x0003)<<2)
2477 #define MCF_ADC_ADZCC_ZCE2(x)      (((x)&0x0003)<<4)
2478 #define MCF_ADC_ADZCC_ZCE3(x)      (((x)&0x0003)<<6)
2479 #define MCF_ADC_ADZCC_ZCE4(x)      (((x)&0x0003)<<8)
2480 #define MCF_ADC_ADZCC_ZCE5(x)      (((x)&0x0003)<<10)
2481 #define MCF_ADC_ADZCC_ZCE6(x)      (((x)&0x0003)<<12)
2482 #define MCF_ADC_ADZCC_ZCE7(x)      (((x)&0x0003)<<14)
2483 
2484 /* Bit definitions and macros for MCF_ADC_ADLST1 */
2485 #define MCF_ADC_ADLST1_SAMPLE0(x)  (((x)&0x0007)<<0)
2486 #define MCF_ADC_ADLST1_SAMPLE1(x)  (((x)&0x0007)<<4)
2487 #define MCF_ADC_ADLST1_SAMPLE2(x)  (((x)&0x0007)<<8)
2488 #define MCF_ADC_ADLST1_SAMPLE3(x)  (((x)&0x0007)<<12)
2489 
2490 /* Bit definitions and macros for MCF_ADC_ADLST2 */
2491 #define MCF_ADC_ADLST2_SAMPLE4(x)  (((x)&0x0007)<<0)
2492 #define MCF_ADC_ADLST2_SAMPLE5(x)  (((x)&0x0007)<<4)
2493 #define MCF_ADC_ADLST2_SAMPLE6(x)  (((x)&0x0007)<<8)
2494 #define MCF_ADC_ADLST2_SAMPLE7(x)  (((x)&0x0007)<<12)
2495 
2496 /* Bit definitions and macros for MCF_ADC_ADSDIS */
2497 #define MCF_ADC_ADSDIS_DS0         (0x0001)
2498 #define MCF_ADC_ADSDIS_DS1         (0x0002)
2499 #define MCF_ADC_ADSDIS_DS2         (0x0004)
2500 #define MCF_ADC_ADSDIS_DS3         (0x0008)
2501 #define MCF_ADC_ADSDIS_DS4         (0x0010)
2502 #define MCF_ADC_ADSDIS_DS5         (0x0020)
2503 #define MCF_ADC_ADSDIS_DS6         (0x0040)
2504 #define MCF_ADC_ADSDIS_DS7         (0x0080)
2505 
2506 /* Bit definitions and macros for MCF_ADC_ADSTAT */
2507 #define MCF_ADC_ADSTAT_RDY0        (0x0001)
2508 #define MCF_ADC_ADSTAT_RDY1        (0x0002)
2509 #define MCF_ADC_ADSTAT_RDY2        (0x0004)
2510 #define MCF_ADC_ADSTAT_RDY3        (0x0008)
2511 #define MCF_ADC_ADSTAT_RDY4        (0x0010)
2512 #define MCF_ADC_ADSTAT_RDY5        (0x0020)
2513 #define MCF_ADC_ADSTAT_RDY6        (0x0040)
2514 #define MCF_ADC_ADSTAT_RDY7        (0x0080)
2515 #define MCF_ADC_ADSTAT_HLMT        (0x0100)
2516 #define MCF_ADC_ADSTAT_LLMTI       (0x0200)
2517 #define MCF_ADC_ADSTAT_ZCI         (0x0400)
2518 #define MCF_ADC_ADSTAT_EOSI        (0x0800)
2519 #define MCF_ADC_ADSTAT_CIP         (0x8000)
2520 
2521 /* Bit definitions and macros for MCF_ADC_ADLSTAT */
2522 #define MCF_ADC_ADLSTAT_LLS0       (0x0001)
2523 #define MCF_ADC_ADLSTAT_LLS1       (0x0002)
2524 #define MCF_ADC_ADLSTAT_LLS2       (0x0004)
2525 #define MCF_ADC_ADLSTAT_LLS3       (0x0008)
2526 #define MCF_ADC_ADLSTAT_LLS4       (0x0010)
2527 #define MCF_ADC_ADLSTAT_LLS5       (0x0020)
2528 #define MCF_ADC_ADLSTAT_LLS6       (0x0040)
2529 #define MCF_ADC_ADLSTAT_LLS7       (0x0080)
2530 #define MCF_ADC_ADLSTAT_HLS0       (0x0100)
2531 #define MCF_ADC_ADLSTAT_HLS1       (0x0200)
2532 #define MCF_ADC_ADLSTAT_HLS2       (0x0400)
2533 #define MCF_ADC_ADLSTAT_HLS3       (0x0800)
2534 #define MCF_ADC_ADLSTAT_HLS4       (0x1000)
2535 #define MCF_ADC_ADLSTAT_HLS5       (0x2000)
2536 #define MCF_ADC_ADLSTAT_HLS6       (0x4000)
2537 #define MCF_ADC_ADLSTAT_HLS7       (0x8000)
2538 
2539 /* Bit definitions and macros for MCF_ADC_ADZCSTAT */
2540 #define MCF_ADC_ADZCSTAT_ZCS0      (0x0001)
2541 #define MCF_ADC_ADZCSTAT_ZCS1      (0x0002)
2542 #define MCF_ADC_ADZCSTAT_ZCS2      (0x0004)
2543 #define MCF_ADC_ADZCSTAT_ZCS3      (0x0008)
2544 #define MCF_ADC_ADZCSTAT_ZCS4      (0x0010)
2545 #define MCF_ADC_ADZCSTAT_ZCS5      (0x0020)
2546 #define MCF_ADC_ADZCSTAT_ZCS6      (0x0040)
2547 #define MCF_ADC_ADZCSTAT_ZCS7      (0x0080)
2548 
2549 /* Bit definitions and macros for MCF_ADC_ADRSLT */
2550 #define MCF_ADC_ADRSLT_RSLT(x)     (((x)&0x0FFF)<<3)
2551 #define MCF_ADC_ADRSLT_SEXT        (0x8000)
2552 
2553 /* Bit definitions and macros for MCF_ADC_ADLLMT */
2554 #define MCF_ADC_ADLLMT_LLMT(x)     (((x)&0x0FFF)<<3)
2555 
2556 /* Bit definitions and macros for MCF_ADC_ADHLMT */
2557 #define MCF_ADC_ADHLMT_HLMT(x)     (((x)&0x0FFF)<<3)
2558 
2559 /* Bit definitions and macros for MCF_ADC_ADOFS */
2560 #define MCF_ADC_ADOFS_OFFSET(x)    (((x)&0x0FFF)<<3)
2561 
2562 /* Bit definitions and macros for MCF_ADC_POWER */
2563 #define MCF_ADC_POWER_PD0          (0x0001)
2564 #define MCF_ADC_POWER_PD1          (0x0002)
2565 #define MCF_ADC_POWER_PD2          (0x0004)
2566 #define MCF_ADC_POWER_APD          (0x0008)
2567 #define MCF_ADC_POWER_PUDELAY(x)   (((x)&0x003F)<<4)
2568 #define MCF_ADC_POWER_PSTS0        (0x0400)
2569 #define MCF_ADC_POWER_PSTS1        (0x0800)
2570 #define MCF_ADC_POWER_PSTS2        (0x1000)
2571 #define MCF_ADC_POWER_ASTBY        (0x8000)
2572 
2573 /* Bit definitions and macros for MCF_ADC_CAL */
2574 #define MCF_ADC_CAL_CAL0           (0x0001)
2575 #define MCF_ADC_CAL_CRS0           (0x0002)
2576 #define MCF_ADC_CAL_CAL1           (0x0004)
2577 #define MCF_ADC_CAL_CRS1           (0x0008)
2578 
2579 /*********************************************************************
2580 *
2581 * General Purpose Timer (GPT)
2582 *
2583 *********************************************************************/
2584 
2585 /* Register read/write macros */
2586 #define MCF_GPT_GPTIOS                    (*(vuint8 *)(&__IPSBAR[0x1A0000]))
2587 #define MCF_GPT_GPTCFORC                  (*(vuint8 *)(&__IPSBAR[0x1A0001]))
2588 #define MCF_GPT_GPTOC3M                   (*(vuint8 *)(&__IPSBAR[0x1A0002]))
2589 #define MCF_GPT_GPTOC3D                   (*(vuint8 *)(&__IPSBAR[0x1A0003]))
2590 #define MCF_GPT_GPTCNT                    (*(vuint16*)(&__IPSBAR[0x1A0004]))
2591 #define MCF_GPT_GPTSCR1                   (*(vuint8 *)(&__IPSBAR[0x1A0006]))
2592 #define MCF_GPT_GPTTOV                    (*(vuint8 *)(&__IPSBAR[0x1A0008]))
2593 #define MCF_GPT_GPTCTL1                   (*(vuint8 *)(&__IPSBAR[0x1A0009]))
2594 #define MCF_GPT_GPTCTL2                   (*(vuint8 *)(&__IPSBAR[0x1A000B]))
2595 #define MCF_GPT_GPTIE                     (*(vuint8 *)(&__IPSBAR[0x1A000C]))
2596 #define MCF_GPT_GPTSCR2                   (*(vuint8 *)(&__IPSBAR[0x1A000D]))
2597 #define MCF_GPT_GPTFLG1                   (*(vuint8 *)(&__IPSBAR[0x1A000E]))
2598 #define MCF_GPT_GPTFLG2                   (*(vuint8 *)(&__IPSBAR[0x1A000F]))
2599 #define MCF_GPT_GPTC0                     (*(vuint16*)(&__IPSBAR[0x1A0010]))
2600 #define MCF_GPT_GPTC1                     (*(vuint16*)(&__IPSBAR[0x1A0012]))
2601 #define MCF_GPT_GPTC2                     (*(vuint16*)(&__IPSBAR[0x1A0014]))
2602 #define MCF_GPT_GPTC3                     (*(vuint16*)(&__IPSBAR[0x1A0016]))
2603 #define MCF_GPT_GPTC(x)                   (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)]))
2604 #define MCF_GPT_GPTPACTL                  (*(vuint8 *)(&__IPSBAR[0x1A0018]))
2605 #define MCF_GPT_GPTPAFLG                  (*(vuint8 *)(&__IPSBAR[0x1A0019]))
2606 #define MCF_GPT_GPTPACNT                  (*(vuint16*)(&__IPSBAR[0x1A001A]))
2607 #define MCF_GPT_GPTPORT                   (*(vuint8 *)(&__IPSBAR[0x1A001D]))
2608 #define MCF_GPT_GPTDDR                    (*(vuint8 *)(&__IPSBAR[0x1A001E]))
2609 
2610 /* Bit definitions and macros for MCF_GPT_GPTIOS */
2611 #define MCF_GPT_GPTIOS_IOS0               (0x01)
2612 #define MCF_GPT_GPTIOS_IOS1               (0x02)
2613 #define MCF_GPT_GPTIOS_IOS2               (0x04)
2614 #define MCF_GPT_GPTIOS_IOS3               (0x08)
2615 
2616 /* Bit definitions and macros for MCF_GPT_GPTCFORC */
2617 #define MCF_GPT_GPTCFORC_FOC0             (0x01)
2618 #define MCF_GPT_GPTCFORC_FOC1             (0x02)
2619 #define MCF_GPT_GPTCFORC_FOC2             (0x04)
2620 #define MCF_GPT_GPTCFORC_FOC3             (0x08)
2621 
2622 /* Bit definitions and macros for MCF_GPT_GPTOC3D */
2623 #define MCF_GPT_GPTOC3D_OC3D0             (0x01)
2624 #define MCF_GPT_GPTOC3D_OC3D1             (0x02)
2625 #define MCF_GPT_GPTOC3D_OC3D2             (0x04)
2626 #define MCF_GPT_GPTOC3D_OC3D3             (0x08)
2627 
2628 /* Bit definitions and macros for MCF_GPT_GPTSCR1 */
2629 #define MCF_GPT_GPTSCR1_TFFCA             (0x10)
2630 #define MCF_GPT_GPTSCR1_GPTEN             (0x80)
2631 
2632 /* Bit definitions and macros for MCF_GPT_GPTTOV */
2633 #define MCF_GPT_GPTTOV_TOV0               (0x01)
2634 #define MCF_GPT_GPTTOV_TOV1               (0x02)
2635 #define MCF_GPT_GPTTOV_TOV2               (0x04)
2636 #define MCF_GPT_GPTTOV_TOV3               (0x08)
2637 
2638 /* Bit definitions and macros for MCF_GPT_GPTCTL1 */
2639 #define MCF_GPT_GPTCTL1_OL0               (0x01)
2640 #define MCF_GPT_GPTCTL1_OM0               (0x02)
2641 #define MCF_GPT_GPTCTL1_OL1               (0x04)
2642 #define MCF_GPT_GPTCTL1_OM1               (0x08)
2643 #define MCF_GPT_GPTCTL1_OL2               (0x10)
2644 #define MCF_GPT_GPTCTL1_OM2               (0x20)
2645 #define MCF_GPT_GPTCTL1_OL3               (0x40)
2646 #define MCF_GPT_GPTCTL1_OM3               (0x80)
2647 #define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING   ((0x00))
2648 #define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE    ((0x40))
2649 #define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR     ((0x80))
2650 #define MCF_GPT_GPTCTL1_OUTPUT3_SET       ((0xC0))
2651 #define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING   ((0x00))
2652 #define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE    ((0x10))
2653 #define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR     ((0x20))
2654 #define MCF_GPT_GPTCTL1_OUTPUT2_SET       ((0x30))
2655 #define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING   ((0x00))
2656 #define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE    ((0x04))
2657 #define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR     ((0x08))
2658 #define MCF_GPT_GPTCTL1_OUTPUT1_SET       ((0x0C))
2659 #define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING   ((0x00))
2660 #define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE    ((0x01))
2661 #define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR     ((0x02))
2662 #define MCF_GPT_GPTCTL1_OUTPUT0_SET       ((0x03))
2663 
2664 /* Bit definitions and macros for MCF_GPT_GPTCTL2 */
2665 #define MCF_GPT_GPTCTL2_EDG0A             (0x01)
2666 #define MCF_GPT_GPTCTL2_EDG0B             (0x02)
2667 #define MCF_GPT_GPTCTL2_EDG1A             (0x04)
2668 #define MCF_GPT_GPTCTL2_EDG1B             (0x08)
2669 #define MCF_GPT_GPTCTL2_EDG2A             (0x10)
2670 #define MCF_GPT_GPTCTL2_EDG2B             (0x20)
2671 #define MCF_GPT_GPTCTL2_EDG3A             (0x40)
2672 #define MCF_GPT_GPTCTL2_EDG3B             (0x80)
2673 #define MCF_GPT_GPTCTL2_INPUT3_DISABLED   ((0x00))
2674 #define MCF_GPT_GPTCTL2_INPUT3_RISING     ((0x40))
2675 #define MCF_GPT_GPTCTL2_INPUT3_FALLING    ((0x80))
2676 #define MCF_GPT_GPTCTL2_INPUT3_ANY        ((0xC0))
2677 #define MCF_GPT_GPTCTL2_INPUT2_DISABLED   ((0x00))
2678 #define MCF_GPT_GPTCTL2_INPUT2_RISING     ((0x10))
2679 #define MCF_GPT_GPTCTL2_INPUT2_FALLING    ((0x20))
2680 #define MCF_GPT_GPTCTL2_INPUT2_ANY        ((0x30))
2681 #define MCF_GPT_GPTCTL2_INPUT1_DISABLED   ((0x00))
2682 #define MCF_GPT_GPTCTL2_INPUT1_RISING     ((0x04))
2683 #define MCF_GPT_GPTCTL2_INPUT1_FALLING    ((0x08))
2684 #define MCF_GPT_GPTCTL2_INPUT1_ANY        ((0x0C))
2685 #define MCF_GPT_GPTCTL2_INPUT0_DISABLED   ((0x00))
2686 #define MCF_GPT_GPTCTL2_INPUT0_RISING     ((0x01))
2687 #define MCF_GPT_GPTCTL2_INPUT0_FALLING    ((0x02))
2688 #define MCF_GPT_GPTCTL2_INPUT0_ANY        ((0x03))
2689 
2690 /* Bit definitions and macros for MCF_GPT_GPTIE */
2691 #define MCF_GPT_GPTIE_CI0                 (0x01)
2692 #define MCF_GPT_GPTIE_CI1                 (0x02)
2693 #define MCF_GPT_GPTIE_CI2                 (0x04)
2694 #define MCF_GPT_GPTIE_CI3                 (0x08)
2695 
2696 /* Bit definitions and macros for MCF_GPT_GPTSCR2 */
2697 #define MCF_GPT_GPTSCR2_PR(x)             (((x)&0x07)<<0)
2698 #define MCF_GPT_GPTSCR2_TCRE              (0x08)
2699 #define MCF_GPT_GPTSCR2_RDPT              (0x10)
2700 #define MCF_GPT_GPTSCR2_PUPT              (0x20)
2701 #define MCF_GPT_GPTSCR2_TOI               (0x80)
2702 #define MCF_GPT_GPTSCR2_PR_1              ((0x00))
2703 #define MCF_GPT_GPTSCR2_PR_2              ((0x01))
2704 #define MCF_GPT_GPTSCR2_PR_4              ((0x02))
2705 #define MCF_GPT_GPTSCR2_PR_8              ((0x03))
2706 #define MCF_GPT_GPTSCR2_PR_16             ((0x04))
2707 #define MCF_GPT_GPTSCR2_PR_32             ((0x05))
2708 #define MCF_GPT_GPTSCR2_PR_64             ((0x06))
2709 #define MCF_GPT_GPTSCR2_PR_128            ((0x07))
2710 
2711 /* Bit definitions and macros for MCF_GPT_GPTFLG1 */
2712 #define MCF_GPT_GPTFLG1_CF0               (0x01)
2713 #define MCF_GPT_GPTFLG1_CF1               (0x02)
2714 #define MCF_GPT_GPTFLG1_CF2               (0x04)
2715 #define MCF_GPT_GPTFLG1_CF3               (0x08)
2716 
2717 /* Bit definitions and macros for MCF_GPT_GPTFLG2 */
2718 #define MCF_GPT_GPTFLG2_CF0               (0x01)
2719 #define MCF_GPT_GPTFLG2_CF1               (0x02)
2720 #define MCF_GPT_GPTFLG2_CF2               (0x04)
2721 #define MCF_GPT_GPTFLG2_CF3               (0x08)
2722 #define MCF_GPT_GPTFLG2_TOF               (0x80)
2723 
2724 /* Bit definitions and macros for MCF_GPT_GPTC */
2725 #define MCF_GPT_GPTC_CCNT(x)              (((x)&0xFFFF)<<0)
2726 
2727 /* Bit definitions and macros for MCF_GPT_GPTPACTL */
2728 #define MCF_GPT_GPTPACTL_PAI              (0x01)
2729 #define MCF_GPT_GPTPACTL_PAOVI            (0x02)
2730 #define MCF_GPT_GPTPACTL_CLK(x)           (((x)&0x03)<<2)
2731 #define MCF_GPT_GPTPACTL_PEDGE            (0x10)
2732 #define MCF_GPT_GPTPACTL_PAMOD            (0x20)
2733 #define MCF_GPT_GPTPACTL_PAE              (0x40)
2734 #define MCF_GPT_GPTPACTL_CLK_GPTPR        ((0x00))
2735 #define MCF_GPT_GPTPACTL_CLK_PACLK        ((0x01))
2736 #define MCF_GPT_GPTPACTL_CLK_PACLK_256    ((0x02))
2737 #define MCF_GPT_GPTPACTL_CLK_PACLK_65536  ((0x03))
2738 
2739 /* Bit definitions and macros for MCF_GPT_GPTPAFLG */
2740 #define MCF_GPT_GPTPAFLG_PAIF             (0x01)
2741 #define MCF_GPT_GPTPAFLG_PAOVF            (0x02)
2742 
2743 /* Bit definitions and macros for MCF_GPT_GPTPACNT */
2744 #define MCF_GPT_GPTPACNT_PACNT(x)         (((x)&0xFFFF)<<0)
2745 
2746 /* Bit definitions and macros for MCF_GPT_GPTPORT */
2747 #define MCF_GPT_GPTPORT_PORTT(x)          (((x)&0x0F)<<0)
2748 
2749 /* Bit definitions and macros for MCF_GPT_GPTDDR */
2750 #define MCF_GPT_GPTDDR_DDRT0              (0x01)
2751 #define MCF_GPT_GPTDDR_DDRT1              (0x02)
2752 #define MCF_GPT_GPTDDR_DDRT2              (0x04)
2753 #define MCF_GPT_GPTDDR_DDRT3              (0x08)
2754 
2755 /*********************************************************************
2756 *
2757 * Pulse Width Modulation (PWM)
2758 *
2759 *********************************************************************/
2760 
2761 /* Register read/write macros */
2762 #define MCF_PWM_PWME               (*(vuint8 *)(&__IPSBAR[0x1B0000]))
2763 #define MCF_PWM_PWMPOL             (*(vuint8 *)(&__IPSBAR[0x1B0001]))
2764 #define MCF_PWM_PWMCLK             (*(vuint8 *)(&__IPSBAR[0x1B0002]))
2765 #define MCF_PWM_PWMPRCLK           (*(vuint8 *)(&__IPSBAR[0x1B0003]))
2766 #define MCF_PWM_PWMCAE             (*(vuint8 *)(&__IPSBAR[0x1B0004]))
2767 #define MCF_PWM_PWMCTL             (*(vuint8 *)(&__IPSBAR[0x1B0005]))
2768 #define MCF_PWM_PWMSCLA            (*(vuint8 *)(&__IPSBAR[0x1B0008]))
2769 #define MCF_PWM_PWMSCLB            (*(vuint8 *)(&__IPSBAR[0x1B0009]))
2770 #define MCF_PWM_PWMCNT0            (*(vuint8 *)(&__IPSBAR[0x1B000C]))
2771 #define MCF_PWM_PWMCNT1            (*(vuint8 *)(&__IPSBAR[0x1B000D]))
2772 #define MCF_PWM_PWMCNT2            (*(vuint8 *)(&__IPSBAR[0x1B000E]))
2773 #define MCF_PWM_PWMCNT3            (*(vuint8 *)(&__IPSBAR[0x1B000F]))
2774 #define MCF_PWM_PWMCNT4            (*(vuint8 *)(&__IPSBAR[0x1B0010]))
2775 #define MCF_PWM_PWMCNT5            (*(vuint8 *)(&__IPSBAR[0x1B0011]))
2776 #define MCF_PWM_PWMCNT6            (*(vuint8 *)(&__IPSBAR[0x1B0012]))
2777 #define MCF_PWM_PWMCNT7            (*(vuint8 *)(&__IPSBAR[0x1B0013]))
2778 #define MCF_PWM_PWMCNT(x)          (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)]))
2779 #define MCF_PWM_PWMPER0            (*(vuint8 *)(&__IPSBAR[0x1B0014]))
2780 #define MCF_PWM_PWMPER1            (*(vuint8 *)(&__IPSBAR[0x1B0015]))
2781 #define MCF_PWM_PWMPER2            (*(vuint8 *)(&__IPSBAR[0x1B0016]))
2782 #define MCF_PWM_PWMPER3            (*(vuint8 *)(&__IPSBAR[0x1B0017]))
2783 #define MCF_PWM_PWMPER4            (*(vuint8 *)(&__IPSBAR[0x1B0018]))
2784 #define MCF_PWM_PWMPER5            (*(vuint8 *)(&__IPSBAR[0x1B0019]))
2785 #define MCF_PWM_PWMPER6            (*(vuint8 *)(&__IPSBAR[0x1B001A]))
2786 #define MCF_PWM_PWMPER7            (*(vuint8 *)(&__IPSBAR[0x1B001B]))
2787 #define MCF_PWM_PWMPER(x)          (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)]))
2788 #define MCF_PWM_PWMDTY0            (*(vuint8 *)(&__IPSBAR[0x1B001C]))
2789 #define MCF_PWM_PWMDTY1            (*(vuint8 *)(&__IPSBAR[0x1B001D]))
2790 #define MCF_PWM_PWMDTY2            (*(vuint8 *)(&__IPSBAR[0x1B001E]))
2791 #define MCF_PWM_PWMDTY3            (*(vuint8 *)(&__IPSBAR[0x1B001F]))
2792 #define MCF_PWM_PWMDTY4            (*(vuint8 *)(&__IPSBAR[0x1B0020]))
2793 #define MCF_PWM_PWMDTY5            (*(vuint8 *)(&__IPSBAR[0x1B0021]))
2794 #define MCF_PWM_PWMDTY6            (*(vuint8 *)(&__IPSBAR[0x1B0022]))
2795 #define MCF_PWM_PWMDTY7            (*(vuint8 *)(&__IPSBAR[0x1B0023]))
2796 #define MCF_PWM_PWMDTY(x)          (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)]))
2797 #define MCF_PWM_PWMSDN             (*(vuint8 *)(&__IPSBAR[0x1B0024]))
2798 
2799 /* Bit definitions and macros for MCF_PWM_PWME */
2800 #define MCF_PWM_PWME_PWME0         (0x01)
2801 #define MCF_PWM_PWME_PWME1         (0x02)
2802 #define MCF_PWM_PWME_PWME2         (0x04)
2803 #define MCF_PWM_PWME_PWME3         (0x08)
2804 
2805 /* Bit definitions and macros for MCF_PWM_PWMPOL */
2806 #define MCF_PWM_PWMPOL_PPOL0       (0x01)
2807 #define MCF_PWM_PWMPOL_PPOL1       (0x02)
2808 #define MCF_PWM_PWMPOL_PPOL2       (0x04)
2809 #define MCF_PWM_PWMPOL_PPOL3       (0x08)
2810 
2811 /* Bit definitions and macros for MCF_PWM_PWMCLK */
2812 #define MCF_PWM_PWMCLK_PCLK0       (0x01)
2813 #define MCF_PWM_PWMCLK_PCLK1       (0x02)
2814 #define MCF_PWM_PWMCLK_PCLK2       (0x04)
2815 #define MCF_PWM_PWMCLK_PCLK3       (0x08)
2816 
2817 /* Bit definitions and macros for MCF_PWM_PWMPRCLK */
2818 #define MCF_PWM_PWMPRCLK_PCKA(x)   (((x)&0x07)<<0)
2819 #define MCF_PWM_PWMPRCLK_PCKB(x)   (((x)&0x07)<<4)
2820 
2821 /* Bit definitions and macros for MCF_PWM_PWMCAE */
2822 #define MCF_PWM_PWMCAE_CAE0        (0x01)
2823 #define MCF_PWM_PWMCAE_CAE1        (0x02)
2824 #define MCF_PWM_PWMCAE_CAE2        (0x04)
2825 #define MCF_PWM_PWMCAE_CAE3        (0x08)
2826 
2827 /* Bit definitions and macros for MCF_PWM_PWMCTL */
2828 #define MCF_PWM_PWMCTL_PFRZ        (0x04)
2829 #define MCF_PWM_PWMCTL_PSWAI       (0x08)
2830 #define MCF_PWM_PWMCTL_CON01       (0x10)
2831 #define MCF_PWM_PWMCTL_CON23       (0x20)
2832 
2833 /* Bit definitions and macros for MCF_PWM_PWMSCLA */
2834 #define MCF_PWM_PWMSCLA_SCALEA(x)  (((x)&0xFF)<<0)
2835 
2836 /* Bit definitions and macros for MCF_PWM_PWMSCLB */
2837 #define MCF_PWM_PWMSCLB_SCALEB(x)  (((x)&0xFF)<<0)
2838 
2839 /* Bit definitions and macros for MCF_PWM_PWMCNT */
2840 #define MCF_PWM_PWMCNT_COUNT(x)    (((x)&0xFF)<<0)
2841 
2842 /* Bit definitions and macros for MCF_PWM_PWMPER */
2843 #define MCF_PWM_PWMPER_PERIOD(x)   (((x)&0xFF)<<0)
2844 
2845 /* Bit definitions and macros for MCF_PWM_PWMDTY */
2846 #define MCF_PWM_PWMDTY_DUTY(x)     (((x)&0xFF)<<0)
2847 
2848 /* Bit definitions and macros for MCF_PWM_PWMSDN */
2849 #define MCF_PWM_PWMSDN_SDNEN       (0x01)
2850 #define MCF_PWM_PWMSDN_PWM7IL      (0x02)
2851 #define MCF_PWM_PWMSDN_PWM7IN      (0x04)
2852 #define MCF_PWM_PWMSDN_LVL         (0x10)
2853 #define MCF_PWM_PWMSDN_RESTART     (0x20)
2854 #define MCF_PWM_PWMSDN_IE          (0x40)
2855 #define MCF_PWM_PWMSDN_IF          (0x80)
2856 
2857 /*********************************************************************
2858 *
2859 * FlexCAN Module (CAN)
2860 *
2861 *********************************************************************/
2862 
2863 /* Register read/write macros */
2864 #define MCF_CAN_CANMCR                   (*(vuint32*)(&__IPSBAR[0x1C0000]))
2865 #define MCF_CAN_CANCTRL                  (*(vuint32*)(&__IPSBAR[0x1C0004]))
2866 #define MCF_CAN_TIMER                    (*(vuint32*)(&__IPSBAR[0x1C0008]))
2867 #define MCF_CAN_RXGMASK                  (*(vuint32*)(&__IPSBAR[0x1C0010]))
2868 #define MCF_CAN_RX14MASK                 (*(vuint32*)(&__IPSBAR[0x1C0014]))
2869 #define MCF_CAN_RX15MASK                 (*(vuint32*)(&__IPSBAR[0x1C0018]))
2870 #define MCF_CAN_ERRCNT                   (*(vuint32*)(&__IPSBAR[0x1C001C]))
2871 #define MCF_CAN_ERRSTAT                  (*(vuint32*)(&__IPSBAR[0x1C0020]))
2872 #define MCF_CAN_IMASK                    (*(vuint32*)(&__IPSBAR[0x1C0028]))
2873 #define MCF_CAN_IFLAG                    (*(vuint32*)(&__IPSBAR[0x1C0030]))
2874 
2875 /* Bit definitions and macros for MCF_CAN_CANMCR */
2876 #define MCF_CAN_CANMCR_MAXMB(x)          (((x)&0x0000000F)<<0)
2877 #define MCF_CAN_CANMCR_SUPV              (0x00800000)
2878 #define MCF_CAN_CANMCR_FRZACK            (0x01000000)
2879 #define MCF_CAN_CANMCR_SOFTRST           (0x02000000)
2880 #define MCF_CAN_CANMCR_HALT              (0x10000000)
2881 #define MCF_CAN_CANMCR_FRZ               (0x40000000)
2882 #define MCF_CAN_CANMCR_MDIS              (0x80000000)
2883 
2884 /* Bit definitions and macros for MCF_CAN_CANCTRL */
2885 #define MCF_CAN_CANCTRL_PROPSEG(x)       (((x)&0x00000007)<<0)
2886 #define MCF_CAN_CANCTRL_LOM              (0x00000008)
2887 #define MCF_CAN_CANCTRL_LBUF             (0x00000010)
2888 #define MCF_CAN_CANCTRL_TSYNC            (0x00000020)
2889 #define MCF_CAN_CANCTRL_BOFFREC          (0x00000040)
2890 #define MCF_CAN_CANCTRL_SAMP             (0x00000080)
2891 #define MCF_CAN_CANCTRL_LPB              (0x00001000)
2892 #define MCF_CAN_CANCTRL_CLKSRC           (0x00002000)
2893 #define MCF_CAN_CANCTRL_ERRMSK           (0x00004000)
2894 #define MCF_CAN_CANCTRL_BOFFMSK          (0x00008000)
2895 #define MCF_CAN_CANCTRL_PSEG2(x)         (((x)&0x00000007)<<16)
2896 #define MCF_CAN_CANCTRL_PSEG1(x)         (((x)&0x00000007)<<19)
2897 #define MCF_CAN_CANCTRL_RJW(x)           (((x)&0x00000003)<<22)
2898 #define MCF_CAN_CANCTRL_PRESDIV(x)       (((x)&0x000000FF)<<24)
2899 
2900 /* Bit definitions and macros for MCF_CAN_TIMER */
2901 #define MCF_CAN_TIMER_TIMER(x)           (((x)&0x0000FFFF)<<0)
2902 
2903 /* Bit definitions and macros for MCF_CAN_RXGMASK */
2904 #define MCF_CAN_RXGMASK_MI(x)            (((x)&0x1FFFFFFF)<<0)
2905 
2906 /* Bit definitions and macros for MCF_CAN_RX14MASK */
2907 #define MCF_CAN_RX14MASK_MI(x)           (((x)&0x1FFFFFFF)<<0)
2908 
2909 /* Bit definitions and macros for MCF_CAN_RX15MASK */
2910 #define MCF_CAN_RX15MASK_MI(x)           (((x)&0x1FFFFFFF)<<0)
2911 
2912 /* Bit definitions and macros for MCF_CAN_ERRCNT */
2913 #define MCF_CAN_ERRCNT_TXECTR(x)         (((x)&0x000000FF)<<0)
2914 #define MCF_CAN_ERRCNT_RXECTR(x)         (((x)&0x000000FF)<<8)
2915 
2916 /* Bit definitions and macros for MCF_CAN_ERRSTAT */
2917 #define MCF_CAN_ERRSTAT_WAKINT           (0x00000001)
2918 #define MCF_CAN_ERRSTAT_ERRINT           (0x00000002)
2919 #define MCF_CAN_ERRSTAT_BOFFINT          (0x00000004)
2920 #define MCF_CAN_ERRSTAT_FLTCONF(x)       (((x)&0x00000003)<<4)
2921 #define MCF_CAN_ERRSTAT_TXRX             (0x00000040)
2922 #define MCF_CAN_ERRSTAT_IDLE             (0x00000080)
2923 #define MCF_CAN_ERRSTAT_RXWRN            (0x00000100)
2924 #define MCF_CAN_ERRSTAT_TXWRN            (0x00000200)
2925 #define MCF_CAN_ERRSTAT_STFERR           (0x00000400)
2926 #define MCF_CAN_ERRSTAT_FRMERR           (0x00000800)
2927 #define MCF_CAN_ERRSTAT_CRCERR           (0x00001000)
2928 #define MCF_CAN_ERRSTAT_ACKERR           (0x00002000)
2929 #define MCF_CAN_ERRSTAT_BITERR(x)        (((x)&0x00000003)<<14)
2930 #define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE   (0x00000000)
2931 #define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE  (0x00000010)
2932 #define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF   (0x00000020)
2933 
2934 /* Bit definitions and macros for MCF_CAN_IMASK */
2935 #define MCF_CAN_IMASK_BUF(x)             (1<<x)
2936 
2937 /* Bit definitions and macros for MCF_CAN_IFLAG */
2938 #define MCF_CAN_IFLAG_BUF(x)             (1<<x)
2939 
2940 /*********************************************************************
2941 *
2942 * ColdFire Flash Module (CFM)
2943 *
2944 *********************************************************************/
2945 
2946 /* Register read/write macros */
2947 #define MCF_CFM_CFMMCR           (*(vuint16*)(&__IPSBAR[0x1D0000]))
2948 #define MCF_CFM_CFMCLKD          (*(vuint8 *)(&__IPSBAR[0x1D0002]))
2949 #define MCF_CFM_CFMSEC           (*(vuint32*)(&__IPSBAR[0x1D0008]))
2950 #define MCF_CFM_CFMPROT          (*(vuint32*)(&__IPSBAR[0x1D0010]))
2951 #define MCF_CFM_CFMSACC          (*(vuint32*)(&__IPSBAR[0x1D0014]))
2952 #define MCF_CFM_CFMDACC          (*(vuint32*)(&__IPSBAR[0x1D0018]))
2953 #define MCF_CFM_CFMUSTAT         (*(vuint8 *)(&__IPSBAR[0x1D0020]))
2954 #define MCF_CFM_CFMCMD           (*(vuint8 *)(&__IPSBAR[0x1D0024]))
2955 
2956 /* Bit definitions and macros for MCF_CFM_CFMMCR */
2957 #define MCF_CFM_CFMMCR_KEYACC    (0x0020)
2958 #define MCF_CFM_CFMMCR_CCIE      (0x0040)
2959 #define MCF_CFM_CFMMCR_CBEIE     (0x0080)
2960 #define MCF_CFM_CFMMCR_AEIE      (0x0100)
2961 #define MCF_CFM_CFMMCR_PVIE      (0x0200)
2962 #define MCF_CFM_CFMMCR_LOCK      (0x0400)
2963 
2964 /* Bit definitions and macros for MCF_CFM_CFMCLKD */
2965 #define MCF_CFM_CFMCLKD_DIV(x)   (((x)&0x3F)<<0)
2966 #define MCF_CFM_CFMCLKD_PRDIV8   (0x40)
2967 #define MCF_CFM_CFMCLKD_DIVLD    (0x80)
2968 
2969 /* Bit definitions and macros for MCF_CFM_CFMSEC */
2970 #define MCF_CFM_CFMSEC_SEC(x)    (((x)&0x0000FFFF)<<0)
2971 #define MCF_CFM_CFMSEC_SECSTAT   (0x40000000)
2972 #define MCF_CFM_CFMSEC_KEYEN     (0x80000000)
2973 
2974 /* Bit definitions and macros for MCF_CFM_CFMUSTAT */
2975 #define MCF_CFM_CFMUSTAT_BLANK   (0x04)
2976 #define MCF_CFM_CFMUSTAT_ACCERR  (0x10)
2977 #define MCF_CFM_CFMUSTAT_PVIOL   (0x20)
2978 #define MCF_CFM_CFMUSTAT_CCIF    (0x40)
2979 #define MCF_CFM_CFMUSTAT_CBEIF   (0x80)
2980 
2981 /* Bit definitions and macros for MCF_CFM_CFMCMD */
2982 #define MCF_CFM_CFMCMD_CMD(x)    (((x)&0x7F)<<0)
2983 #define MCF_CFM_CFMCMD_RDARY1    (0x05)
2984 #define MCF_CFM_CFMCMD_PGM       (0x20)
2985 #define MCF_CFM_CFMCMD_PGERS     (0x40)
2986 #define MCF_CFM_CFMCMD_MASERS    (0x41)
2987 #define MCF_CFM_CFMCMD_PGERSVER  (0x06)
2988 
2989 /*********************************************************************
2990 *
2991 * Interrupt Controller (INTC_IACK)
2992 *
2993 *********************************************************************/
2994 
2995 /* Register read/write macros */
2996 #define MCF_INTC_IACK_GSWIACK            (*(vuint8 *)(&__IPSBAR[0x000FE0]))
2997 #define MCF_INTC_IACK_GL1IACK            (*(vuint8 *)(&__IPSBAR[0x000FE4]))
2998 #define MCF_INTC_IACK_GL2IACK            (*(vuint8 *)(&__IPSBAR[0x000FE8]))
2999 #define MCF_INTC_IACK_GL3IACK            (*(vuint8 *)(&__IPSBAR[0x000FEC]))
3000 #define MCF_INTC_IACK_GL4IACK            (*(vuint8 *)(&__IPSBAR[0x000FF0]))
3001 #define MCF_INTC_IACK_GL5IACK            (*(vuint8 *)(&__IPSBAR[0x000FF4]))
3002 #define MCF_INTC_IACK_GL6IACK            (*(vuint8 *)(&__IPSBAR[0x000FF8]))
3003 #define MCF_INTC_IACK_GL7IACK            (*(vuint8 *)(&__IPSBAR[0x000FFC]))
3004 #define MCF_INTC_IACK_GLIACK(x)          (*(vuint8 *)(&__IPSBAR[0x000FE4+((x-1)*0x004)]))
3005 
3006 /* Bit definitions and macros for MCF_INTC_IACK_GSWIACK */
3007 #define MCF_INTC_IACK_GSWIACK_VECTOR(x)  (((x)&0xFF)<<0)
3008 
3009 /* Bit definitions and macros for MCF_INTC_IACK_GLIACK */
3010 #define MCF_INTC_IACK_GLIACK_VECTOR(x)   (((x)&0xFF)<<0)
3011 
3012 /*********************************************************************
3013 *
3014 * Fast Ethernet Controller (FEC)
3015 *
3016 *********************************************************************/
3017 
3018 /* Register read/write macros */
3019 #define MCF_FEC_EIR                   (*(vuint32*)(&__IPSBAR[0x001004]))
3020 #define MCF_FEC_EIMR                  (*(vuint32*)(&__IPSBAR[0x001008]))
3021 #define MCF_FEC_RDAR                  (*(vuint32*)(&__IPSBAR[0x001010]))
3022 #define MCF_FEC_TDAR                  (*(vuint32*)(&__IPSBAR[0x001014]))
3023 #define MCF_FEC_ECR                   (*(vuint32*)(&__IPSBAR[0x001024]))
3024 #define MCF_FEC_MMFR                  (*(vuint32*)(&__IPSBAR[0x001040]))
3025 #define MCF_FEC_MSCR                  (*(vuint32*)(&__IPSBAR[0x001044]))
3026 #define MCF_FEC_MIBC                  (*(vuint32*)(&__IPSBAR[0x001064]))
3027 #define MCF_FEC_RCR                   (*(vuint32*)(&__IPSBAR[0x001084]))
3028 #define MCF_FEC_TCR                   (*(vuint32*)(&__IPSBAR[0x0010C4]))
3029 #define MCF_FEC_PALR                  (*(vuint32*)(&__IPSBAR[0x0010E4]))
3030 #define MCF_FEC_PAUR                  (*(vuint32*)(&__IPSBAR[0x0010E8]))
3031 #define MCF_FEC_OPD                   (*(vuint32*)(&__IPSBAR[0x0010EC]))
3032 #define MCF_FEC_IAUR                  (*(vuint32*)(&__IPSBAR[0x001118]))
3033 #define MCF_FEC_IALR                  (*(vuint32*)(&__IPSBAR[0x00111C]))
3034 #define MCF_FEC_GAUR                  (*(vuint32*)(&__IPSBAR[0x001120]))
3035 #define MCF_FEC_GALR                  (*(vuint32*)(&__IPSBAR[0x001124]))
3036 #define MCF_FEC_TFWR                  (*(vuint32*)(&__IPSBAR[0x001144]))
3037 #define MCF_FEC_FRBR                  (*(vuint32*)(&__IPSBAR[0x00114C]))
3038 #define MCF_FEC_FRSR                  (*(vuint32*)(&__IPSBAR[0x001150]))
3039 #define MCF_FEC_ERDSR                 (*(vuint32*)(&__IPSBAR[0x001180]))
3040 #define MCF_FEC_ETDSR                 (*(vuint32*)(&__IPSBAR[0x001184]))
3041 #define MCF_FEC_EMRBR                 (*(vuint32*)(&__IPSBAR[0x001188]))
3042 #define MCF_FEC_RMON_T_DROP           (*(vuint32*)(&__IPSBAR[0x001200]))
3043 #define MCF_FEC_RMON_T_PACKETS        (*(vuint32*)(&__IPSBAR[0x001204]))
3044 #define MCF_FEC_RMON_T_BC_PKT         (*(vuint32*)(&__IPSBAR[0x001208]))
3045 #define MCF_FEC_RMON_T_MC_PKT         (*(vuint32*)(&__IPSBAR[0x00120C]))
3046 #define MCF_FEC_RMON_T_CRC_ALIGN      (*(vuint32*)(&__IPSBAR[0x001210]))
3047 #define MCF_FEC_RMON_T_UNDERSIZE      (*(vuint32*)(&__IPSBAR[0x001214]))
3048 #define MCF_FEC_RMON_T_OVERSIZE       (*(vuint32*)(&__IPSBAR[0x001218]))
3049 #define MCF_FEC_RMON_T_FRAG           (*(vuint32*)(&__IPSBAR[0x00121C]))
3050 #define MCF_FEC_RMON_T_JAB            (*(vuint32*)(&__IPSBAR[0x001220]))
3051 #define MCF_FEC_RMON_T_COL            (*(vuint32*)(&__IPSBAR[0x001224]))
3052 #define MCF_FEC_RMON_T_P64            (*(vuint32*)(&__IPSBAR[0x001228]))
3053 #define MCF_FEC_RMON_T_P65TO127       (*(vuint32*)(&__IPSBAR[0x00122C]))
3054 #define MCF_FEC_RMON_T_P128TO255      (*(vuint32*)(&__IPSBAR[0x001230]))
3055 #define MCF_FEC_RMON_T_P256TO511      (*(vuint32*)(&__IPSBAR[0x001234]))
3056 #define MCF_FEC_RMON_T_P512TO1023     (*(vuint32*)(&__IPSBAR[0x001238]))
3057 #define MCF_FEC_RMON_T_P1024TO2047    (*(vuint32*)(&__IPSBAR[0x00123C]))
3058 #define MCF_FEC_RMON_T_P_GTE2048      (*(vuint32*)(&__IPSBAR[0x001240]))
3059 #define MCF_FEC_RMON_T_OCTETS         (*(vuint32*)(&__IPSBAR[0x001244]))
3060 #define MCF_FEC_IEEE_T_DROP           (*(vuint32*)(&__IPSBAR[0x001248]))
3061 #define MCF_FEC_IEEE_T_FRAME_OK       (*(vuint32*)(&__IPSBAR[0x00124C]))
3062 #define MCF_FEC_IEEE_T_1COL           (*(vuint32*)(&__IPSBAR[0x001250]))
3063 #define MCF_FEC_IEEE_T_MCOL           (*(vuint32*)(&__IPSBAR[0x001254]))
3064 #define MCF_FEC_IEEE_T_DEF            (*(vuint32*)(&__IPSBAR[0x001258]))
3065 #define MCF_FEC_IEEE_T_LCOL           (*(vuint32*)(&__IPSBAR[0x00125C]))
3066 #define MCF_FEC_IEEE_T_EXCOL          (*(vuint32*)(&__IPSBAR[0x001260]))
3067 #define MCF_FEC_IEEE_T_MACERR         (*(vuint32*)(&__IPSBAR[0x001264]))
3068 #define MCF_FEC_IEEE_T_CSERR          (*(vuint32*)(&__IPSBAR[0x001268]))
3069 #define MCF_FEC_IEEE_T_SQE            (*(vuint32*)(&__IPSBAR[0x00126C]))
3070 #define MCF_FEC_IEEE_T_FDXFC          (*(vuint32*)(&__IPSBAR[0x001270]))
3071 #define MCF_FEC_IEEE_T_OCTETS_OK      (*(vuint32*)(&__IPSBAR[0x001274]))
3072 #define MCF_FEC_RMON_R_PACKETS        (*(vuint32*)(&__IPSBAR[0x001284]))
3073 #define MCF_FEC_RMON_R_BC_PKT         (*(vuint32*)(&__IPSBAR[0x001288]))
3074 #define MCF_FEC_RMON_R_MC_PKT         (*(vuint32*)(&__IPSBAR[0x00128C]))
3075 #define MCF_FEC_RMON_R_CRC_ALIGN      (*(vuint32*)(&__IPSBAR[0x001290]))
3076 #define MCF_FEC_RMON_R_UNDERSIZE      (*(vuint32*)(&__IPSBAR[0x001294]))
3077 #define MCF_FEC_RMON_R_OVERSIZE       (*(vuint32*)(&__IPSBAR[0x001298]))
3078 #define MCF_FEC_RMON_R_FRAG           (*(vuint32*)(&__IPSBAR[0x00129C]))
3079 #define MCF_FEC_RMON_R_JAB            (*(vuint32*)(&__IPSBAR[0x0012A0]))
3080 #define MCF_FEC_RMON_R_RESVD_0        (*(vuint32*)(&__IPSBAR[0x0012A4]))
3081 #define MCF_FEC_RMON_R_P64            (*(vuint32*)(&__IPSBAR[0x0012A8]))
3082 #define MCF_FEC_RMON_R_P65TO127       (*(vuint32*)(&__IPSBAR[0x0012AC]))
3083 #define MCF_FEC_RMON_R_P128TO255      (*(vuint32*)(&__IPSBAR[0x0012B0]))
3084 #define MCF_FEC_RMON_R_P256TO511      (*(vuint32*)(&__IPSBAR[0x0012B4]))
3085 #define MCF_FEC_RMON_R_512TO1023      (*(vuint32*)(&__IPSBAR[0x0012B8]))
3086 #define MCF_FEC_RMON_R_P_GTE2048      (*(vuint32*)(&__IPSBAR[0x0012C0]))
3087 #define MCF_FEC_RMON_R_1024TO2047     (*(vuint32*)(&__IPSBAR[0x0012BC]))
3088 #define MCF_FEC_RMON_R_OCTETS         (*(vuint32*)(&__IPSBAR[0x0012C4]))
3089 #define MCF_FEC_IEEE_R_DROP           (*(vuint32*)(&__IPSBAR[0x0012C8]))
3090 #define MCF_FEC_IEEE_R_FRAME_OK       (*(vuint32*)(&__IPSBAR[0x0012CC]))
3091 #define MCF_FEC_IEEE_R_CRC            (*(vuint32*)(&__IPSBAR[0x0012D0]))
3092 #define MCF_FEC_IEEE_R_ALIGN          (*(vuint32*)(&__IPSBAR[0x0012D4]))
3093 #define MCF_FEC_IEEE_R_MACERR         (*(vuint32*)(&__IPSBAR[0x0012D8]))
3094 #define MCF_FEC_IEEE_R_FDXFC          (*(vuint32*)(&__IPSBAR[0x0012DC]))
3095 #define MCF_FEC_IEEE_R_OCTETS_OK      (*(vuint32*)(&__IPSBAR[0x0012E0]))
3096 
3097 /* Bit definitions and macros for MCF_FEC_EIR */
3098 #define MCF_FEC_EIR_UN                (0x00080000)
3099 #define MCF_FEC_EIR_RL                (0x00100000)
3100 #define MCF_FEC_EIR_LC                (0x00200000)
3101 #define MCF_FEC_EIR_EBERR             (0x00400000)
3102 #define MCF_FEC_EIR_MII               (0x00800000)
3103 #define MCF_FEC_EIR_RXB               (0x01000000)
3104 #define MCF_FEC_EIR_RXF               (0x02000000)
3105 #define MCF_FEC_EIR_TXB               (0x04000000)
3106 #define MCF_FEC_EIR_TXF               (0x08000000)
3107 #define MCF_FEC_EIR_GRA               (0x10000000)
3108 #define MCF_FEC_EIR_BABT              (0x20000000)
3109 #define MCF_FEC_EIR_BABR              (0x40000000)
3110 #define MCF_FEC_EIR_HBERR             (0x80000000)
3111 #define MCF_FEC_EIR_CLEAR_ALL         (0xFFFFFFFF)
3112 
3113 /* Bit definitions and macros for MCF_FEC_EIMR */
3114 #define MCF_FEC_EIMR_UN               (0x00080000)
3115 #define MCF_FEC_EIMR_RL               (0x00100000)
3116 #define MCF_FEC_EIMR_LC               (0x00200000)
3117 #define MCF_FEC_EIMR_EBERR            (0x00400000)
3118 #define MCF_FEC_EIMR_MII              (0x00800000)
3119 #define MCF_FEC_EIMR_RXB              (0x01000000)
3120 #define MCF_FEC_EIMR_RXF              (0x02000000)
3121 #define MCF_FEC_EIMR_TXB              (0x04000000)
3122 #define MCF_FEC_EIMR_TXF              (0x08000000)
3123 #define MCF_FEC_EIMR_GRA              (0x10000000)
3124 #define MCF_FEC_EIMR_BABT             (0x20000000)
3125 #define MCF_FEC_EIMR_BABR             (0x40000000)
3126 #define MCF_FEC_EIMR_HBERR            (0x80000000)
3127 #define MCF_FEC_EIMR_MASK_ALL         (0x00000000)
3128 #define MCF_FEC_EIMR_UNMASK_ALL       (0xFFFFFFFF)
3129 
3130 /* Bit definitions and macros for MCF_FEC_RDAR */
3131 #define MCF_FEC_RDAR_R_DES_ACTIVE     (0x01000000)
3132 
3133 /* Bit definitions and macros for MCF_FEC_TDAR */
3134 #define MCF_FEC_TDAR_X_DES_ACTIVE     (0x01000000)
3135 
3136 /* Bit definitions and macros for MCF_FEC_ECR */
3137 #define MCF_FEC_ECR_RESET             (0x00000001)
3138 #define MCF_FEC_ECR_ETHER_EN          (0x00000002)
3139 
3140 /* Bit definitions and macros for MCF_FEC_MMFR */
3141 #define MCF_FEC_MMFR_DATA(x)          (((x)&0x0000FFFF)<<0)
3142 #define MCF_FEC_MMFR_TA(x)            (((x)&0x00000003)<<16)
3143 #define MCF_FEC_MMFR_RA(x)            (((x)&0x0000001F)<<18)
3144 #define MCF_FEC_MMFR_PA(x)            (((x)&0x0000001F)<<23)
3145 #define MCF_FEC_MMFR_OP(x)            (((x)&0x00000003)<<28)
3146 #define MCF_FEC_MMFR_ST(x)            (((x)&0x00000003)<<30)
3147 #define MCF_FEC_MMFR_ST_01            (0x40000000)
3148 #define MCF_FEC_MMFR_OP_READ          (0x20000000)
3149 #define MCF_FEC_MMFR_OP_WRITE         (0x10000000)
3150 #define MCF_FEC_MMFR_TA_10            (0x00020000)
3151 
3152 /* Bit definitions and macros for MCF_FEC_MSCR */
3153 #define MCF_FEC_MSCR_MII_SPEED(x)     (((x)&0x0000003F)<<1)
3154 #define MCF_FEC_MSCR_DIS_PREAMBLE     (0x00000080)
3155 
3156 /* Bit definitions and macros for MCF_FEC_MIBC */
3157 #define MCF_FEC_MIBC_MIB_IDLE         (0x40000000)
3158 #define MCF_FEC_MIBC_MIB_DISABLE      (0x80000000)
3159 
3160 /* Bit definitions and macros for MCF_FEC_RCR */
3161 #define MCF_FEC_RCR_LOOP              (0x00000001)
3162 #define MCF_FEC_RCR_DRT               (0x00000002)
3163 #define MCF_FEC_RCR_MII_MODE          (0x00000004)
3164 #define MCF_FEC_RCR_PROM              (0x00000008)
3165 #define MCF_FEC_RCR_BC_REJ            (0x00000010)
3166 #define MCF_FEC_RCR_FCE               (0x00000020)
3167 #define MCF_FEC_RCR_MAX_FL(x)         (((x)&0x000007FF)<<16)
3168 
3169 /* Bit definitions and macros for MCF_FEC_TCR */
3170 #define MCF_FEC_TCR_GTS               (0x00000001)
3171 #define MCF_FEC_TCR_HBC               (0x00000002)
3172 #define MCF_FEC_TCR_FDEN              (0x00000004)
3173 #define MCF_FEC_TCR_TFC_PAUSE         (0x00000008)
3174 #define MCF_FEC_TCR_RFC_PAUSE         (0x00000010)
3175 
3176 /* Bit definitions and macros for MCF_FEC_PALR */
3177 #define MCF_FEC_PALR_PADDR1(x)        (((x)&0xFFFFFFFF)<<0)
3178 
3179 /* Bit definitions and macros for MCF_FEC_PAUR */
3180 #define MCF_FEC_PAUR_TYPE(x)          (((x)&0x0000FFFF)<<0)
3181 #define MCF_FEC_PAUR_PADDR2(x)        (((x)&0x0000FFFF)<<16)
3182 
3183 /* Bit definitions and macros for MCF_FEC_OPD */
3184 #define MCF_FEC_OPD_PAUSE_DUR(x)      (((x)&0x0000FFFF)<<0)
3185 #define MCF_FEC_OPD_OPCODE(x)         (((x)&0x0000FFFF)<<16)
3186 
3187 /* Bit definitions and macros for MCF_FEC_IAUR */
3188 #define MCF_FEC_IAUR_IADDR1(x)        (((x)&0xFFFFFFFF)<<0)
3189 
3190 /* Bit definitions and macros for MCF_FEC_IALR */
3191 #define MCF_FEC_IALR_IADDR2(x)        (((x)&0xFFFFFFFF)<<0)
3192 
3193 /* Bit definitions and macros for MCF_FEC_GAUR */
3194 #define MCF_FEC_GAUR_GADDR1(x)        (((x)&0xFFFFFFFF)<<0)
3195 
3196 /* Bit definitions and macros for MCF_FEC_GALR */
3197 #define MCF_FEC_GALR_GADDR2(x)        (((x)&0xFFFFFFFF)<<0)
3198 
3199 /* Bit definitions and macros for MCF_FEC_TFWR */
3200 #define MCF_FEC_TFWR_X_WMRK(x)        (((x)&0x00000003)<<0)
3201 
3202 /* Bit definitions and macros for MCF_FEC_FRBR */
3203 #define MCF_FEC_FRBR_R_BOUND(x)       (((x)&0x000000FF)<<2)
3204 
3205 /* Bit definitions and macros for MCF_FEC_FRSR */
3206 #define MCF_FEC_FRSR_R_FSTART(x)      (((x)&0x000000FF)<<2)
3207 
3208 /* Bit definitions and macros for MCF_FEC_ERDSR */
3209 #define MCF_FEC_ERDSR_R_DES_START(x)  (((x)&0x3FFFFFFF)<<2)
3210 
3211 /* Bit definitions and macros for MCF_FEC_ETDSR */
3212 #define MCF_FEC_ETDSR_X_DES_START(x)  (((x)&0x3FFFFFFF)<<2)
3213 
3214 /* Bit definitions and macros for MCF_FEC_EMRBR */
3215 #define MCF_FEC_EMRBR_R_BUF_SIZE(x)   (((x)&0x0000007F)<<4)
3216 
3217 /*********************************************************************
3218 *
3219 * Ethernet PHY (PHY)
3220 *
3221 *********************************************************************/
3222 
3223 /* Register read/write macros */
3224 #define MCF_PHY_EPHYCTL0             (*(vuint8 *)(&__IPSBAR[0x1E0000]))
3225 #define MCF_PHY_EPHYCTL1             (*(vuint8 *)(&__IPSBAR[0x1E0001]))
3226 #define MCF_PHY_EPHYSR               (*(vuint8 *)(&__IPSBAR[0x1E0002]))
3227 
3228 /* Bit definitions and macros for MCF_PHY_EPHYCTL0 */
3229 #define MCF_PHY_EPHYCTL0_EPHYIEN     (0x01)
3230 #define MCF_PHY_EPHYCTL0_EPHYWAI     (0x04)
3231 #define MCF_PHY_EPHYCTL0_LEDEN       (0x08)
3232 #define MCF_PHY_EPHYCTL0_DIS10       (0x10)
3233 #define MCF_PHY_EPHYCTL0_DIS100      (0x20)
3234 #define MCF_PHY_EPHYCTL0_ANDIS       (0x40)
3235 #define MCF_PHY_EPHYCTL0_EPHYEN      (0x80)
3236 
3237 /* Bit definitions and macros for MCF_PHY_EPHYCTL1 */
3238 #define MCF_PHY_EPHYCTL1_PHYADDR(x)  (((x)&0x1F)<<0)
3239 
3240 /* Bit definitions and macros for MCF_PHY_EPHYSR */
3241 #define MCF_PHY_EPHYSR_EPHYIF        (0x01)
3242 #define MCF_PHY_EPHYSR_10DIS         (0x10)
3243 #define MCF_PHY_EPHYSR_100DIS        (0x20)
3244 
3245 /*********************************************************************
3246 *
3247 * Random Number Generator (RNG)
3248 *
3249 *********************************************************************/
3250 
3251 /* Register read/write macros */
3252 #define MCF_RNG_RNGCR             (*(vuint32*)(&__IPSBAR[0x1F0000]))
3253 #define MCF_RNG_RNGSR             (*(vuint32*)(&__IPSBAR[0x1F0004]))
3254 #define MCF_RNG_RNGER             (*(vuint32*)(&__IPSBAR[0x1F0008]))
3255 #define MCF_RNG_RNGOUT            (*(vuint32*)(&__IPSBAR[0x1F000C]))
3256 
3257 /* Bit definitions and macros for MCF_RNG_RNGCR */
3258 #define MCF_RNG_RNGCR_GO          (0x00000001)
3259 #define MCF_RNG_RNGCR_HA          (0x00000002)
3260 #define MCF_RNG_RNGCR_IM          (0x00000004)
3261 #define MCF_RNG_RNGCR_CI          (0x00000008)
3262 
3263 /* Bit definitions and macros for MCF_RNG_RNGSR */
3264 #define MCF_RNG_RNGSR_SV          (0x00000001)
3265 #define MCF_RNG_RNGSR_LRS         (0x00000002)
3266 #define MCF_RNG_RNGSR_FUF         (0x00000004)
3267 #define MCF_RNG_RNGSR_EI          (0x00000008)
3268 #define MCF_RNG_RNGSR_OFL(x)      (((x)&0x000000FF)<<8)
3269 #define MCF_RNG_RNGSR_OFS(x)      (((x)&0x000000FF)<<16)
3270 
3271 /* Bit definitions and macros for MCF_RNG_RNGER */
3272 #define MCF_RNG_RNGER_ENTROPY(x)  (((x)&0xFFFFFFFF)<<0)
3273 
3274 /* Bit definitions and macros for MCF_RNG_RNGOUT */
3275 #define MCF_RNG_RNGOUT_OUTPUT(x)  (((x)&0xFFFFFFFF)<<0)
3276 
3277 /*********************************************************************
3278 *
3279 * Real-time Clock (RTC)
3280 *
3281 *********************************************************************/
3282 
3283 /* Register read/write macros */
3284 #define MCF_RTC_HOURMIN              (*(vuint32*)(&__IPSBAR[0x0003C0]))
3285 #define MCF_RTC_SECONDS              (*(vuint32*)(&__IPSBAR[0x0003C4]))
3286 #define MCF_RTC_ALRM_HM              (*(vuint32*)(&__IPSBAR[0x0003C8]))
3287 #define MCF_RTC_ALRM_SEC             (*(vuint32*)(&__IPSBAR[0x0003CC]))
3288 #define MCF_RTC_CR                   (*(vuint32*)(&__IPSBAR[0x0003D0]))
3289 #define MCF_RTC_ISR                  (*(vuint32*)(&__IPSBAR[0x0003D4]))
3290 #define MCF_RTC_IER                  (*(vuint32*)(&__IPSBAR[0x0003D8]))
3291 #define MCF_RTC_STPWCH               (*(vuint32*)(&__IPSBAR[0x0003DC]))
3292 #define MCF_RTC_DAYS                 (*(vuint32*)(&__IPSBAR[0x0003E0]))
3293 #define MCF_RTC_ALRM_DAY             (*(vuint32*)(&__IPSBAR[0x0003E4]))
3294 
3295 /* Bit definitions and macros for MCF_RTC_HOURMIN */
3296 #define MCF_RTC_HOURMIN_MINUTES(x)   (((x)&0x0000003F)<<0)
3297 #define MCF_RTC_HOURMIN_HOURS(x)     (((x)&0x0000001F)<<8)
3298 
3299 /* Bit definitions and macros for MCF_RTC_SECONDS */
3300 #define MCF_RTC_SECONDS_SECONDS(x)   (((x)&0x0000003F)<<0)
3301 
3302 /* Bit definitions and macros for MCF_RTC_ALRM_HM */
3303 #define MCF_RTC_ALRM_HM_MINUTES(x)   (((x)&0x0000003F)<<0)
3304 #define MCF_RTC_ALRM_HM_HOURS(x)     (((x)&0x0000001F)<<8)
3305 
3306 /* Bit definitions and macros for MCF_RTC_ALRM_SEC */
3307 #define MCF_RTC_ALRM_SEC_SECONDS(x)  (((x)&0x0000003F)<<0)
3308 
3309 /* Bit definitions and macros for MCF_RTC_CR */
3310 #define MCF_RTC_CR_SWR               (0x00000001)
3311 #define MCF_RTC_CR_XTL(x)            (((x)&0x00000003)<<5)
3312 #define MCF_RTC_CR_EN                (0x00000080)
3313 #define MCF_RTC_CR_32768             (0x0)
3314 #define MCF_RTC_CR_32000             (0x1)
3315 #define MCF_RTC_CR_38400             (0x2)
3316 
3317 /* Bit definitions and macros for MCF_RTC_ISR */
3318 #define MCF_RTC_ISR_SW               (0x00000001)
3319 #define MCF_RTC_ISR_MIN              (0x00000002)
3320 #define MCF_RTC_ISR_ALM              (0x00000004)
3321 #define MCF_RTC_ISR_DAY              (0x00000008)
3322 #define MCF_RTC_ISR_1HZ              (0x00000010)
3323 #define MCF_RTC_ISR_HR               (0x00000020)
3324 #define MCF_RTC_ISR_2HZ              (0x00000080)
3325 #define MCF_RTC_ISR_SAM0             (0x00000100)
3326 #define MCF_RTC_ISR_SAM1             (0x00000200)
3327 #define MCF_RTC_ISR_SAM2             (0x00000400)
3328 #define MCF_RTC_ISR_SAM3             (0x00000800)
3329 #define MCF_RTC_ISR_SAM4             (0x00001000)
3330 #define MCF_RTC_ISR_SAM5             (0x00002000)
3331 #define MCF_RTC_ISR_SAM6             (0x00004000)
3332 #define MCF_RTC_ISR_SAM7             (0x00008000)
3333 
3334 /* Bit definitions and macros for MCF_RTC_IER */
3335 #define MCF_RTC_IER_SW               (0x00000001)
3336 #define MCF_RTC_IER_MIN              (0x00000002)
3337 #define MCF_RTC_IER_ALM              (0x00000004)
3338 #define MCF_RTC_IER_DAY              (0x00000008)
3339 #define MCF_RTC_IER_1HZ              (0x00000010)
3340 #define MCF_RTC_IER_HR               (0x00000020)
3341 #define MCF_RTC_IER_2HZ              (0x00000080)
3342 #define MCF_RTC_IER_SAM0             (0x00000100)
3343 #define MCF_RTC_IER_SAM1             (0x00000200)
3344 #define MCF_RTC_IER_SAM2             (0x00000400)
3345 #define MCF_RTC_IER_SAM3             (0x00000800)
3346 #define MCF_RTC_IER_SAM4             (0x00001000)
3347 #define MCF_RTC_IER_SAM5             (0x00002000)
3348 #define MCF_RTC_IER_SAM6             (0x00004000)
3349 #define MCF_RTC_IER_SAM7             (0x00008000)
3350 
3351 /* Bit definitions and macros for MCF_RTC_STPWCH */
3352 #define MCF_RTC_STPWCH_CNT(x)        (((x)&0x0000003F)<<0)
3353 
3354 /* Bit definitions and macros for MCF_RTC_DAYS */
3355 #define MCF_RTC_DAYS_DAYS(x)         (((x)&0x0000FFFF)<<0)
3356 
3357 /* Bit definitions and macros for MCF_RTC_ALRM_DAY */
3358 #define MCF_RTC_ALRM_DAY_DAYS(x)     (((x)&0x0000FFFF)<<0)
3359 
3360 /********************************************************************/
3361 
3362 #endif /* __MCF5223x_H__ */
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