genmcf548x/start/init548x.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * RTEMS generic mcf548x BSP
0005  *
0006  * The file contains the c part of MCF548x init code
0007  *
0008  * Parts of the code has been derived from the "dBUG source code"
0009  * package Freescale is providing for M548X EVBs. The usage of
0010  * the modified or unmodified code and it's integration into the
0011  * generic mcf548x BSP has been done according to the Freescale
0012  * license terms.
0013  *
0014  * The Freescale license terms can be reviewed in the file
0015  *
0016  *    LICENSE.Freescale
0017  *
0018  * The generic mcf548x BSP has been developed on the basic
0019  * structures and modules of the av5282 BSP.
0020  */
0021
0022 /*
0023  * Copyright (c) 2008 embedded brains GmbH & Co. KG
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions
0027  * are met:
0028  * 1. Redistributions of source code must retain the above copyright
0029  *    notice, this list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright
0031  *    notice, this list of conditions and the following disclaimer in the
0032  *    documentation and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0035  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0036  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0037  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0038  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0039  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0040  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0041  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0042  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0043  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0044  * POSSIBILITY OF SUCH DAMAGE.
0045  */
0046
0047 #include <bsp.h>
0048
0049 #include <string.h>
0050
0051 #include <bsp/linker-symbols.h>
0052
0053 #if defined(HAS_LOW_LEVEL_INIT)
0054 #define SYSTEM_PERIOD           10      /* system bus period in ns */
0055
0056 /* SDRAM Timing Parameters */
0057 #define SDRAM_TWR               2       /* in clocks */
0058 #define SDRAM_CASL              2.5     /* in clocks */
0059 #define SDRAM_TRCD              20      /* in ns */
0060 #define SDRAM_TRP               20      /* in ns */
0061 #define SDRAM_TRFC              75      /* in ns */
0062 #define SDRAM_TREFI             7800    /* in ns */
0063 #endif /* defined(HAS_LOW_LEVEL_INIT) */
0064
0065 extern uint8_t _DataRom[];
0066 extern uint8_t _DataRam[];
0067 extern uint8_t _DataEnd[];
0068 extern uint8_t _BssStart[];
0069 extern uint8_t _BssEnd[];
0070 extern uint8_t _BootFlashBase[];
0071 extern uint8_t _CodeFlashBase[];
0072 extern uint8_t RamBase[];
0073
0074 void gpio_init(void);
0075 void fbcs_init(void);
0076 void sdramc_init(void);
0077 void mcf548x_init(void);
0078
0079
0080 void mcf548x_init(void)
0081 {
0082     size_t i;
0083
0084 #if defined(HAS_LOW_LEVEL_INIT)
0085     /* set XLB arbiter timeouts */
0086     MCF548X_XLB_ADRTO = 0x00000100;
0087     MCF548X_XLB_DATTO = 0x00000100;
0088     MCF548X_XLB_BUSTO = 0x00000100;
0089 #endif
0090
0091     gpio_init();
0092 #if defined(HAS_LOW_LEVEL_INIT)
0093     fbcs_init();
0094     sdramc_init();
0095 #endif /* defined(HAS_LOW_LEVEL_INIT) */
0096
0097     /* Copy the vector table to RAM if necessary */
0098     if (bsp_vector0_size == bsp_vector1_size) {
0099       memcpy(bsp_vector1_begin, bsp_vector0_begin, (size_t) bsp_vector1_size);
0100       m68k_set_vbr((uint32_t)bsp_vector1_begin);
0101     }
0102
0103     /* Move initialized data from ROM to RAM. */
0104     if (bsp_section_data_begin != bsp_section_data_load_begin) {
0105       memcpy(
0106         bsp_section_data_begin,
0107         bsp_section_data_load_begin,
0108         (size_t) bsp_section_data_size
0109       );
0110     }
0111
0112     /* Zero uninitialized data */
0113     memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
0114
0115     for (i = 8; i < RTEMS_ARRAY_SIZE(mcf548x_intc_icr_init_values); ++i) {
0116       volatile uint8_t *icr = &MCF548X_INTC_ICR0;
0117
0118       icr[i] = mcf548x_intc_icr_init_values[i];
0119     }
0120 }
0121 /********************************************************************/
0122 #if defined(HAS_LOW_LEVEL_INIT)
0123 void
0124 fbcs_init (void)
0125 {
0126 #ifdef M5484FIREENGINE
0127
0128 volatile uint32_t cscr, clk_ratio, fb_period, ws;
0129
0130 /* boot flash already valid ? */
0131 if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V))
0132   {
0133
0134     /*
0135      * Boot Flash
0136      */
0137     MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase));
0138
0139     cscr = (0
0140             | MCF548X_FBCS_CSCR_ASET(1)
0141             | MCF548X_FBCS_CSCR_WRAH(0)
0142             | MCF548X_FBCS_CSCR_RDAH(0)
0143             | MCF548X_FBCS_CSCR_AA
0144             | MCF548X_FBCS_CSCR_PS_16);
0145
0146     /*
0147      * Determine the necessary wait states based on the defined system
0148      * period (XLB clock period) and the CLKIN to XLB ratio.
0149      * The boot flash has a max access time of 110ns.
0150      */
0151     clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7;
0152     fb_period = SYSTEM_PERIOD * clk_ratio;
0153     ws = 110 / fb_period;
0154
0155     MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws);
0156     MCF548X_FBCS_CSMR0 = (0
0157                           | MCF548X_FBCS_CSMR_BAM_2M
0158                           | MCF548X_FBCS_CSMR_V);
0159
0160   }
0161
0162 /* code flash already valid ? */
0163 if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))
0164   {
0165
0166     /*
0167      * Code Flash
0168      */
0169     MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase));
0170
0171     /*
0172      * Determine the necessary wait states based on the defined system
0173      * period (XLB clock period) and the CLKIN to XLB ratio.
0174      * The user/code flash has a max access time of 120ns.
0175      */
0176     ws = 120 / fb_period;
0177     MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws);
0178     MCF548X_FBCS_CSMR1 = (0
0179                           | MCF548X_FBCS_CSMR_BAM_16M
0180                           | MCF548X_FBCS_CSMR_V);
0181     }
0182
0183 #endif
0184 }
0185 #endif /* defined(HAS_LOW_LEVEL_INIT) */
0186
0187 /********************************************************************/
0188 #if defined(HAS_LOW_LEVEL_INIT)
0189 void
0190 sdramc_init (void)
0191 {
0192
0193     /*
0194      * Check to see if the SDRAM has already been initialized
0195      * by a run control tool
0196      */
0197     if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF))
0198     {
0199         /*
0200          * Basic configuration and initialization
0201          */
0202         MCF548X_SDRAMC_SDRAMDS = (0
0203             | MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
0204             | MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
0205             | MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
0206             | MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
0207             | MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)
0208             );
0209         MCF548X_SDRAMC_CS0CFG = (0
0210             | MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(RamBase))
0211             | MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE)
0212             );
0213         MCF548X_SDRAMC_SDCFG1 = (0
0214             | MCF548X_SDRAMC_SDCFG1_SRD2RW(7)
0215             | MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
0216             | MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
0217             | MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))
0218             | MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))
0219             | MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))
0220             | MCF548X_SDRAMC_SDCFG1_WTLAT(3)
0221             );
0222         MCF548X_SDRAMC_SDCFG2 = (0
0223             | MCF548X_SDRAMC_SDCFG2_BRD2PRE(4)
0224             | MCF548X_SDRAMC_SDCFG2_BWT2RW(6)
0225             | MCF548X_SDRAMC_SDCFG2_BRD2WT(7)
0226             | MCF548X_SDRAMC_SDCFG2_BL(7)
0227             );
0228
0229         /*
0230          * Precharge and enable write to SDMR
0231          */
0232         MCF548X_SDRAMC_SDCR = (0
0233             | MCF548X_SDRAMC_SDCR_MODE_EN
0234             | MCF548X_SDRAMC_SDCR_CKE
0235             | MCF548X_SDRAMC_SDCR_DDR
0236             | MCF548X_SDRAMC_SDCR_MUX(1)
0237             | MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
0238             | MCF548X_SDRAMC_SDCR_IPALL
0239             );
0240
0241         /*
0242          * Write extended mode register
0243          */
0244         MCF548X_SDRAMC_SDMR = (0
0245             | MCF548X_SDRAMC_SDMR_BNKAD_LEMR
0246             | MCF548X_SDRAMC_SDMR_AD(0x0)
0247             | MCF548X_SDRAMC_SDMR_CMD
0248             );
0249
0250         /*
0251          * Write mode register and reset DLL
0252          */
0253         MCF548X_SDRAMC_SDMR = (0
0254             | MCF548X_SDRAMC_SDMR_BNKAD_LMR
0255             | MCF548X_SDRAMC_SDMR_AD(0x163)
0256             | MCF548X_SDRAMC_SDMR_CMD
0257             );
0258
0259         /*
0260          * Execute a PALL command
0261          */
0262         MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL;
0263
0264         /*
0265          * Perform two REF cycles
0266          */
0267         MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
0268         MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;
0269
0270         /*
0271          * Write mode register and clear reset DLL
0272          */
0273         MCF548X_SDRAMC_SDMR = (0
0274             | MCF548X_SDRAMC_SDMR_BNKAD_LMR
0275             | MCF548X_SDRAMC_SDMR_AD(0x063)
0276             | MCF548X_SDRAMC_SDMR_CMD
0277             );
0278
0279         /*
0280          * Enable auto refresh and lock SDMR
0281          */
0282         MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN;
0283         MCF548X_SDRAMC_SDCR |= (0
0284             | MCF548X_SDRAMC_SDCR_REF
0285             | MCF548X_SDRAMC_SDCR_DQS_OE(0xF)
0286             );
0287     }
0288
0289 }
0290 #endif /* defined(HAS_LOW_LEVEL_INIT) */
0291
0292 /********************************************************************/
0293 void
0294 gpio_init(void)
0295 {
0296
0297 #ifdef M5484FIREENGINE
0298
0299     /*
0300      * Enable Ethernet signals so that, if a cable is plugged into
0301      * the ports, the lines won't be floating and potentially cause
0302      * erroneous transmissions
0303      */
0304     MCF548X_GPIO_PAR_FECI2CIRQ = (0
0305
0306         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
0307         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
0308         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII
0309         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17
0310
0311         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
0312         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
0313         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII
0314         | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07
0315         );
0316
0317 #endif
0318     /*
0319      * make sure the "edge port" has all interrupts disabled
0320      */
0321     MCF548X_EPORT_EPIER = 0;
0322 }