genmcf548x/start/cache.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2007, 2014 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp.h>
0029
0030 #define CPU_DATA_CACHE_ALIGNMENT 16
0031
0032 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 16
0033
0034 /*
0035  * There is no complete cache lock (only 2 ways of 4 can be locked)
0036  */
0037 static inline void _CPU_cache_freeze_data(void)
0038 {
0039   /* Do nothing */
0040 }
0041
0042 static inline void _CPU_cache_unfreeze_data(void)
0043 {
0044   /* Do nothing */
0045 }
0046
0047 static inline void _CPU_cache_freeze_instruction(void)
0048 {
0049   /* Do nothing */
0050 }
0051
0052 static inline void _CPU_cache_unfreeze_instruction(void)
0053 {
0054   /* Do nothing */
0055 }
0056
0057 static inline void _CPU_cache_enable_instruction(void)
0058 {
0059   bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
0060 }
0061
0062 static inline void _CPU_cache_disable_instruction(void)
0063 {
0064   bsp_cacr_set_flags( MCF548X_CACR_IDCM);
0065 }
0066
0067 static inline void _CPU_cache_invalidate_entire_instruction(void)
0068 {
0069   bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
0070 }
0071
0072 static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
0073 {
0074   uint32_t a = (uint32_t) addr & ~0x3;
0075
0076   __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
0077   __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
0078   __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
0079   __asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
0080 }
0081
0082 static inline void _CPU_cache_enable_data(void)
0083 {
0084   bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
0085 }
0086
0087 static inline void _CPU_cache_disable_data(void)
0088 {
0089   bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
0090 }
0091
0092 static inline void _CPU_cache_invalidate_entire_data(void)
0093 {
0094   bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
0095 }
0096
0097 static inline void _CPU_cache_invalidate_1_data_line( const void *addr)
0098 {
0099   uint32_t a = (uint32_t) addr & ~0x3;
0100
0101   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
0102   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
0103   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
0104   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
0105 }
0106
0107 static inline void _CPU_cache_flush_1_data_line( const void *addr)
0108 {
0109   uint32_t a = (uint32_t) addr & ~0x3;
0110
0111   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
0112   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
0113   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
0114   __asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
0115 }
0116
0117 static inline void _CPU_cache_flush_entire_data( void)
0118 {
0119   uint32_t line = 0;
0120
0121   for (line = 0; line < 512; ++line) {
0122     _CPU_cache_flush_1_data_line( (const void *) (line * 16));
0123   }
0124 }
0125
0126 #include "../../../shared/cache/cacheimpl.h"