genmcf548x/start/bspstart.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * RTEMS generic mcf548x BSP
0005  *
0006  * The file contains the startup code of generic MCF548x BSP
0007  *
0008  * Parts of the code has been derived from the "dBUG source code"
0009  * package Freescale is providing for M548X EVBs. The usage of
0010  * the modified or unmodified code and it's integration into the
0011  * generic mcf548x BSP has been done according to the Freescale
0012  * license terms.
0013  *
0014  * The Freescale license terms can be reviewed in the file
0015  *
0016  * The generic mcf548x BSP has been developed on the basic
0017  * structures and modules of the av5282 BSP.
0018  */
0019
0020 /*
0021  * Copyright (c) 2007 embedded brains GmbH & Co. KG
0022  *
0023  * Redistribution and use in source and binary forms, with or without
0024  * modification, are permitted provided that the following conditions
0025  * are met:
0026  * 1. Redistributions of source code must retain the above copyright
0027  *    notice, this list of conditions and the following disclaimer.
0028  * 2. Redistributions in binary form must reproduce the above copyright
0029  *    notice, this list of conditions and the following disclaimer in the
0030  *    documentation and/or other materials provided with the distribution.
0031  *
0032  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0033  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0034  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0035  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0036  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0037  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0038  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0039  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0040  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0041  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0042  * POSSIBILITY OF SUCH DAMAGE.
0043  */
0044
0045 #include <bsp.h>
0046 #include <bsp/bootcard.h>
0047
0048 extern uint32_t _CPU_cacr_shadow;
0049
0050 /*
0051 * These labels (!) are defined in the linker command file or when the linker is
0052 * invoked.
0053 * NOTE: The information (size) is the address of the object, not the object
0054 * itself.
0055 */
0056
0057 extern char _SdramBase[];
0058 extern char _BootFlashBase[];
0059 extern char _CodeFlashBase[];
0060 extern char _SdramSize[];
0061 extern char _BootFlashSize[];
0062 extern char _CodeFlashSize[];
0063 extern char _TopRamReserved [];
0064 extern char WorkAreaBase [];
0065
0066 /*
0067  * CPU-space access
0068  */
0069 #define m68k_set_acr2(_acr2) __asm__ volatile ("movec %0,#0x0005" : : "d" (_acr2))
0070 #define m68k_set_acr3(_acr3) __asm__ volatile ("movec %0,#0x0007" : : "d" (_acr3))
0071
0072 /*
0073  * Set initial CACR mode, mainly enables branch/instruction/data cache.  The
0074  * FPU must be switched on in the BSP startup code since the
0075  * _Thread_Start_multitasking() will restore the floating-point context of the
0076  * initialization task if necessary.
0077  */
0078 static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
0079   | MCF548X_CACR_BEC /* enable branch cache */
0080   | MCF548X_CACR_IEC /* enable instruction cache */
0081   | MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH)
0082       /* set data cache mode to write-through */
0083   | MCF548X_CACR_DESB /* enable data store buffer */
0084   | MCF548X_CACR_DDSP /* data access only in supv. mode */
0085   | MCF548X_CACR_IDSP; /* instr. access only in supv. mode */
0086
0087 /*
0088  * CACR maintenance functions
0089  */
0090
0091 void bsp_cacr_set_flags( uint32_t flags)
0092 {
0093   rtems_interrupt_level level;
0094
0095   rtems_interrupt_disable( level);
0096   _CPU_cacr_shadow |= flags;
0097   m68k_set_cacr( _CPU_cacr_shadow);
0098   rtems_interrupt_enable( level);
0099 }
0100
0101 void bsp_cacr_set_self_clear_flags( uint32_t flags)
0102 {
0103   rtems_interrupt_level level;
0104   uint32_t cacr = 0;
0105
0106   rtems_interrupt_disable( level);
0107   cacr = _CPU_cacr_shadow | flags;
0108   m68k_set_cacr( cacr);
0109   rtems_interrupt_enable( level);
0110 }
0111
0112 void bsp_cacr_clear_flags( uint32_t flags)
0113 {
0114   rtems_interrupt_level level;
0115
0116   rtems_interrupt_disable( level);
0117   _CPU_cacr_shadow &= ~flags;
0118   m68k_set_cacr( _CPU_cacr_shadow);
0119   rtems_interrupt_enable( level);
0120 }
0121
0122 /*
0123  * Coldfire acr and mmu settings
0124  */
0125  static void acr_mmu_mapping(void)
0126    {
0127
0128   /*
0129    * Cache disabled for internal register area (256 kB).
0130    * Choose the smallest maskable size of 1MB.
0131    */
0132   m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
0133                 MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
0134                 MCF548X_ACR_E                                                |
0135                 MCF548X_ACR_SP               /* supervisor protection */     |
0136                 MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
0137                 MCF548X_ACR_CM(CM_OFF_PRECISE));
0138
0139 #ifdef M5484FIREENGINE
0140
0141
0142   /*
0143    * Cache enabled for entire SDRAM (64 MB)
0144    */
0145   m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
0146                 MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
0147                 MCF548X_ACR_E                                                |
0148                 MCF548X_ACR_SP               /* supervisor protection */     |
0149                 MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
0150                 MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
0151
0152   /*
0153    * Cache enabled for entire boot flash (2 MB)
0154    */
0155   m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
0156                 MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
0157                 MCF548X_ACR_E                                                |
0158                 MCF548X_ACR_SP               /* supervisor protection */     |
0159                 MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
0160                 MCF548X_ACR_CM(CM_ON_COPYBACK));
0161
0162   /*
0163    * Cache enabled for entire code flash (16 MB)
0164    */
0165   m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
0166                 MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
0167                 MCF548X_ACR_E                                                |
0168                 MCF548X_ACR_SP               /* supervisor protection */     |
0169                 MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
0170                 MCF548X_ACR_CM(CM_ON_COPYBACK));
0171 #endif
0172
0173    }
0174
0175 /*
0176  *  bsp_start
0177  *
0178  *  This routine does the bulk of the system initialisation.
0179  */
0180 void bsp_start( void )
0181 {
0182   /* Initialize CACR shadow register */
0183   _CPU_cacr_shadow = BSP_CACR_INIT;
0184
0185   /*
0186    * Load the shadow variable of CACR with initial mode and write it to the
0187    * CACR.  Interrupts are still disabled, so there is no need for surrounding
0188    * rtems_interrupt_enable() / rtems_interrupt_disable().
0189    */
0190   m68k_set_cacr( _CPU_cacr_shadow);
0191
0192   /*
0193    * do mapping of acr's and/or mmu
0194    */
0195   acr_mmu_mapping();
0196 }
0197
0198
0199 /*
0200  * Get the XLB clock speed
0201  */
0202 uint32_t get_CPU_clock_speed(void)
0203 {
0204     return (uint32_t)BSP_CPU_CLOCK_SPEED;
0205 }