genmcf548x/irq/irq.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2013, 2021 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp/irq-generic.h>
0029
0030 #include <mcf548x/mcf548x.h>
0031
0032 void asm_default_interrupt(void);
0033
0034 typedef void (*void_func)(void);
0035
0036 static uint32_t vector_to_reg(rtems_vector_number vector)
0037 {
0038   return ((vector + 32U) >> 5) & 0x1;
0039 }
0040
0041 static uint32_t vector_to_bit(rtems_vector_number vector)
0042 {
0043   return 1U << (vector & 0x1fU);
0044 }
0045
0046 static volatile uint32_t *vector_to_imr(rtems_vector_number vector)
0047 {
0048   volatile uint32_t *imr = &MCF548X_INTC_IMRH;
0049
0050   return &imr[vector_to_reg(vector)];
0051 }
0052
0053 static rtems_vector_number exception_vector_to_vector(
0054   rtems_vector_number exception_vector
0055 )
0056 {
0057   return exception_vector - 64U;
0058 }
0059
0060 static rtems_vector_number vector_to_exception_vector(
0061   rtems_vector_number vector
0062 )
0063 {
0064   return vector + 64U;
0065 }
0066
0067 rtems_status_code bsp_interrupt_get_attributes(
0068   rtems_vector_number         vector,
0069   rtems_interrupt_attributes *attributes
0070 )
0071 {
0072   return RTEMS_SUCCESSFUL;
0073 }
0074
0075 rtems_status_code bsp_interrupt_is_pending(
0076   rtems_vector_number vector,
0077   bool               *pending
0078 )
0079 {
0080   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0081   bsp_interrupt_assert(pending != NULL);
0082   *pending = false;
0083   return RTEMS_UNSATISFIED;
0084 }
0085
0086 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0087 {
0088   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0089   return RTEMS_UNSATISFIED;
0090 }
0091
0092 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0093 {
0094   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0095   return RTEMS_UNSATISFIED;
0096 }
0097
0098 rtems_status_code bsp_interrupt_vector_is_enabled(
0099   rtems_vector_number vector,
0100   bool               *enabled
0101 )
0102 {
0103   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0104   bsp_interrupt_assert(enabled != NULL);
0105   *enabled = false;
0106   return RTEMS_UNSATISFIED;
0107 }
0108
0109 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0110 {
0111   volatile uint32_t *imr = vector_to_imr(vector);
0112   uint32_t bit = vector_to_bit(vector);
0113   rtems_interrupt_level level;
0114
0115   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0116
0117   rtems_interrupt_disable(level);
0118   *imr &= ~bit;
0119   rtems_interrupt_enable(level);
0120
0121   return RTEMS_SUCCESSFUL;
0122 }
0123
0124 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0125 {
0126   volatile uint32_t *imr = vector_to_imr(vector);
0127   uint32_t bit = vector_to_bit(vector);
0128   rtems_interrupt_level level;
0129
0130   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0131
0132   rtems_interrupt_disable(level);
0133   *imr |= bit;
0134   rtems_interrupt_enable(level);
0135
0136   return RTEMS_SUCCESSFUL;
0137 }
0138
0139 rtems_status_code bsp_interrupt_set_priority(
0140   rtems_vector_number vector,
0141   uint32_t priority
0142 )
0143 {
0144   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0145   return RTEMS_UNSATISFIED;
0146 }
0147
0148 rtems_status_code bsp_interrupt_get_priority(
0149   rtems_vector_number vector,
0150   uint32_t *priority
0151 )
0152 {
0153   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0154   bsp_interrupt_assert(priority != NULL);
0155   return RTEMS_UNSATISFIED;
0156 }
0157
0158 static void set_exception_handler(rtems_vector_number vector, void_func handler)
0159 {
0160   void **vbr;
0161   void_func *exception_table;
0162
0163   m68k_get_vbr(vbr);
0164
0165   exception_table = (void_func *)vbr;
0166
0167   exception_table[vector_to_exception_vector(vector)] = handler;
0168 }
0169
0170 static void dispatch_handler(rtems_vector_number exception_vector)
0171 {
0172   bsp_interrupt_handler_dispatch_unchecked(
0173     exception_vector_to_vector(exception_vector)
0174   );
0175 }
0176
0177 void mcf548x_interrupt_vector_install(rtems_vector_number vector)
0178 {
0179   _ISR_Vector_table[vector_to_exception_vector(vector)]
0180     = dispatch_handler;
0181   set_exception_handler(vector, _ISR_Handler);
0182 }
0183
0184 void mcf548x_interrupt_vector_remove(rtems_vector_number vector)
0185 {
0186   set_exception_handler(vector, asm_default_interrupt);
0187 }